1 UNIT - I Register Transfer The term Register Transfer refers to the availability of hardware logic circuits that can perform a given micro - operation and transfer the result of the operation to the same or another register. Most of the standard notations used for specifying operations on various registers are stated below. o The memory address register is designated by MAR o Program Counter PC holds the next instruction's address. o Instruction Register IR holds the instruction being executed. o R1 (Processor Register). o We can also indicate individual bits by placing them in parenthesis. For instance, PC (8 - 15), R2 (5), etc. o Data Transfer from one register to another register is represe nted in symbolic form by means of replacement operator. For instance, the following statement denotes a transfer of the data of register R1 into register R2. Register Transfer Language (RTL) In symbolic notation, it is used to describe the micro - operations transfer among registers. It is a kind of intermediate representation (IR) that is very close to assembly language, such as that which is used in a compiler. The term “Register Transfer” c an perform micro - operations and transfer the result of operation to the same or other register. Micro - operations : The operation executed on the data store in registers are called micro - operations. They are detailed low - level instructions used in some de signs to implement complex machine instructions. Register Transfer : The information transformed from one register to another register is represented in symbolic form by replacement operator is called Register Transfer. Replacement Operator : In the st atement, R2 < - R1, < - acts as a replacement operator. This statement defines the transfer of content of register R1 into register R2. There are various methods of RTL – 1. General way of representing a register is by the name of the register enclosed in a rectangular box as shown in (a). 2. Register is numbered in a sequence of 0 to (n - 1) as shown in (b). 3. The numbering of bits in a register can be marked on the top of the box as shown in (c). 2 4. A 16 - bit register PC is divided into 2 parts - Bits (0 to 7) are assigned with lower byte of 16 - bit address and bits (8 to 15) are assigned with higher bytes of 16 - bit address as shown in (d). Basic symbols of RTL : Register Transfer Operations: The operation performed on the data stored in the registers are referred to as register transfer operations. There are different types of register transfer operations: 1. Simple Transfer – R2 < - R1 The content of R1 are copied into R2 without affecting the content of R1. It is an unconditional type of transfer operation. 2. Conditional Transfer – Symbol Description Example Letters and Numbers Denotes a Register MAR, R1, R2 ( ) Denotes a part of register R1(8 - bit) R1(0 - 7) < - Denotes a transfer of information R2 < - R1 , Specify two micro - operations of Register Transfer R1 < - R2 R2 < - R1 : Denotes conditional operations P : R2 < - R1 if P=1 Naming Operator (:=) Denotes another name for an already existing register/alias Ra := R1 3 P: R2 ← R1 It indicates that if P=1, then the content of R1 is transferred to R2. It is a unidirectional operation. 3. Simultaneous Operations – If 2 or more operations are to occur simultaneously then they are separated with comma (,) If the control function P=1, then load the content of R1 into R2 and at the same clock load the content of R2 into R1 Arithmetic MicroInstructions : The four basic arithmetic operations are addition, subtraction, multiplication, and division. Most computers provide instructions for all four operations. Typical Arithmetic Instructions – Name Mnemonic Example Explanation Increment INC INC B It will increment the register B by 1 B< - B+1 Decrement DEC DEC B It will decrement the register B by 1 B< - B - 1 Add ADD ADD B It will add contents of register B to the contents of the accumulator and store the result in the accumulator AC< - AC+B Subtract SUB SUB B It will subtract the contents of register B from the contents of the accumulator and store the result in the 4 accumulator AC< - AC - B Multiply MUL MUL B It will multiply the contents of register B with the contents of the accumulator and store the result in the accumulator AC< - AC*B Divide DIV DIV B It will divide the contents of register B with the contents of the accumulator and store the quotient in the accumulator AC< - AC/B Add with carry ADDC ADDC B It will add the contents of register B and the carry flag with the contents of the accumulator and store the result in the accumulator AC< - AC+B+Carry flag Subtract with borrow SUBB SUBB B It will subtract the contents of register B and the carry flag from the contents of the accumulator and store the result in the accumulator AC< - AC - B - Carry flag Negate(2’s complement) NEG NEG B It will negate a value by finding 2’s complement of its single oper and. This means simply operand by - 1. B< - B’+1 Logical and Bit Manipulation Instructions : 5 Logical instructions perform binary operations on strings of bits stored in registers. They are useful for manipulating individual bits or a group of bits. Typical Logical and Bit Manipulation Instructions – Name Mnemon ic Example Explanation Clear CLR CLR It will set the accumulator to 0 AC< - 0 Complement COM COM A It will complement the accumulator AC< - (AC)’ AND AND AND B It will AND the contents of register B with the contents of accumulator and store it in the accumulator AC< - AC AND B OR OR OR B It will OR the contents of register B with the contents of accumulator and store it in the accumulator AC< - AC OR B Exclusive - OR XOR XOR B It will XOR the contents of register B with the contents of the accumulator and store it in the accumulator AC< - AC XOR B Clear carry CLRC CLRC It will set the carry flag to 0 Carry flag< - 0 Set carry SETC SETC It will set the carry flag to 1 Carry flag< - 1 Complement carry COM C COMC It will complement the carry flag Carry flag< - (Carry flag)’ Enable interrupt EI EI It will enable the interrupt Disable interrupt DI DI It will disable the interrupt Shift Micro - Instructions : Shifts are operations in which the bits of a word are moved to the left or right. Shift 6 instructions may specify either logical shifts, arithmetic shifts, or rotate - type operations. Typical Shift Instructions – Name Mnemonic Logical shift right SHR Logical shift left SHL Arithmetic shift right SHRA Arithmetic shift left SHLA Rotate right ROR Rotate left ROL Rotate right through carry RORC Rotate left through carry ROLC Logical Shift Left – In this shift one position moves each bit to the left one by one. The Empty least significant bit (LSB) is filled with zero (i.e, the serial input), and the most significant bit (MSB) is rejected. Right Logical Shift – In this one position moves each bit to the right one by one and the least significant bit(LSB) is rejected and the empty MSB is filled with zero. 7 Left Arithmetic Shift – In this one position moves each bit to the left one by one. The empty least significant bit (LSB) is filled with zero and the most significant bit (MSB) is re jected. Same as the Left Logical Shift. Right Arithmetic Shift – In this one position moves each bit to the right one by one and the least significant bit is rejected and the empty MSB is filled with the value of the previous MSB. Left Circular Shift – 8 Right Circular Shift – Computer Registers Registers are a type of computer memory used to quickly accept, store, and transfer data and instructions that are being used immediately by the CPU. The registers used by the CPU are often termed as Processo r registers. A processor register may hold an instruction, a storage address, or any data (such as bit sequence or individual characters). The computer needs processor registers for manipulating data and a register for holding a memory address. The registe r holding the memory location is used to calculate the address of the next instruction after the execution of the current instruction is completed. Register Symbol Number of bits Function Data register DR 16 Holds memory operand Address register AR 12 Holds address for the memory Accumulator AC 16 Processor register 9 Instruction register IR 16 Holds instruction code Program counter PC 12 Holds address of the instruction Temporary register TR 16 Holds temporary data Input register INPR 8 Carries input character Output register OUTR 8 Carries output character The following image shows the register and memory configuration for a basic computer. o The Memory unit has a capacity of 4096 words, and each word contains 16 bits. o The Data Register (DR) contains 16 bits which hold the operand read from the memory location. o The Memory Address Register (MAR) contains 12 bits which hold the address for the memory location. o The Program Counter (PC) also contains 12 bits which hold the address of the next inst ruction to be read from memory after the current instruction is executed. o The Accumulator (AC) register is a general purpose processing register. o The instruction read from memory is placed in the Instruction register (IR). o The Temporary Register (TR) is used for holding the temporary data during the processing. o The Input Registers (IR) holds the input characters given by the user. o The Output Registers (OR) holds the output after processing the input data. 10 Common Bus System We shall study the common bus system of a very basic computer in this article. A basic computer has 8 registers, memory unit and a control unit. The diagram of the common bus system is as shown below. Connections: The outputs of all the registers except the OUTR (output register) are connected to the common bus. The output selected depends upon the binary value of variables S2, S1 and S0. The lines from common bus are connected to the inputs of the registers and memory. A register receives the information from the bus when its LD ( load) input is activated while in case of memory the Write input must be enabled to receive the information. The contents of memory are placed onto the bus when its Read input is activated. Various Registers: 4 registers DR, AC, IR and TR have 16 bits an d 2 registers AR and PC have 12 bits. The INPR and OUTR have 8 bits each. The INPR receives character from input device and delivers it to the AC while the OUTR receives character from AC and transfers it to the 11 output device. 5 registers have 3 control in puts LD (load), INR (increment) and CLR (clear). These types of registers are similar to a binary counter. Adder and logic circuit: The adder and logic circuit provides the 16 inputs of AC. This circuit has 3 sets of inputs. One set comes from the outputs of AC which implements register micro operations. The other set comes from the DR (data register) which are used to perform arithmetic and logic micro operations. The result of these operations is sent to AC while the end around carry is stored in E as sh own in diagram. The third set of inputs is from INPR. Instruction set An instruction is a set of codes that the computer processor can understand. The code is usually in 1s and 0s, or machine language. It contains instructions or tasks that control the mo vement of bits and bytes within the processor. Example of some instruction sets −  ADD − Add two numbers together.  JUMP − Jump to designated RAM address.  LOAD − Load information from RAM to the CPU. Types of Instruction Set 1.Reduced Instruction set Computer (RISC) 2.Complex Instruction Set Computer (CISC) Instruction Cycle Each computer’s CPU can have different cycles based on different instruction sets, but will be similar to the following cycle: Fetch Stage: The next instruction is fetched from t he memory address that is currently stored in the program counter and stored in the instruction register. At the end of the fetch operation, the PC points to the next instruction that will be read in the next cycle.  Fetch Cycle: Fetch the instruction fro m memory  Decode Cycle: Decode the instruction. Then Read the effective address from the memory  Execute Cycle: Execute the instruction. 12 Registers Involved In Each Instruction Cycle Following are the different types of registers involved in each instruction cycle: 1. Memory address registers(MAR): It is connected to the address lines of the system bus. It specifies the address in memory for a read or write operation. 2. Memory Buffer Register(MBR): It is connected to the data lines of the system bus. It contains t he value to be stored in memory or the last value read from the memory. 3. Program Counter(PC): Holds the address of the next instruction to be fetched. 4. Instruction Register(IR): Holds the last instruction fetched. Role of Registers Involved in Instruction Cy cle The program counter (PC) is a special register that holds the memory address of the next instruction to be executed. During the fetch stage, the address stored in the PC is copied into the memory address register (MAR) and then the PC is incremented in order to “point” to the memory address of the next instruction to be executed. The CPU then takes the instruction at the memory address described by the MAR and copies it into the memory data register (MDR). The MDR also acts as a two - way register that h olds data fetched from memory or data waiting to be stored in memory (it is also known as the memory buffer register (MBR) because of this). Eventually, the instruction in the MDR is copied into the current instruction register (CIR) which acts as a tempor ary holding ground for the instruction that has just been fetched from memory. During the decode stage, the control unit (CU) will decode the instruction in the CIR. The CU then sends signals to other components within the CPU, such as the arithmetic logic unit (ALU) and the floating - point unit (FPU). The ALU performs arithmetic operations such as addition and subtraction and also multiplication by repeated addition and division via repe ated subtraction. It also performs logic operations such as AND, OR, NOT, and binary shifts as well. The FPU is reserved for performing floating - point operations. Components of Instruc tion Cycle Following are the main components of every instruction cycle: 1. Fetch Cycle The fetching of instruction is the first phase. The fetch instruction is common for each instruction executed in a central processing unit. In this phase, the central processing unit sends the PC to MAR and then sends the READ command into a control bus. After sending a read command on the data bus, the memory returns the instruction, which is stored at that particular address in the memory. Then, the CPU copies data fr om the data bus into MBR and then copies the data from MBR to registers. After all this, the pointer is incremented to the next memory location so that the next instruction can be fetched from memory. 2. Decode Cycle The decoding of instruction is the seco nd phase. In this phase, the CPU determines which instruction is fetched from the instruction and what action needs to be performed on the instruction. The opcode for the instruction is also fetched from memory and decodes the related operation which needs to be performed for the related instruction. The reading of an effective address is the third phase. This phase deals with the decision of the operation. The operation can be of any type of memory type non - memory type operation. Memory instruction can be categorized into two categories: direct memory instruction and indirect memory instruction. 3. Execute Cycle The execution of instruction is the last phase. In this stage, the instruction is finally executed. The instruction is executed, and the result of the instruction is stored in the register. After the execution of an instruction, the CPU prepares itself for the execution of the next instruction. For every instruction, the execution time is calculated, which is used to tell the processing speed of the processor. Computer Organization | Basic Computer Instructions The basic computer has 16 - bit instruction register (IR) which can denote either memory reference or register reference or input - output instruction. 13 1. Memory Reference Instruction – These instructions refer to memory address as an operand. The other operand is always accumulator. Specifies 12 - bit address, 3 - bit opcode (other than 111) and 1 - bit addressing mode for direct and indirect addressing. Example – IR register contains = 0001XXXXXXXX XXXX, i.e. ADD after fetching and decoding of instruction we find out that it is a memory reference instruction for ADD operation. Hence, DR ← M[AR] AC ← AC + DR, SC ← 0 2. Register Reference – These instructions perform operations on registers rather than memory addresses. The IR(14 – 12) is 111 (differentiates it from memory reference) and IR(15) is 0 (differentiates it from input/output instructions). The rest 12 bits specify register operation. Example – IR register contains = 0111001000000000, i.e. CMA after fetch and decode cycle we find out that it is a register reference instruction for complement accumulator. Hence, AC ← ~AC 3. Input/Output – These instructions are for communication between computer and outside environment. The IR(14 – 12) is 111 (differentiates it from memory reference) and IR(15) is 1 (differentiates it from register reference instructions). The rest 12 bits specify I/O operation. Example – IR register contains = 1111100000000000, i.e. INP after fetch and decode cycle we find out that it is an input/output instruction for inputing character. Hence, INPUT character from peripheral device. INPUT - OUTPUT AND INTERRUPT An interrupt I/O is a process of data transfer in which an external device or a peripheral informs the CPU that it is ready for communication and requests the attention of the CPU. 14 I/O Configuration The terminals send and receive serial information. Each portion of serial data has eight bits of alphanumeric code, where the leftmost bit is continually 0. The serial data from the input register is transferred into the input register INPR. The output register OUTR can save the serial data for the printer. These two registers interact with the Accumulator (AC) in parallel and with a communication interface in a serial s tructure. The Input/Output configuration is displayed in the figure. The transmitter interface gets serial data from the keyboard and sends it to INPR. The receiver interface gets data from OUTR and transfers it to the printer serially. The input/output re gisters include eight bits. The FGI is a 1 - bit input flag, which is a control flip - flop. The flag bit is set to 1 when new data is accessible in the input device and is cleared to 0 when the data is approved through the device. When a key is clicked on the keyboard, the alphanumeric code equivalent to the key is shifted to INPR and the input flag FGI is set to 0. The data in INPR cannot be modified considering the flag is set. The device tests the flag bit; if it is 1, the data from INPR is sent in parallel into AC, and FGI is cleared to 0. The output register OUTR works equivalent to the input register INPR. The flow of data by the OUTR is the opposite of INPR. Therefore, the output flag FGO is set to 1 originally. The device tests the flag bit; if it is 1, the data from AC is sent in parallel to OUTR, and FGO is cleared to 0. The new data cannot be loaded into OUTR when the FGO is 0 because this condition denotes that the output device is in the procedure of printing a character. Input Register : The INPR in put register is a register that includes eight bits and influences alphanumeric input data. The 1 - bit input flag FGI is a control flip - flop. When new data is accessible in the input device, the flag bit is set to 1. It is cleared to 0 when the data is appr oved by the device. The flag is needed to synchronize the timing rate difference between the input device and the computer. The process of data transfer is as follows − 15  The input flag FGI is set to 0. When a user clicks any key on the keyboard, an 8 - bit al phanumeric code is transferred into INPR and the input flag FGI is set to 1.  The device tests the flag bit. If the bit is 1, thus the data from INPR is transferred to AC and together FGI is cleared to 0.  Then the flag is cleared, new data can be transferred into INPR by introducing another key. Output Register : The working of the output register OUTR is equivalent to that of the input register INPR, therefore the control of data flow is in the opposite. The procedure of data transfer is as follows −  The output flag FGO is set to 1.  The device tests the flag bit. If the bit is 1, the data from AC is shared to OUTR and concurrently FGO is cleared to 0.  After that, the output device receives the coded 8 - bit data and prints the matching character.  Afte r this operation is done, the output device sets the FGO to 1. Design of Basic Computer The basic computer comprises the following hardware components: 1. Memory Unit with 4096 words of 16 bits each 2. Eight registers 1. AR (Address Register): In indirect or direct addressing, the processor needs to keep track of the locations in the memory that it is addressing. For this purpose, the processor uses Address Register(AR). 2. PC (Program Counter): It holds the memory address of the next instruction to get. 3. DR (Data Register): It is used to keep the operand, found using direct or indirect addressing. The processor uses the value stored in DR as data for its operations. 4. AC (Accumulator): It is a general - purpose register. It can be referred to load the AC with a specif ic memory or storing the AC contents into one particular memory location. 5. IR (Instruction Register): It stores the instruction code currently being processed. The control circuitry then converts this code into microoperations, necessary to implement it. 6. TR (Temporary Register) stores the intermediate results or other temporary data. It acts as a scratch register for the processor. 7. OUTR (Output Register): It holds an 8 - bit character to the output device. 8. INPR (Input Register): It holds an 8 - bit character rec eived from the input device. 3. Seven flip - flops 1. I flip - flop: It gives information about the addressing mode, whether it is direct or indirect. 2. S flip - flop: It is the start - stop flip - flop 3. E flip - flop: It is used for the 'carry.' 4. R flip - flop: It is used for th e 'interrupt.' 5. IEN flip - flop: It is used for Interrupt enable on 6. FGI flip - flop: used for input flag 7. FGO flip - flop: used for output flag 4. Two decoders 1. 3x8 operation decoder: used to decode the output of IR (Instruction Register) 2. 4x16 timing decoder: used to decode the time signal generated by SC (Sequence Counter) 5. A 16 - bit common bus: The basic computer has eight registers, a memory unit, and a control unit, and there is a requirement of a path to transfer information from one register to another and between 16 memory and register. So to provide this path we use a common bus. Here is a diagram of the 16 - bit common bus for a better understanding 6. Control logic gates 7. Adder and logic circuit connected to the input of AC The input for the control logic gate comes from: 1. Input from I flip - flops 2. Input from the two decoders 3. Input from 0 - 11 bits of IR (Instruction Register) 4. Other inputs to the control logic gate include 1. AC (Accumulator) bits 0 - 15, to check if AC=0 and to detect the sign bit in AC(15) 2. DR (Data Register) bits 0 - 15, to check if DR=0 and check the values of seven flip - flops. The output of the control logic circuit is as follows: 1. Signals to control the read and write inputs of memory 2. Signals to control the inputs of the eight registers. 3. Signals to control the AC adder and logic circuit 4. Signals to control the S2, S1, and S0 to select a register for the bus 5. Signals to set, clear or complement the flip - flops 17 Booth's Multiplication Algorithm The booth algorithm is a multiplication algorithm that allows us t o multiply the two signed binary integers in 2's complement, respectively. It is also used to speed up the performance of the multiplication process. It is very efficient too. It works on the string bits 0's in the multiplier that requires no additional bi t only shift the right - most string bits and a string of 1's in a multiplier bit weight 2 k to weight 2 m that can be considered as 2 k+ 1 - 2 m Following is the pictorial representation of the Booth's Algorithm: In the above flowchart, initially, AC and Q n + 1 bits are set to 0, and the SC is a sequence counter that represents the total bits set n, which is equal to the number of bits in the multiplier. There are BR that represent the multiplicand bits, and QR represents the multiplier bits . After that, we enc ountered two bits of the multiplier as Q n and Q n + 1 , where Qn represents the last bit of QR, and Q n + 1 represents the incremented bit of Qn by 1. Suppose two bits of the multiplier is equal to 10; it means that we have to subtract the multiplier from the partial product in the accumulator AC and then perform the arithmetic shift operation (ashr). If the two of the multipliers equal to 01, it means we need to perform the addition of the multiplicand to the partial product in accumulator AC and then perform the arithmetic shift operation ( ashr ), including Q n + 1 . The arithmetic shift operation is used in Booth's algorithm to shift AC and QR bits to the right by one and remains the sign bit in AC unchanged. And the sequence counter is continuously decremented till the computational loop is repeated, equal to the number of bits (n). 18 Working on the Booth Algorithm 1. Set the Multiplicand and Multiplier binary bits as M and Q, respectively. 2. Initially, we set the AC and Q n + 1 registers value to 0. 3. SC represents the number of Multiplier bits (Q), and it is a sequence counter that is continuously decremented till equal to the number of bits (n) or reached to 0. 4. A Qn represents the last bit of the Q, and the Q n+1 shows the incremented bit of Qn by 1. 5. On each cycle o f the booth algorithm, Q n and Q n + 1 bits will be checked on the following parameters as follows: i. When two bits Q n and Q n + 1 are 00 or 11, we simply perform the arithmetic shift right operation (ashr) to the partial product AC. And the bits of Qn and Q n + 1 is incremented by 1 bit. 19 ii. If the bits of Q n and Q n + 1 is shows to 01, the multiplicand bits (M) will be added to the AC (Accumulator register). After that, we perform the right shift operation to the AC and QR bits by 1. iii. If the bits of Q n and Q n + 1 is shows to 10, the multiplicand bits (M) will be subtracted from the AC (Accumulator register). After that, we perform the right shift operation to the AC and QR bits by 1. 6. The operation continuously works till we reached n - 1 bit in the booth algorithm. 7. Re sults of the Multiplication binary bits will be stored in the AC and QR registers. 20 UNIT - II CONTROL UNIT In a system or computer, most of the tasks are controlled with the help of a processor or CPU (Central processing unit), which is the main component of a computer. The CPU usually has two main systems: control unit (CU) and arithmetic and logic unit (ALU). The control unit (CU) is used to synchronize the tasks with the help of sending timings and control signals. On the other hand, m athematical and logical operations can be handled with the help of ALU. Micro programmed control units and hardwired control units can be called two types of control units. We can execute an instruction with the help of these two control units. In the hard wired control unit , the execution of operations is much faster, but the implementation, modification, and decoding are difficult. In contrast, implementing, modifying, decoding micro - programmed control units is very easy. The micro - programmed control unit is also able to handle complex instructions. With the help of control signals generated by micro - programmed and hardwired control units, we are able to fetch and execute the instructions. Control Signals In order to generate the control signals, both the c ontrol signals were basically designed. The functionality of a processor's hardware is operated with the help of these control signals. The control signals are used to know about various types of things, which are described as follows: o Control signals are used to know what operation is going to be performed. o It is used to know about the sequence of operations that are performed by the processor. o It is used to know about the timing at which an operation must be executed and many other types of things. Hardwi red Control Unit With the help of generating control signals, the hardwired control unit is able to execute the instructions at a correct time and proper sequence. As compared to the micro - programmed, the hardwired CU is generally faster. In this CU, the c ontrol signals are generated with the help of PLA circuit and state counter. Here the Central processing unit requires all these control signals. With the help of hardware, the hardwired control signals are generated, and it basically uses the circuitry ap proach. The image of a hardwired control unit is described as follows, which contains various components in the form of circuitry. We will discuss them one by one so that we can properly understand the "generation of control signals".

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