i Preface Welcome to the Volume 3 Number 2 of the International Journal of Design, Analysis and Tools for Integrated Circuits and Systems (IJDATICS). This IJDATICS issue presents four high quality academic papers. This mix provides a well-rounded snapshot of current research in the field and provides a springboard for driving future work and discussion. The four papers presented in this volume are summarized as follows: • Circuit Modeling and Simulation: Avireni exhibits stable, linear and drift-free square waveform generator for very large scale integration (VLSI) implementation. • Electronic Circuits: Bhaskar presents a technique to implement linear CMOS transconductor as an alternative to conventional source-coupled differential pair (SCDP) circuits. • Analog/RF circuits: Jai, Jayanta, and Prakash propose a novel nonlinear model generation technique for Analog/RF circuits. • Circuits and Systems for Cryptography: Reza, Mohammad, and Keivan present application specific instruction set processors to support two popular crypto algorithms. We are beholden to all of the authors for their contributions to IJDATICS. We would also like to thank the IJDATICS editorial team. Editors: Ka Lok Man , Xi’an Jiaotong-Liverpool University, China, Myongji University, South Korea and Baltic Institute of Advanced Technology (BPTI), Lithuania Amir-Mohammad Rahmani , University of Turku, Finland Chi-Un Lei , University of Hong Kong, Hong Kong ii Table of Contents Vol. 3, No. 2, November 2012 Preface .......................................................................................... ....... i Table of Contents ................................................................................. .. ii 1. Current Conveyor Based Relaxation Oscillator with Tunable Grounded Resistor/Capacitor.................................................................. Avireni Srinivasulu 1 2. A Linear CMOS Transconductance Element ........................... .. Bhaskar Gopalan 8 3. Nonlinear Modeling and Optimization by Design of Experiments : A 2 GHz RF Oscillator Case Study................................................................................ ............................. Jai Narayan Tripathi, Jayanta Mukherjee, and Prakash R. Apte 15 4. Design and Implementation of an ASIP - Based Crypto Processor for IDEA and SAFER K-64 .......................... Reza Faghih Mirzaee, Mohammad Eshghi, and Keivan Navi 21 INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR INTEGRATED CIRCUITS AND SYSTEMS, VOL. 3, NO. 2, NOVEMBER 2012 1 Abstract — At the outset the foregoing document is represented by square-wave generator using three second generation current conveyers, five resistors and one capacitor with independent control of frequency is presented. The unique features associated with such waveform generator are the easy tunability of frequency over a range of 15 Hz to 150 kHz, extremely low sensitivities as well as suitable for very large scale integration (VLSI) implementation. The working capacity of the proposed circuit is examined with the aid of SPICE models of IC AD 844 AN. Later, the circuit was built with commercially available current feedback operational amplifiers (AD 844 AN), passive components used externally and tested for waveform generation and tunability. Results achieved prove better agreement with the theoretical values. And the non-idealities also are examined. Index Terms — Second generation current conveyer, CCII+, AD 844 AN applications, Schmitt trigger, square wave generator, relaxation oscillator. I. INTRODUCTION ELAXATION oscillators are widely introduced in many electronic systems such as bio-medical instrumentation, power electronics, communication and signal processing applications including pulse width modulation (PWM). Even today, operational amplifiers make-up the majority of the analogue active function circuits and filters found in electronic application in both discrete and monolithic form. Unfortunately, however, for stability reasons the frequencies at which these circuits operate are limited by the operational amplifier compensation network. The second generation current conveyor (CCII+) is found to be of great use as an analogue building block and also widely introduced in waveform generators, oscillators, and design of amplifiers and filters [1-8]. The current conveyor strictly depends upon the ability of the circuit which acts as a voltage buffer between its inputs and also on its ability to transmit current between two ports at highly different impedance levels. It is of great interest to note that these two functional characteristics of the current conveyor are independent of one another and the later can be combined to form the current Manuscript received October 25, 2011 accepted January 26, 2012. Avireni Srinivasulu is with the Department of Electronics and Communication Engineering, Vignan University, Vadlamudi, A.P, India. (Mobile: +91 9502223336, Tel Phone: +91 863 2344700 Extn: 223; fax: +91 863 2534468; e-mail: avireni@ieee.org (or) avireni_s@yahoo.com). conveyor [9-10]. The response H(s) = i z (s)/i x (s) of CCII at varied frequencies does not exhibit roll-off properties at very low frequency levels like the operational amplifiers could do. It is also that, if the feedback loop is built up in a CCII network, the band width of the network has not shown any sign of collapse from the limitation due to a constant gain bandwidth product [11-15]. Firstly, the CCII+ based nonlinear design was attributed to Cataldo et al [16]. Applying the Schmitt trigger topology of [16], CCII+ based relaxation oscillator, CFOA-based triangular/square wave generator, Current-mode triangular wave generator using CCIIs and Current conveyor-based relaxation oscillators as a multifaceted electronic interface for capacitive and resistive sensors were reported earlier [17-20]. However all these topologies which were quite similar to each other, had only limited success due to bandwidth and linearity. In this paper, a new topology using the three CCII+’s, is concerned it exhibits stable, linear and drift-free square waveform over the frequency range from 15 Hz to 150 kHz. In order to control a system, it is necessary to have a stable, distortion-free signal over the complete frequency range. It has a grounded capacitor and a grounded resistor each of which can be used for easy tuning. The topology is, therefore, also suitable for digital control by switched programmable resistor/capacitor array and can be integrated by the monolithic process with the tuning component placed outside the wafer. The remaining sections of the paper are organized as follows. The CCII+ modalities and analysis of the proposed design procedure are reported in section II. Effect of non-idealities and measured results with comparison are reckoned in sections III and IV. Finally, the component sensitivity of proposed configuration and end results are surfaced in section V and VI, respectively. II. CCII+ F UNDAMENTALS AND A NALYSIS OF T HE P ROPOSED D ESIGN A. CCII+ Fundamentals Figure1 depicts the symbol of a CCII whose ideal terminal characteristics can be reproduced by a hybrid matrix [10], Current Conveyor Based Relaxation Oscillator with Tunable Grounded Resistor/Capacitor Avireni Srinivasulu R INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR INTEGRATED CIRCUITS AND SYSTEMS, VOL. 3, NO. 2, NOVEMBER 2012 2 with the output parameters of the three ports in terms of their corresponding inputs given by: 0 1 0 0 0 0 1 0 0 X X Y Y Z Z V i i V i V ª º ª º ª º « » « » « » « » « » « » « » « » « » r ¬ ¼ ¬ ¼ ¬ ¼ (1) The output current i Z depends only on the input current i X drawn from terminal X (Fig.1). The current may be directly injected at terminal X or it may be generated by the copy of the input voltage V Y , from terminal Y that acts across the impedance connected at X . The ± sign in (1) denotes whether the conveyor is formulated either non-inverting or inverting circuit, however termed as CCII+ or CCII–. By convention i X and i Z to be taken for positive current that flows simultaneously towards or away from the conveyor (Fig.1). V X = V Y , i Y = 0 and i Z = i X (2) B. Analysis of the Proposed Design: 1 st Method The circuit diagram of the proposed square-wave generator is presented in Fig. 2. The Schmitt trigger is composed of two second generation current conveyors (one is represented by CCII+(1), resistors R F and R 1 and the other CCII+(2), R 2 and R 3 ] both connected in a positive-feedback position. The Schmitt trigger transfer characteristics are shown in Fig. 3. Resistor R , the timing capacitor C and CCII+(3) form an integrator. In order to investigate the operation of generator, initially it is assumed that in Fig. 2 and referring to the notation in Fig. 4, the output voltage at node Z 2 of CCII+(2) is at the Z X Y CCII (±) V Y V X i Z V Z i Y i X Fig. 1. Symbol for CCII +V S +V T-ramp -V T-ramp -V S Fig. 4. Output waveforms of the proposed generator t T V -i C /C i C /C Fig. 3. Transfer characteristic of the Schmitt trigger V T V S -V satL satH F V R R R R ̧ ̧ ¹ · ̈ ̈ © § 3 1 2 1 V satH satL F V R R R R ̧ ̧ ¹ · ̈ ̈ © § 3 1 2 1 0 Fig. 2. Circuit diagram of the proposed square/triangular-wave generator R F Z 1 CCII+(1) X 1 Y 1 Z 2 CCII+(2) Y 2 X 2 V S R 3 R 2 R 1 CCII+(3) Y 3 X 3 R C Z 3 ‘a’ ‘b’ ‘c’ V T INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR INTEGRATED CIRCUITS AND SYSTEMS, VOL. 3, NO. 2, NOVEMBER 2012 3 positive peak of the square wave V S . As such, the voltage at X 1 is also at V S and the current i X1 ( = ( V S -V T ) /R F ) is going out. From the node equations of ideal CCII+ we also get that the node voltage at X 3 is at V S and i X3 =V S /R is going out. It can be concluded that the node current going out of the i Z3 is V S /R. Therefore, at this point of time the capacitor C is getting charged by the combining current i Z3 +i X1 . We can thus write the charging equation for C as 1 X S T i R V dt dV C (3) where V T is the voltage charging the capacitor linearly to give rise to a triangular waveform. Again i X1 can be written as 1 S T X F V V i R (4) and also 1 3 1 3 2 S T F R R V V R R R R § · ̈ ̧ © ¹ (5) Substituting (4) in (3) and combining (5) to eliminate V S , we can write 1 3 2 1 3 2 1 3 2 T T T F F R R dV R C V V dt R R R R R R R R R (6) Now this process continues and the capacitor gets charged to V T until the node voltage Z 3 is high enough to force a current in the opposite direction in the branch i X1 . When that happens, the current direction of i X1 , i Z1 , i X2 , i Z2 , i X3 , and i Z3 changes and the node voltage at Z 2 drops from V S to – V S and the reverse transition with the capacitor voltage discharging through i X1 and i Z1 starts. And also through i X2 and i Z2 starts. The governing equation as can be seen easily however remains the same for the discharging path as well and thus (6) holds. Solving (6), we can get the expression for time period of the waveform generator which can be written as T=1/f where f is expressed as 1 3 2 1 3 2 1 3 2 2 2 F F R R R f R R R R R C R R R R C S S (7) Obviously, the condition for the waveform generation is a positive feedback with a loop gain greater than unity which in this case leads to the condition 3 1 2 R R R R F (8) Equation (8) can also be emphasised that the similarity in performance ascribed to the circuit given in Figure 2. Further, by selecting R 2 << R 1 R 3 , we can simplify (6) to arrive at a more compact equation which is expressed for the time period T as 2 1 3 2 1 F R R T ʌ RC R R § · # ̈ ̧ © ¹ (9) or, the oscillation frequency (f) can be written as 1 3 1 3 2 1 2 F R R f ʌ R C R R R R § · ̈ ̧ © ¹ (10) C. Analysis of the Proposed Design: 2 nd Method Taking into consideration the ideal terminal characteristics involved in CCII+ referred above and the relevant notations appearing in Fig. 2, the mathematical representation is proposed as follows 3 1 1 Z X X F V V i R (i) 1 1 1 Z Z V i R (ii) 2 2 2 X X V i R (iii) 2 2 3 Z Z V i R (iv) 3 3 X X V i R (v) 3 Z C sV C i (vi) From the above relations and for ideal behaviour of the CCII+ given by (2) it is easy to derive the characteristic equation in the form 1 3 2 1 3 0 F R R R R RCs R R (vii) with , s j Z where Ȧ is the angular frequency in rad/s, from the above equation (vii), the oscillation frequency (f) can be written as 1 3 1 3 2 1 2 F R R f ʌ RC R R R R § · ̈ ̧ © ¹ (viii) The time period (T) then thus can be expressed as: 2 1 3 2 1 F R R T ʌ RC R R § · ̈ ̧ © ¹ (ix) However the operation of the waveform generator is relied upon the regenerative feedback which can be secured as long as: 2 1 3 F R R R R (x) Equation (x) can also be stated as the condition of the operation of the circuit denoted in Fig. 2. While analyzing the circuit, the parasitic and the second order effects are ignored. The justification for this is that the waveform generator is designed to operate at a frequency which is less than or equal to 150 kHz. Obviously, the parasitic does not affect the analysis in the frequency range of interest for this paper. However, the ideal behaviour of the CCII+ as stated in (2) and used in the analysis does not hold in practical or commercially available CCII+ like AD 844 AN [21, 22]. As such the effect of the CCII+ non-ideality on the INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR INTEGRATED CIRCUITS AND SYSTEMS, VOL. 3, NO. 2, NOVEMBER 2012 4 analysis is discussed in the next section. III. E FFECT OF C URRENT C ONVEYOR N ON -I DEALITIES M ATH In that analysis so far, ideal characteristics for the current conveyors are being considered. However, in this section of investigation the analysis could change if the parameters of a practical model of current conveyor including some non- idealities are taken for granted. Although for simulation the model presented in Fig. 2 holds good for interest of this paper, the parasitic cannot be altogether ignored while the proposed design is tested using the commercially available current conveyor-cum-buffer AD 844 AN [21]. The measured results in this regard are included in the section 4. For this purpose, therefore, it is determined to utilise the model of AD 844 AN, which is provided in Fig. 5. Typical values as given in [21] include R X = 50 ȍ , R Y = 10 M ȍ , R Z = 3 M ȍ , C X = 2 pF , C Y = 2 pF , and C Z = 4.4 pF. Fig. 5. Practical model of AD 844 (CCII+) Considering now a real CCII+, the terminal voltages at X Y V V z , port currents Z X i i z and there is a very low dependence of i Y from i X For the practical device the modified [16], [22] relation is given by: 0 0 0 0 0 0 X X Y Y Z Z V i i V i V D J E ª º ª º ª º « » « » « » « » « » « » « » « » « » ¬ ¼ ¬ ¼ ¬ ¼ (11) Typical values of D = E = 0.98 and J = 2 u 10 -3 can be verified from [16]. By repeating the complete analysis, as shown in section 2, with the parameters D , E and J , modified relation for the oscillation frequency ( f ) can be written as 2 2 2 1 3 2 3 2 2 2 1 3 2 3 1 2 1 2 F F R R R R f ʌ R C R R R R R R R R D E E J DEJ D E J DJ § · ̈ ̧ ̈ ̧ © ¹ (12) The time period ( T ) then can be expressed as 2 2 2 1 3 2 3 1 2 2 2 2 1 3 2 3 2 F F R R R R R R R R T ʌ RC R R R R D E J DJ D E E J DEJ § · ̈ ̧ ̈ ̧ © ¹ (13) It can be easily verified that, the equation (12) and (13) reduces to equation (10) or (viii) and (9) or (ix) as expected, for ideal CCII+ when D = E = 1 and J = 0 IV M EASURED R ESULTS AND C OMPARISON The complete circuit after using the model of CCII+ form is given in Figure 2 and the related device level circuit is included in Figure 6 [10], [22], [23]. Fig. 6. Device level presentation of the proposed relaxation oscillator X Z Y CCII+ (Ideal) C Y RY W C Z R Z RX buffer 1 i Z C X X Y V Z V X V Y i X i Y Z INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR INTEGRATED CIRCUITS AND SYSTEMS, VOL. 3, NO. 2, NOVEMBER 2012 5 Fig. 7. Typical square/triangular waveform The tunability for the grounded capacitor C was next tested for the configuration. For this the passive components were chosen as R 1 =R 3 = 99 k ȍ , R 2 = 1.95 k ȍ , R F = 4.7 k ȍ , R= 1.95 Nȍ , and the capacitor C was varied from 500 pF to 5 ȝ F. The tunability for the range from 15 Hz (near dc) to 150 kHz can be verified from the plot given in Figure 8. Fig. 8 Variation of time period against capacitor C Fig. 9 Variation of time period against resistor R Similarly, for resistor R , the selected parameters were R 1 = R 3 = 99 k ȍ , R 2 = 1.95 k ȍ , R F = 4.7 k ȍ , and C = 100 nF. Resistor R was varied from 500 ȍ to 5 k ȍ . The result for the variation of R from 500 ȍ to 5 k ȍ is plotted in Figure 9. It was observed from a comparative study of simulated results that the proposed circuit outscored the competitive CCII+ based relaxation oscillator [17], CFOA based designs [18], current mode triangular wave generator [19], and TABLE I C OMPARISON W ITH C ANDIDATE D ESIGNS Candidate Designs Band-width Simulated Total Harmonic Distortion (THD) Percentage variation of amplitude over temperature (-200 0 C to +200 0 C) Proposed design 150 kHz 6.5 0.0002% CCII+ based relaxation oscillator [17] 1 MHz 7.0 0.206% CFOA based design [18] 100 kHz 6.6 0.043% Current mode triangular wave generator [19] 450 kHz 7.2 0.196% Current conveyor based relaxation oscillator [20] 500 kHz 7.0 0.206% INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR INTEGRATED CIRCUITS AND SYSTEMS, VOL. 3, NO. 2, NOVEMBER 2012 6 current conveyor-based relaxation oscillator [20] based designs in linearity and total harmonic distortion performed better as compared with others. Thus from the comparison presented in Table I, the proposed configuration is concluded to have the best overall performance taking all the aforesaid into consideration. Commercially available CCII+ as monolithic IC AD 844 AN (Analog Devices) [21] was used to fabricate the design of Figure 2 with a power supply rail typically ± 6 V. The tunability of the configuration was tested for both C and R For this the passive components were chosen as R 1 =R 3 = 99 Nȍ , R 2 = 1.95 k ȍ , R F = 4.7 k ȍ , R= 1.95 k ȍ , and the capacitor C was varied from 500 pF to 5 ȝ F. Similarly, for resistor R , the selected parameters were R 1 = R 3 = 99 k ȍ , R 2 = 1.95 k ȍ , R F = 4.7 k ȍ , and C = 100 nF. Resistor R got varied from 500 ȍ to 5 k ȍ . As the graphs obtained from the measured results more or less replicate the simulated ones, which are already presented, so they are not included here to avoid repetition. A typical waveform from the oscilloscope screen is presented in Fig. 10 which has been obtained for a supply voltage of r 6 V and for components values R 1 = R 3 = 100 Nȍ , R 2 = 2 k ȍ , R F = 4.7 k ȍ , R = 0.6 k ȍ , and C = 5 μF. The time-period of 19.95 mS measured as is observed from Fig. 10 closely coincide with the predicted time-period of 18.83 mS obtained from (9) by using the ideal CCII+’s. Fig.10 Experimentally observed square/triangular waveform from the built circuit as per Figure 2. V. S ENSITIVITY Classical sensitivity ( y x S ) for parameter y with respect to parameter x has been defined [24] as, y x S = y x y y x y x x G G G G (14) Applying this for (9) it is easy to find, , T C S , T R S , F T R S 1 , T R S 2 T R S and 3 T R S which are given by, T C S = T R S =1 (15) 1 T R S = 3 T R S = – F T R S = – 2 T R S = 2 1 3 2 F F R R R R R R (16) Obviously, in the summation to find the net sensitivity ( 1 2 3 , , , , , F T x x C R R R R R S S ¦ ), it can be easily verified that the sensitivities for R F , R 1 , R 2 , and R 3 completely cancel out leaving for C and R from (15) is 1. Further, for analog ASIC, with appropriate design, the capacitors and resistors can be made to track in opposite polarity [25] there by reducing the sensitivity factors further. In fact both capacitor and resistor actually track quite closely to effectively nullify the component sensitivity ( S ) [17, 19, 25]. As such the proposed configuration can be concluded to be stable against component sensitivity as per the classical definition. VI. C ONCLUSION A new topology square-wave generator is presented. In this case the circuit is made to utilise three CCII+’s, six passive elements with grounded tuning resistor and capacitor. The frequency of waveform generator can be adjusted by tuning a grounded resistor and/or a grounded capacitor and is independent of the power supply voltages. The analysis and the measured results involved exhibit close matching with those for the theoretical analysis. The topology has its genesis in current mode Schmitt Trigger. The reported design has the superiority in terms of the stability of the amplitude, improved linearity, and temperature sensitivity. Tunability of grounded components is an attractive feature of the design as it provides an easy option for digital control by programmable switched capacitor/resistor array. The component’s sensitivity is very small, making it thereby a candidate can easily design for integration. This circuit may gain greater importance as it is bestowed with wider applications in many electronics and communication systems as well as instrumentation and neuro-fuzzy systems. R EFERENCES [1] C. Falconi, G. Ferri, V. Stornelli, A. De Marcellis, D. Mazzieri, and A. D'Amico, “Current-mode high-accuracy high-precision CMOS amplifiers,” IEEE Transactions on Circuits and Systems II: Express Briefs , vol. 55, pp. 394-398, May. 2008 [2] A. M. Soliman, “Current mode filters using two output inverting CCII,” International Journal of Circuit Theory and Applications , vol. 36, no. 7, pp. 875-881, 2007. [3] Avireni Srinivasulu, “A novel current conveyor based Schmitt trigger and its application as a relaxation oscillator”, International Journal of Circuit Theory and Applications , vol. 39, no. 6, pp. 679-686, Jun. 2011. [4] R. A. Saad, A. M. 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Palumbo, and S. Pennisi, “1.5-V CMOS CCII+ with high current-driving capability,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Proc. , vol. 50, pp. 187-190, Apr. 2003. [9] A. S. Sedra and K. C. Smith, “A second generation current conveyor and its applications,” IEEE Transactions on Circuit Theory , CT-17, pp. 132- 134, Feb. 1970. [10] A. S. Sedra, G. W. Roberts, and F. Gohh, “The current conveyor: history, progress and new results,” IEE Proc., vol. 137, Part G.No. 2, pp. 78–87, Apr. 1990. [11] Jiunn-Yih Lee and Hen-Wai Tsao, “True RC Integrators based on current conveyors with tunable time constants using active control and modified loop technique,” IEEE Transactions on Instrumentation and Measurement , vol. 41, no. 5, pp. 709-714, Oct. 1992. [12] E. Seevinck, “Companding current-mode for continuous-time monolithic integrator: a new circuit principle filters,” Electronic Letters., vol. 26, no. 24, pp. 2046-2047, 22nd Nov. 1990. [13] Shahram Minaei, Guven Topcu, and Oguzhan Ccekoglu, “Active only integrator and differentiator with tunable time constants,” International Journal of Electronics , vol. 90, no. 9, pp. 581–588, 2003. [14] Sang-Soo Lee, Rajesh H.Zele, David J. Allstot, and Guojin Liang, “A continuous-time current-mode integrator,” IEEE Transactions on Circuits and Systems, vol. 38, no. 10, pp. 1236-1238, Oct. 1991. [15] D. Patranabis and D. K. Ghosh, “Integrators and differentiators with current conveyors,” IEEE Transactions on Circuits and Systems, vol. CAS-31, no. 6, pp. 567-569, Jun. 1984. [16] G. DI. Cataldo, G. Palumbo, and S. Pennisi, “A Schmitt trigger by means of a CCII+,” International Journal of Circuit Theory and Applications , vol. 23, pp. 161-165, 1995. [17] Mehmet Oguzhan Cicekoglu, and Hakan Kuntman, “On the design of CCII+ based relaxation oscillator employing single grounded passive element for linear period control,” Microelectronics Journal , vol. 29, pp. 983-989, 1998. [18] Muhammad Taher Abuelma’atti and Sa’ad Muhammad Al-shahrani, “New CFOA-based triangular/square wave generator,” International Journal of Electronics , vol. 84, pp. 583-588, 1998. [19] B. Almashary and H. Alhokail, “Current-mode triangular wave generator using CCIIs,” Microelectronics Journal , vol. 31 , pp. 239-243, 2000. [20] Muhammad Taher Abuelma’atti, and Munir Ahmad Al-Absi, “A current conveyor-based relaxation oscillator as a versatile electronic interface for capacitive and resistive sensors,” International Journal of Electronics , vol. 92, pp. 473-477, Aug. 2005. [21] AD844 current feedback op-amp data sheet , Analog Devices Inc., Norwood, MA, 1990. [22] J. A. Svoboda, L. Mc Gory, and S. Webb, “Applications of a commercially available current conveyor,” International Journal of Electronics , vol. 70, no. 1, pp. 159–164, 1991. [23] D. Pal, Avireni Srinivasulu, B. B. Pal, A. Demosthenous, and B. N. Das, “Current conveyor based square/triangular – waveform generators with improved linearity,” IEEE Transactions on Instrumentation and Measurement, vol. 58, no. 7, pp. 2174-2180, Jul. 2009. [24] A.S. Sedra and K. C. Smith, Microelectronic Circuits , Oxford University Press, 4th ed., pp. 1002-1005, 1998. [25] T. Laopoulos, S. Siskos, M. Bafleur, P. Givelin, and E. Tournier, “Design and applications of an easily integrable CMOS operational floating amplifier for the megahertz range,” Analog Integrated Circuits and Signal Processing , 7, pp. 103-111, 1995. Avireni Srinivasulu (M’10) was born in Thurimella, (A.P), India, in 1963. He received the B.Tech degree in electronics and communication engineering from Sri Venkateswara University, Tirupati in 1986, M.E, degree in power electronics engineering from Gulbarga University, Gulbarga in 1991, M.S, degree in software systems from Birla Institute of Technology and Science (BITS), Pilani in 1998 and Ph.D, degree in electronics & communication engineering (VLSI Design) from Birla Institute of Technology, Mesra, India in 2010. He worked as a Lecturer, Assistant Professor, Reader, Associate Professor, and working as a Professor in the department of electronics and communication engineering, T.G.L.G. Polytechnic, Adoni; Guru Nanak Dev Polytechnic, Bidar; K.S.R.M. College of Engineering, Kadapa; Defence University Engineering College, Ethiopia; Kigali Institute of Science, Technology & Management, Rwanda; Birla Institute of Technology, Mesra, Ranchi and Vignan University, Vadlamudi, Guntur, India. He has 24 years of teaching and 14 years of research experience in the department of electronics & communication Engineering. Dr. A.Srinivasulu is a member of IEEE, life member of I.S.T.E and a member of the Institution of Engineers (India). He has published over 25 articles in international journals and international conference proceedings; his main research areas are microelectronics, VLSI design and analog ASIC. INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR INTEGRATED CIRCUITS AND SYSTEMS, VOL. 3, NO. 2, NOVEMBER 2012 8 A Linear CMOS Transconductance Element Bhaskar Gopalan Abstract – A novel circuit technique for realizing a linear CMOS transconductance element is proposed. The present circuit is an alternative to that of conventional source-coupled differential pair (SCDP) and the circuit discussed has superior linearity than the SCDP for a wide range of input differential voltage. The SPICE results using BSIM3v3.1 model are used to verify theoretical predictions. The results show close agreement between predicted behavior and simulated performance. The simulated results on Total Harmonic Distortion (THD) show that the proposed circuit is better than the SCDP for a wide range of input differential voltage. An example circuit, a second order continuous time gm-C band- pass filter is constructed using proposed transconductors and SCDP circuits and the results show that the proposed transconductor circuit is better suited to broadband than SCDP. A method to compensate for the variation of output current with temperature for a particular temperature is also discussed. Index Terms – Transconductor, SCDP circuit, Linearity, Total harmonic distortion (THD) , Power dissipation, gm-C filter, SPICE Models. I. INTRODUCTION inear transconductance elements [1]-[10] are useful in building blocks in analog signal-processing systems. The objective of this paper is to present a simple novel CMOS circuit realization of linear transconductance block, doesn’t require any special cell, for example a cross-coupled quad cell [1] and requires only two additional simple PMOS differential pairs than SCDP. The linearity and input voltage range of the proposed design is superior to that of the Source- coupled differential pair. The computer simulations results are presented. All MOSFET’s are assumed to be enhancement-mode types biased in saturation and the transistor behavior is approximated by the relation, ( ) 2 2 n D GS th K I V V = − (1) Where th V is the total threshold voltage inclusive of body-effect. ( ) ' / n n K K W L = is the transconductance parameter, W and L are width and length of the channel. The effect of channel length modulation is not included in (1) but is taken into account separately. This paper is organized as follows. The next section describes the proposed linear CMOS transconductor. Section III presents the simulation results of proposed and SCDP circuits with BSIM3v3.1 models. Section IV presents the application of the Fig.1. The proposed Linear CMOS Transconductance Element. Manuscript received November, 27,2011. Bhaskar Gopalan is an independent consultant in Chennai, India. Phone: 91- 44-22240746; Email: bhaskar_gopalan@hotmail.com proposed and SCDP circuits to a gm-C filter design. Lastly Section V addresses the circuits to compensate for the variation of output current with temperature for the proposed transconductor. L INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR INTEGRATED CIRCUITS AND SYSTEMS, VOL. 3, NO. 2, NOVEMBER 2012 9 II. THE PROPOSED CIRCUIT The proposed linear transconductor circuit is shown in Fig.1. In Fig.1, transistors M1 and M2 form the NMOS differential pair biased by Iss , transistors M6 and M7 form the PMOS differential pair biased by nIss and M11, M12 form the PMOS differential pair biased by mIss . Make, ' ' ' 1 2 6 ' ' ' 7 11 12 n p n n p p p p K K W W W K K K L L L W W W K K K L L L = = = = = = The differential current of NMOS differential pair (M1,M2) is given by, ( ) 2 ' 1 1 1 4 n n v K I I K Iss v Iss − = − (2) Where 1 2 v V V = − provided 2 n Iss v K <= The differential current of PMOS differential pair (M6,M7) is given by, ( ) 2 ' 2 2 1 4 n n v K I I K Iss v n nIss − = − − (3) Provided 2 n nIss v K <= The differential current of PMOS differential pair (M11,M12) is given by, ( ) 2 ' 3 3 1 4 n n v K I I K Iss v m mIss − = − − (4) Provided 2 n mIss v K <= Now, the sum of equations (2), (3) and (4) is given by, ( ) ( ) ( ) ( ) ' ' ' 1 1 2 2 3 3 2 2 2 1 1 1 4 4 4 n n n n I I I I I I K Iss v v K v K v K n m Iss nIss mIss − + − + − = − − − − − (5) Expanding the square root terms by Binomial Series and after rearranging, we get ' ' ' 1 1 2 2 3 3 ( ) ( ) ( ) I I I I I I − + − + − = ( ) ( ) 1 n K Iss v n m − + − ( ) 2 1 1 1 1 8 1 n v K higher order n m Iss terms n m − − + + + − (6) Now choosing 4 n = and 4 m = , the 2 v term is eliminated and therefore the summed total differential current is given approximately by (neglecting the higher order terms), ( ) ( ) 1 T n I K Iss n m v = − + − (7) The equation (7) shows that the differential current T I is linear with v . Note that the higher order terms are diminished by the factor, ( 1) n m + − III. SIMULATION RESULTS The above circuit is simulated in LTSPICE with 0.13um, 1.2v IBM Technology CMOS process using BSIM3v3.1 Models and found to be much linear than the source-coupled differential pair for a wide range of input voltage but the proposed circuit has more transistors and occupies more area than SCDP. The following SPICE-LEVEL1 model parameters are obtained from matching the results with that of BSIM3v3.1 models for the corresponding device voltages. ' 2 ' 2 1 1 1 1.2 , 2 1.6 , 0.06 / , 0.032 / , 0.37 , 0.39 , 0.61 , 0.41 , 0.7 . n p n p cm Vdd v Vdd v K mA v K mA v vtn v vtp v v v V v λ λ − − = = = = = = − = = = Where cm V is the input common-mode voltage, n p and λ λ are the channel-length modulation parameters for the NMOS and PMOS and vtn and vtp are the threshold voltage parameters for NMOS and PMOS. ' ' , , n p n p K K and λ λ are found out at the appropriate device voltages. The ratio of ' n K to ' p K is 1.875 0.50 , 1.05 . x y z V v V V v = = = , 1 2 6 7 11 12 1 1 1 1.875 1.875 1 1 1.0 1.875 1.875 0.15 W W W W L L L L W W W u where L L L u = = = = = = Note to accommodate the increased currents in PMOS differential pairs, one more additional voltage source 2 Vdd is chosen to maintain the same input common-mode voltage range between NMOS and PMOS differential pairs. INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR INTEGRATED CIRCUITS AND SYSTEMS, VOL. 3, NO. 2, NOVEMBER 2012 10 The tail/biasing currents for the proposed circuit are found to be, 15.74 62.625 Iss uA and nIss mIss uA = = = The theoretical value of T I is found to be 238 / uA v and if we include channel length modulation, this is found to be 380 / uA v These lambda effects are included in T I by fitting a simple LEVEL1 MOS model for the devices. For the same output current, the biasing current required for the SCDP circuit is 44.6 uA For the NMOS-SCDP, ' 2 1 0.040 / 0.61 n n K mA v and v λ − = = are obtained at the appropriate voltages. The (W/L) size ratio required for the NMOS SCDP differential pair is given by, 4.7 0.15 W u L u = for the SCDP. The simulated results of the output current with v are shown in Fig.2 for both proposed circuit and SCDP. These results are obtained for Vcm=0.7v, Vout=0.625v , Iss(Proposed Circuit)= 15.60uA and Iss=44.6uA (SCDP). The graph is almost linear for the proposed circuit due to eqn. (7). The input common-mode voltage can vary from 0.4v to 0.9v without losing linearity much for the proposed circuit but with a change of transfer characteristics slope. The normalized linearity errors in % (deviation from I T ) with v for both present circuit and SCDP are shown in Fig.4 for Fig.2. The output currents for various temperatures are shown in Fig.3 for the proposed circuit, obtained for the same conditions as that of Fig.2. Note that as the temperature is increased, the biasing current and the virtual node of the PMOS differential pair increase. Also the two Vsd of M6 and M7 or M11 and M12 (Fig.1) vary less widely than with lower temperatures. Therefore the output current drops. This shows why lambda effects are important and needed to be included in the output current, I T The transient simulations were performed with a sinusoidal input frequency of Fin=100MHz and an output capacitance C L =50pf. The total harmonic distortion (THD) of output current in % Vs input voltage plots (Fig.5) are obtained for Iss (Proposed) =15.60uA, Iss (SCDP)=44.60uA and Vcm=0.7v. These plots show there is large THD for the case of large input differential voltages for the SCDP circuit. The THD values are lower for the proposed circuit because of equation (6). Fig.2 Transfer Characteristics (SPICE Results). The output current Vs v (=V 2 -V 1 ). Simulated at input Vcm=0.7v, Vout=0.625v, Iss=15.60uA (Proposed) and Iss=44.60uA (SCDP). Fig.3 Transfer Characteristics (SPICE Results) with Temperatures for the Proposed Circuit. Simulated at input Vcm=0.7v, Vout=0.625v and Iss=15.60uA (Proposed). INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR INTEGRATED CIRCUITS AND SYSTEMS, VOL. 3, NO. 2, NOVEMBER 2012 11 Fig.4. Departure from linearity for Fig.2. – Error plot. Fig.5 THD Vs Input voltage, v for the proposed circuit and SCDP. Simulated at Vcm=0.7v, C L =50pf, Fin=100MHz, Iss (proposed)=15.60uA and Iss (SCDP)=44.60uA. Fig.6. THD Vs Bias Current for the proposed circuit. Simulated for Vcm=0.7v, C L =50pf and Fin=100MHz. Fig.7. THD Vs Bias Current for SCDP circuit. Simulated for Vcm=0.7v, Fin=100MHz and C L =50pf. Fig.8. THD Vs DC power dissipation for the proposed and SCDP circuits. Simulated for Vcm=0.7v, C L =50pf and Fin=100MHz. Also THD Vs Bias current (Iss) plots are obtained for the different input voltages for the case of proposed circuit and INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR INTEGRATED CIRCUITS AND SYSTEMS, VOL. 3, NO. 2, NOVEMBER 2012 12 SCDP circuit. These plots for the proposed circuit are shown in Fig.6 and for SCDP are shown in Fig.7. These plots show that the THD values tend to reach equal between the proposed circuit and SCDP circuit with larger bias currents. The THD Vs Dc power dissipation ( d P ) plots are obtained for the proposed and SCDP circuits for various input voltages. These plots are shown in Fig.8. Again these plots show that the THD values are more for the case of SCDP for higher input voltages. The d P values are obtained for proposed and SCDP circuits as follows. 1* , 1* 2*(2* * ), Pd Vdd Iss for SCDP circuit Pd Vdd Iss Vdd n Iss for proposed circuit = = + The present transconductor can be made differential output by using two similar transconductors and applying v=V 2 - V 1 as shown in Fig.9. The next section describes the use of proposed transconductors and SCDP circuits in a second-order continuous time gm-C filter. Fig.9. A fully differential proposed transconductor. IV. A SECOND-ORDER gm-C FILTER A second-order gm-C band-pass continuous time filter is constructed using proposed transconductors discussed above with single-ended output and such a filter is shown in Fig.10. Fig.10. A second-order gm-C band-pass filter developed using proposed transconductors. The transfer function of this filter is given by 0 2 2 0 0 ( ) ( ) ( ) G s Q Vo s H s Vi s s s Q ω ω ω = = + + (8) The factor G =1 is the gain at the center frequency. Choosing, 0 4 3 2 2 gm gm Q C C ω = = and 0 1 2 1 2 gm gm C C ω = = where 0 2 *100.0 06 e ω π = , 5 Q = and 1 2 0.4 C C pf = = we obtain, 1 2 251.33 / gm gm uA v = = and 3 4 50.27 / gm gm uA v = = The bulk node of all the NMOS transistors is tied to the ground and that of all PMOS transistors is tied to Vdd. The bias voltages x V and y V are adjusted to provide the above values. For better results, the common-mode voltage Vcm is applied to the transconductors as shown in Fig.10. The Vcm is taken to be 0.625v. The frequency response of the filter constructed using proposed transconductors is shown in Fig.11. Also the same response for SCDP filter is shown in Fig.11. The performance parameters of the filter are listed in Table.I (both frequency and time domain parameters). The broadband frequency response of the filter with proposed transconductors