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On the linearity and parabolicity of the PIN dark IV: the effect of series resistance Aditya N. Roy Choudhury Shaibal K. Sarkar Department of Energy Science and Engineering Department of Energy Science and Engineering Indian Institute of Technology Bombay Indian Institute of Technology Bombay Mumbai, India Mumbai, India [email protected] [email protected] Abstract — The article provides simple analytical and holes [2-4]. This phenomenon causes a conductivity expressions for calculating the exact current-voltage (IV) modulation in the device. Therefore the resistivity of the I- characteristic of a PIN diode. Focus is on the differences layer changes appreciably whereas that of the P and the N between the PIN and the PN IVs. The I-layer width is assumed to be much greater than the material’s intrinsic Debye length. layers do not. In other words the I-layer’s series resistance Truthfulness of all derived equations is verified by comparing becomes bias dependent. This makes the high bias PIN IV with numerical simulations. As expected, the IV gets limited by parabolic. The high bias PN IV, on the other hand, is always the device’s series resistance (RS) at high forward bias. linear. However, whether the PIN IV is linear, or parabolic (or in As solar cells rise to occupy a significant share of the between) depends on which of the P, I, and/or N layer(s) present semiconductor technology and financial market, a dominate(s) the RS. A transition from linear to parabolic behavior is observed as the width of the intrinsic layer is complete, accurate, and easy-to-understand theory of the increased. Equations for the knee voltages and series PIN IV becomes an immediate necessity. To serve this end, resistances are also analytically derived, and are corroborated this article questions: ‘how is the PIN diode’s IV different with numerical simulations. than the PN diode’s IV?’, and ‘what are the equations for the knee voltages and series resistances of the PIN diode?’. Keywords — PIN diode, IV characteristics, series resistance, It provides simple expressions, derived from fundamental dark IV, PIN solar cell physics, for calculating the PIN IV in terms of measurable device parameters, and supplements these results with adequate numerical simulations. I. INTRODUCTION In what follows, the DC IVs of three different devices are The exponential DC current-voltage (IV) characteristic of numerically simulated. The first device is a PN diode. At the PN junction obeys the Shockley Diode equation [1]. high bias it has a linear IV. The second device is a PIN With an increasing forward bias (V) the junction’s band- diode having a small I-layer width. Interestingly its high bending decreases, and approximately at V = Vbi (the built- bias IV is linear too, and is, in fact, very similar. The third in potential) the bands become flat. More precisely, for V ≥ device is a PIN diode having a large I-layer width. Its high VK (the knee voltage, VK ≤ Vbi), the IV becomes linear due bias IV is parabolic and, is, therefore, very different. In to the series resistance (RS) and the energy bands also tilt, other words, a PIN diode can have a linear or a parabolic IV instead of only flattening, owing to an ohmic voltage drop. depending on its device parameter values. In the later In other words for an applied bias V < VK the voltage drop portions of this article, detailed analytical expressions of the across the junction is mostly diffusive, but for V ≥ VK the series resistances and the knee voltages are derived from drop becomes ohmic. first principles. Using these, the PIN DC IV can be exactly The PN diode, as discussed above, is widely published in written down. The analytical results match the numerically text books and is also taught in classrooms. The PIN diode, simulated ones excellently. This proves that the conceptual on the other hand, is lesser-known. Although some understanding of the PIN IVs outlined here is sound, analytical and numerical calculations were carried out on it practical, and accurate. It also proves that under the several decades ago [2-4], a proper chapter explaining the assumptions considered in this article, the PIN diode is PIN DC IV characteristic is still missing from the textbooks. analytically solvable for all practical purposes. The old papers are mathematically involved, and the simple All calculations assume that the I-layer’s width is fact that the I-layer’s series resistance makes the high bias appreciably greater than the material’s intrinsic Debye PIN IV parabolic instead of linear is buried deep inside their length. This is not a poor assumption because a wide range calculations. of practical devices can fall in this category. It is also noted With increasing forward bias, as minority carrier that the intrinsic Debye length decreases at a higher forward concentrations increase in the P and the N layers [1], the I- bias. Therefore, for a Silicon PIN diode, for any I-layer layer of the PIN diode is increasingly flooded with electrons width greater than about 10 μm, the calculations presented here hold because the intrinsic Debye length becomes Research funding is through IIT Bombay Grant RD/0118-MNRE000-001. negligibly small at and beyond the knee voltage. Copyright notice: 978-1-7281-8660-3/20/$31.00 @2020 IEEE II. NUMERICAL SIMULATIONS has a much smaller I-layer width, and PIN 2 has a much One PN and two PIN devices are simulated using a larger I-layer width, compared to their respective P and N software platform which solves the Poisson Equations, layer widths. Table I summarizes the semiconductor device Continuity Equations, and Drift-Diffusion Equations parameters that were used to perform these simulations. simultaneously using a discrete mesh and a generalized Equal carrier mobilities are considered for electrons and Newton iteration method [5]. The PIN 1 device differs from holes (μe = μh = 500 cm2V-1s-1) in all the device layers. The the PN device in that a thin I-layer is present in the former. material considered is Silicon. Room temperature (300 K) is The two PIN devices differ only in their layer widths. PIN 1 assumed. TABLE I. SIMULATION PARAMETERS P-layer I-layer N-layer Width Doping SRH Width Doping SRH Width Doping SRH Device dP Density Recombination di Density Recombination dN Density Recombination NA Time Ni Time ND Time τP τi τN PN 100 μm 1016 /cc 0.1 ns - - - 100 μm 1016 /cc 0.1 ns PIN 1 100 μm 1016 /cc 0.1 ns 10 μm 0 1 Ms 100 μm 1016 /cc 0.1 ns PIN 2 10 μm 1016 /cc 0.1 ns 100 μm 0 1 Ms 10 μm 1016 /cc 0.1 ns III. SIMULATION RESULTS The most important point to note here is that, for both the Fig. 1 depicts the simulated energy band diagram for the PIN 1 and PIN 2 devices, there is negligible electric field in PIN 2 device. The solid red lines in Fig. 1 show the the bulk of the I-layer. This is because, for applied biases approximated band diagram obtained under the assumption lesser than the knee voltage, the number of carriers in the that the intrinsic Debye length is negligible. This red band intrinsic region is sufficiently large to shield any field from diagram is assumed for all analytical calculations henceforth. penetrating. When the bias exceeds the knee voltage, the This is true for both the PIN 1 and PIN 2 devices. The electric field starts to tilt the energy bands. simulated band diagram for the PIN 1 device is qualitatively Fig. 2 shows the simulated current density (J) vs applied similar to Fig. 1, and is, therefore, not shown here. The PN voltage (V) plots, in the semi log mode, for all the three band diagram is similar to the one with parabolic bands devices considered in Table I. At low forward bias all the commonly found in textbooks [1]. three JVs are linear. This linearity can be explained by Shockley’s Diode Equation [1], which is characterized by a -3.5 saturation current density (JS) and an ideality factor (nID). The linearity extends only up to the knee voltage VK. This is Vbi - VD -4.0 how the knee voltage is defined in this article. Beyond VK effect of series resistance enters, and the semilog JV P becomes sublinear. JS and nID are obtained for each device E (eV) -4.5 i using linear curve fitting. N -5.0 20 -5.5 15 0.5 V 0 20 40 60 80 100 120 x (µm) 10 ln (J) Fig. 1. Simulated (black) and approximated (solid red) energy band 5 diagram for the PIN 2 device at V = VD = 0.2 V. 0 PN For all the three devices, the analytically calculated built- -5 0.4 V PIN 1 in voltage [1] Vbi = VT ln(NAND/ni2) = 0.69 V matches the PIN 2 simulation results well. Here, VT = kBT/q is the thermal -10 0.0 0.5 1.0 1.5 2.0 2.5 3.0 voltage, and ni is the intrinsic carrier concentration expressed as [1] ni = (NCNV)1/2 exp(-EG/2qVT), where EG is V (V) the band gap. At low forward biases (below the knee Fig. 2. Natural logarithm of the simulated current densities plotted vs voltage), the applied voltage V is expressed as VD; i.e. for V applied forward bias. All curves are linear up to the knee voltage and are < VK, V ≈ VD. VD is called the diffusion voltage or the well fitted by the Shockley Diode Equation [1]. At higher bias, series resistance deviate them from linearity. The knee voltages are shown by junction voltage. For V > VK, an ohmic drop VR adds to VD. vertical arrows. In other words, below the knee voltage, VR is negligible. The rich variety, exhibited by the low bias slopes and the = + + (2a) knee voltages of the three devices, is the most interesting feature of Fig. 2. The low bias slopes of the two PIN (2b) - (2d) express these individual series resistances. A is devices are the same but their knee voltages are different. the device cross-sectional area. dP, dN and di are the On the other hand, the knee voltages of the PN and PIN 1 individual widths of the P, N, and I layers. The bias devices are the same but their low bias slopes are different. dependence of Ri is caused by the bias dependence of the Fig. 3 shows the same J-V characteristics for the devices, carrier concentrations [1] in the I-layer. This, in its essence, this time, in the linear scale. originates from the bias dependence of the ‘np product’, i.e. np = ni2exp(VD/VT), which is also the basis of Shockley’s 3x106 8x103 Diode Equation [1]. Here, n and p are the electron and hole Left Axis concentrations respectively (in the I-layer, n = p). In deriving PN (2b) and (2c), the minority carrier concentrations in the P or 6x103 PIN 1 the N layers are neglected. J1/2 (A1/2m-1) 2x106 J (Am-2) PIN 2 Right Axis 4x103 PIN 2 = (2b) 1x106 3 2x10 0.5 V = (2c) 0 0 = ! − (2d) # 0.4 V 0 1 2 3 4 5 6 V (V) If RP + RN >> Ri, RS ≈ RP + RN, i.e. the series resistance Fig. 3. Simulated J-V curves, obtained for all the three PN and PIN is bias independent. This makes the IV linear beyond the devices, shown in the linear scale. Beyond the knee voltage, the PN and the PIN 1 IVs are linear, and the PIN 2 IV is parabolic. Knee voltages are knee voltage. Both the PN and the PIN 1 devices show this shown by vertical arrows. kind of behavior. If, instead, Ri >> RP + RN, RS ≈ Ri, and the series resistance is bias dependent. This leads to a parabolic IV, as for the PIN 2 device. In the case where (RP + RN) and Unlike Fig. 2, which helps in extracting the JS and nID of Ri are comparable, the high bias PIN IV ends up being the three diodes and highlights the fact that the PIN diode obeys the Shockley Equation too, Fig. 3 is more towards the between linear and parabolic. (3) gives the complete main focus of this article in that it shows how the PN and the analytical expression for the PIN IV. Here, AJRS = VR. PIN IVs differ. In other words, beyond their respective knee voltages (that are marked by two vertical arrows in Fig. 3), $ = $% + & (3) the PIN 1 device shows a linear IV and the PIN 2 device shows a parabolic IV. The parabolicity of the PIN 2 IV, beyond VK,PIN2 = 0.4 V, is confirmed by plotting the √J-V The exact method of obtaining the series-resistance- curve and ensuring its linearity. Additionally, it is to be affected diode IV is simple. One starts with a value of VD, noted that, beyond the knee voltage, the PIN 1 IV is very which, to begin with, can be any small voltage typical of similar to the PN IV. This is because the very thin I-layer in diodes. Then, using (1), the current density J can be the PIN 1 device hardly changes the series resistance. In obtained. (2), then, yields RS. Finally, using (3), the total what follows in this article, explicit analytical expressions voltage V is obtained. The complete IV can thus be are provided for both the high bias slopes and the knee generated by considering a range of VD. Such a process voltages of the PIN JVs (or, √JVs). works for both PN and PIN diodes. A theoretical study describing the effect of a variable I- layer width on the PIN IV, was reported in a conference IV. ANALYTICAL DEVICE MODELING proceeding in 2010 [6]. Although that work depicts some The rest of this article derives exact analytical interesting Sentaurus TCAD simulations, the fact that a PIN expressions for the complete PIN IV, the knee voltages, and IV, in principle, can change from linear to parabolic when the RS affected high bias slopes. At low bias (i.e. for V < the I-layer width is increased is not mentioned in that VK) the J-V curves of all the three devices obey the publication. Shockley Diode Equation [1-3] given in (1). The slope of the √J-V curve for the PIN 2 device (Fig. 3, right axis) is denoted by MRS. For the PIN 1 device, ≈ (1) similarly, MRS denotes the slope of the linear J-V curve (Fig. 3, left axis). The quantity MRS, here, has two different dimensions (measurement units) for the PIN 1 and the PIN 2 At high bias (V ≥ VK) the series resistance dominates the devices. For PIN 1, MRS relates directly to RS. For PIN 2, the IV. The total series resistance RS of the PIN diode is given relation with series resistance is more indirect owing to the by the sum of the individual series resistances of the P, N, square-root involved. The analytical expressions for the two and I layers, i.e. RP, RN, and Ri. This is expressed in (2a). MRSs are given in (4) and (5). Note that for both the PIN 1 and PIN 2 devices, dP = dN = d, and NA = ND = N as per One notable work in which the exact expression for the Table I. series resistance affected PN IV is calculated using the Lambert W function is Ref. [7]. At the time of submitting this article, no theoretical work is found in the literature which analytically expresses the knee voltage of a PIN '( , * + = - - (4) diode. (6) and (7) finally express the knee voltages of the , / . . PIN 1 and PIN 2 devices. 12 + + ! $3, * + = $4 − $5 67 8 + : (6) '( , * # = (5) 9 012 The knee voltage is calculated in this work following a 12 very simple technique. The equivalent resistance of the $3, * # = $4 − 2$5 67 8 ! 9 : (7) diode is first obtained by differentiating the Shockley Diode Equation. Then the knee voltage is defined to be the voltage at which the diode (diffusion) resistance and the (ohmic) Table II compares the simulated values with the ones series resistance become equal. It is to be noted that, the analytically calculated using (4)-(7). All the calculated and electrical resistance, defined as dV/dI or (dI/dV)-1, can, in simulated quantities match excellently. This demonstrates principle, be calculated from any non-linear current-voltage the truthfulness of the derived equations. characteristic. TABLE II. COMPARISON OF SIMULATED AND CALCULATED RESULTS Device Simulated Calculated nID JS VK MRS VK MRS PN 1.8 2.8×10-1 Am-2 0.5 V 3.9×105 Ω-1m-2 - 4×105 Ω-1m-2 PIN 1 1.03 4.4×10-5 Am-2 0.5 V 3.7×105 Ω-1m-2 0.5 V 4×105 Ω-1m-2 PIN 2 1.04 3.9×10-5 Am-2 0.4 V 3.7×102 A-1/2m-1V-1 0.4 V 4.1×102 A-1/2m-1V-1 V. CONCLUSIONS ACKNOWLEDGMENT An exhaustive set of analytical equations are derived for ANRC acknowledges financial support from IIT Bombay a PIN diode. Using these equations, the complete PIN DESE Grant - RD/0118-MNRE000-001. current-voltage (IV) characteristic can be obtained easily. The truthfulness of the equations is confirmed for two REFERENCES different PIN devices, one with a linear and another with a parabolic IV, by comparing analytical calculations with [1] R. F. Pierret, Semiconductor Device Fundamentals, Addison-Wesley Publishing Company (1996) numerical simulations. Simple expressions for the PIN series [2] D. A. Kleinman, “The forward characteristic of the PIN diode”, Bell resistances and the knee voltages are derived. In brief, it is Syst. Tech. J., 35 (1956) 685-706 seen that a PIN diode’s IV can be anywhere in between a [3] A. Herlet, “The forward characteristic of Silicon power rectifiers at straight line and a parabola at high forward bias. Below the high current densities”, Solid State Electron. 11 (1968) 717-742 knee voltage, the PIN diodes’ IV obeys the Shockley Diode [4] F. Berz, “A simplified theory of the PIN diode”, Solid State Electron. 20 (1977) 709-714 Equation. [5] J. Gray, X. Wang, R. V. K. Chavali, X. Sun, A. Kanti, and J. R. An analytical expression of the PIN diode’s knee voltage Wilcox, ADEPT 2.1 (2015) https://nanohub.org/resources/adeptnpt can be used to extract important device parameters from [6] W. M. Jubadi and S. N. M. Noor, “Simulations of variable I layer experiments. Although it can be calculated following a thickness effects on silicon PIN diode IV characteristics”, IEEE simple and fundamental technique, such an analytical Symposium on Industrial Electronics and Applications (ISIEA 2010), Malaysia, 428-432 expression was absent from the literature. This work fills [7] T. C. Banwell and A. Jayakumar, “Exact analytical solution for this gap, and opens new directions towards reviving the current flow through diode with series resistance” IET Electron. Lett. fundamental physics of PIN solar cells. (2000) 36, 291-292