On the linearity and parabolicity of the PIN dark IV: the effect of series resistance Aditya N. Roy Choudhury Department of Energy Science and Engineering Indian Institute of Technology Bombay Mumbai, India roychoudhury.aditya.2019@gmail.com Shaibal K. Sarkar Department of Energy Science and Engineering Indian Institute of Technology Bombay Mumbai, India shaibal.sarkar@iitb.ac.in Abstract — The article provides simple analytical expressions for calculating the exact current-voltage (IV) characteristic of a PIN diode. Focus is on the differences between the PIN and the PN IVs. The I-layer width is assumed to be much greater than the material’s intrinsic Debye length. Truthfulness of all derived equations is verified by comparing with numerical simulations. As expected, the IV gets limited by the device’s series resistance (R S ) at high forward bias. However, whether the PIN IV is linear, or parabolic (or in between) depends on which of the P, I, and/or N layer(s) dominate(s) the R S A transition from linear to parabolic behavior is observed as the width of the intrinsic layer is increased. Equations for the knee voltages and series resistances are also analytically derived, and are corroborated with numerical simulations. Keywords — PIN diode, IV characteristics, series resistance, dark IV, PIN solar cell I. I NTRODUCTION The exponential DC current-voltage (IV) characteristic of the PN junction obeys the Shockley Diode equation [1]. With an increasing forward bias (V) the junction’s band- bending decreases, and approximately at V = V bi (the built- in potential) the bands become flat. More precisely, for V ≥ V K (the knee voltage, V K ≤ V bi ), the IV becomes linear due to the series resistance (R S ) and the energy bands also tilt, instead of only flattening, owing to an ohmic voltage drop. In other words for an applied bias V < V K the voltage drop across the junction is mostly diffusive, but for V ≥ V K the drop becomes ohmic. The PN diode, as discussed above, is widely published in text books and is also taught in classrooms. The PIN diode, on the other hand, is lesser-known. Although some analytical and numerical calculations were carried out on it several decades ago [2-4], a proper chapter explaining the PIN DC IV characteristic is still missing from the textbooks. The old papers are mathematically involved, and the simple fact that the I-layer’s series resistance makes the high bias PIN IV parabolic instead of linear is buried deep inside their calculations. With increasing forward bias, as minority carrier concentrations increase in the P and the N layers [1], the I- layer of the PIN diode is increasingly flooded with electrons and holes [2-4]. This phenomenon causes a conductivity modulation in the device. Therefore the resistivity of the I- layer changes appreciably whereas that of the P and the N layers do not. In other words the I-layer’s series resistance becomes bias dependent. This makes the high bias PIN IV parabolic. The high bias PN IV, on the other hand, is always linear. As solar cells rise to occupy a significant share of the present semiconductor technology and financial market, a complete, accurate, and easy-to-understand theory of the PIN IV becomes an immediate necessity. To serve this end, this article questions: ‘how is the PIN diode’s IV different than the PN diode’s IV?’, and ‘what are the equations for the knee voltages and series resistances of the PIN diode?’. It provides simple expressions, derived from fundamental physics, for calculating the PIN IV in terms of measurable device parameters, and supplements these results with adequate numerical simulations. In what follows, the DC IVs of three different devices are numerically simulated. The first device is a PN diode. At high bias it has a linear IV. The second device is a PIN diode having a small I-layer width. Interestingly its high bias IV is linear too, and is, in fact, very similar. The third device is a PIN diode having a large I-layer width. Its high bias IV is parabolic and, is, therefore, very different. In other words, a PIN diode can have a linear or a parabolic IV depending on its device parameter values. In the later portions of this article, detailed analytical expressions of the series resistances and the knee voltages are derived from first principles. Using these, the PIN DC IV can be exactly written down. The analytical results match the numerically simulated ones excellently. This proves that the conceptual understanding of the PIN IVs outlined here is sound, practical, and accurate. It also proves that under the assumptions considered in this article, the PIN diode is analytically solvable for all practical purposes. All calculations assume that the I-layer’s width is appreciably greater than the material’s intrinsic Debye length. This is not a poor assumption because a wide range of practical devices can fall in this category. It is also noted that the intrinsic Debye length decreases at a higher forward bias. Therefore, for a Silicon PIN diode, for any I-layer width greater than about 10 μm, the calculations presented here hold because the intrinsic Debye length becomes negligibly small at and beyond the knee voltage. Research funding is through IIT Bombay Grant RD/0118-MNRE000-001. Copyright notice: 978-1-7281-8660-3/20/$31.00 @2020 IEEE II. NUMERICAL SIMULATIONS One PN and two PIN devices are simulated using a software platform which solves the Poisson Equations, Continuity Equations, and Drift-Diffusion Equations simultaneously using a discrete mesh and a generalized Newton iteration method [5]. The PIN 1 device differs from the PN device in that a thin I-layer is present in the former. The two PIN devices differ only in their layer widths. PIN 1 has a much smaller I-layer width, and PIN 2 has a much larger I-layer width, compared to their respective P and N layer widths. Table I summarizes the semiconductor device parameters that were used to perform these simulations. Equal carrier mobilities are considered for electrons and holes (μ e = μ h = 500 cm 2 V -1 s -1 ) in all the device layers. The material considered is Silicon. Room temperature (300 K) is assumed. TABLE I. SIMULATION PARAMETERS Device P-layer I-layer N-layer Width d P Doping Density N A SRH Recombination Time τ P Width d i Doping Density N i SRH Recombination Time τ i Width d N Doping Density N D SRH Recombination Time τ N PN PIN 1 PIN 2 100 μm 100 μm 10 μm 10 16 /cc 10 16 /cc 10 16 /cc 0.1 ns 0.1 ns 0.1 ns - 10 μm 100 μm - 0 0 - 1 Ms 1 Ms 100 μm 100 μm 10 μm 10 16 /cc 10 16 /cc 10 16 /cc 0.1 ns 0.1 ns 0.1 ns III. SIMULATION RESULTS Fig. 1 depicts the simulated energy band diagram for the PIN 2 device. The solid red lines in Fig. 1 show the approximated band diagram obtained under the assumption that the intrinsic Debye length is negligible. This red band diagram is assumed for all analytical calculations henceforth. This is true for both the PIN 1 and PIN 2 devices. The simulated band diagram for the PIN 1 device is qualitatively similar to Fig. 1, and is, therefore, not shown here. The PN band diagram is similar to the one with parabolic bands commonly found in textbooks [1]. 0 20 40 60 80 100 120 -5.5 -5.0 -4.5 -4.0 -3.5 N i E (eV) x ( μ m) V bi - V D P Fig. 1. Simulated (black) and approximated (solid red) energy band diagram for the PIN 2 device at V = V D = 0.2 V. For all the three devices, the analytically calculated built- in voltage [1] V bi = V T ln(N A N D /ni 2 ) = 0.69 V matches the simulation results well. Here, V T = k B T/q is the thermal voltage, and n i is the intrinsic carrier concentration expressed as [1] n i = (N C N V ) 1/2 exp(-E G /2qV T ), where E G is the band gap. At low forward biases (below the knee voltage), the applied voltage V is expressed as V D ; i.e. for V < V K , V ≈ V D . V D is called the diffusion voltage or the junction voltage. For V > V K , an ohmic drop V R adds to V D In other words, below the knee voltage, V R is negligible. The most important point to note here is that, for both the PIN 1 and PIN 2 devices, there is negligible electric field in the bulk of the I-layer. This is because, for applied biases lesser than the knee voltage, the number of carriers in the intrinsic region is sufficiently large to shield any field from penetrating. When the bias exceeds the knee voltage, the electric field starts to tilt the energy bands. Fig. 2 shows the simulated current density (J) vs applied voltage (V) plots, in the semi log mode, for all the three devices considered in Table I. At low forward bias all the three JVs are linear. This linearity can be explained by Shockley’s Diode Equation [1], which is characterized by a saturation current density (J S ) and an ideality factor (n ID ). The linearity extends only up to the knee voltage V K . This is how the knee voltage is defined in this article. Beyond V K effect of series resistance enters, and the semilog JV becomes sublinear. J S and n ID are obtained for each device using linear curve fitting. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -10 -5 0 5 10 15 20 0.5 V PN PIN 1 PIN 2 ln (J) V (V) 0.4 V Fig. 2. Natural logarithm of the simulated current densities plotted vs applied forward bias. All curves are linear up to the knee voltage and are well fitted by the Shockley Diode Equation [1]. At higher bias, series resistance deviate them from linearity. The knee voltages are shown by vertical arrows. The rich variety, exhibited by the low bias slopes and the knee voltages of the three devices, is the most interesting feature of Fig. 2. The low bias slopes of the two PIN devices are the same but their knee voltages are different. On the other hand, the knee voltages of the PN and PIN 1 devices are the same but their low bias slopes are different. Fig. 3 shows the same J-V characteristics for the devices, this time, in the linear scale. 0 1 2 3 4 5 6 0 1x10 6 2x10 6 3x10 6 0.5 V V (V) J (Am -2 ) 0.4 V 0 2x10 3 4x10 3 6x10 3 8x10 3 Left Axis PN PIN 1 PIN 2 Right Axis PIN 2 J 1/2 (A 1/2 m -1 ) Fig. 3. Simulated J-V curves, obtained for all the three PN and PIN devices, shown in the linear scale. Beyond the knee voltage, the PN and the PIN 1 IVs are linear, and the PIN 2 IV is parabolic. Knee voltages are shown by vertical arrows. Unlike Fig. 2, which helps in extracting the J S and n ID of the three diodes and highlights the fact that the PIN diode obeys the Shockley Equation too, Fig. 3 is more towards the main focus of this article in that it shows how the PN and the PIN IVs differ. In other words, beyond their respective knee voltages (that are marked by two vertical arrows in Fig. 3), the PIN 1 device shows a linear IV and the PIN 2 device shows a parabolic IV. The parabolicity of the PIN 2 IV, beyond V K,PIN2 = 0.4 V, is confirmed by plotting the √J-V curve and ensuring its linearity. Additionally, it is to be noted that, beyond the knee voltage, the PIN 1 IV is very similar to the PN IV. This is because the very thin I-layer in the PIN 1 device hardly changes the series resistance. In what follows in this article, explicit analytical expressions are provided for both the high bias slopes and the knee voltages of the PIN JVs (or, √JVs). IV. ANALYTICAL DEVICE MODELING The rest of this article derives exact analytical expressions for the complete PIN IV, the knee voltages, and the R S affected high bias slopes. At low bias (i.e. for V < V K ) the J-V curves of all the three devices obey the Shockley Diode Equation [1-3] given in (1). ≈ (1) At high bias (V ≥ V K ) the series resistance dominates the IV. The total series resistance R S of the PIN diode is given by the sum of the individual series resistances of the P, N, and I layers, i.e. R P , R N , and R i . This is expressed in (2a). = + + (2a) (2b) - (2d) express these individual series resistances. A is the device cross-sectional area. d P , d N and d i are the individual widths of the P, N, and I layers. The bias dependence of R i is caused by the bias dependence of the carrier concentrations [1] in the I-layer. This, in its essence, originates from the bias dependence of the ‘np product’, i.e. np = n i2 exp(V D /V T ), which is also the basis of Shockley’s Diode Equation [1]. Here, n and p are the electron and hole concentrations respectively (in the I-layer, n = p). In deriving (2b) and (2c), the minority carrier concentrations in the P or the N layers are neglected. = (2b) = (2c) = ! − # (2d) If R P + R N >> R i , R S ≈ R P + R N , i.e. the series resistance is bias independent. This makes the IV linear beyond the knee voltage. Both the PN and the PIN 1 devices show this kind of behavior. If, instead, R i >> R P + R N , R S ≈ R i , and the series resistance is bias dependent. This leads to a parabolic IV, as for the PIN 2 device. In the case where (R P + R N ) and R i are comparable, the high bias PIN IV ends up being between linear and parabolic. (3) gives the complete analytical expression for the PIN IV. Here, AJR S = V R $ = $ % + & (3) The exact method of obtaining the series-resistance- affected diode IV is simple. One starts with a value of V D , which, to begin with, can be any small voltage typical of diodes. Then, using (1), the current density J can be obtained. (2), then, yields R S . Finally, using (3), the total voltage V is obtained. The complete IV can thus be generated by considering a range of V D . Such a process works for both PN and PIN diodes. A theoretical study describing the effect of a variable I- layer width on the PIN IV, was reported in a conference proceeding in 2010 [6]. Although that work depicts some interesting Sentaurus TCAD simulations, the fact that a PIN IV, in principle, can change from linear to parabolic when the I-layer width is increased is not mentioned in that publication. The slope of the √J-V curve for the PIN 2 device (Fig. 3, right axis) is denoted by M RS For the PIN 1 device, similarly, M RS denotes the slope of the linear J-V curve (Fig. 3, left axis). The quantity M RS , here, has two different dimensions (measurement units) for the PIN 1 and the PIN 2 devices. For PIN 1, M RS relates directly to R S . For PIN 2, the relation with series resistance is more indirect owing to the square-root involved. The analytical expressions for the two M RS s are given in (4) and (5). Note that for both the PIN 1 and PIN 2 devices, d P = d N = d, and N A = N D = N as per Table I. ' (,*+ = , - . - . / (4) ' (,*# = ! 01 2 (5) The knee voltage is calculated in this work following a very simple technique. The equivalent resistance of the diode is first obtained by differentiating the Shockley Diode Equation. Then the knee voltage is defined to be the voltage at which the diode (diffusion) resistance and the (ohmic) series resistance become equal. It is to be noted that, the electrical resistance, defined as dV/dI or (dI/dV) -1 , can, in principle, be calculated from any non-linear current-voltage characteristic. One notable work in which the exact expression for the series resistance affected PN IV is calculated using the Lambert W function is Ref. [7]. At the time of submitting this article, no theoretical work is found in the literature which analytically expresses the knee voltage of a PIN diode. (6) and (7) finally express the knee voltages of the PIN 1 and PIN 2 devices. $ 3,*+ = $ 4 − $ 5 67 8 1 2 + + + 9 : (6) $ 3,*# = $ 4 − 2$ 5 67 8 1 2 ! 9 : (7) Table II compares the simulated values with the ones analytically calculated using (4)-(7). All the calculated and simulated quantities match excellently. This demonstrates the truthfulness of the derived equations. TABLE II. COMPARISON OF SIMULATED AND CALCULATED RESULTS Device Simulated Calculated n ID J S V K M RS V K M RS PN PIN 1 PIN 2 1.8 1.03 1.04 2.8×10 -1 Am -2 4.4×10 -5 Am -2 3.9×10 -5 Am -2 0.5 V 0.5 V 0.4 V 3.9×10 5 Ω -1 m -2 3.7×10 5 Ω -1 m -2 3.7×10 2 A -1/2 m -1 V -1 - 0.5 V 0.4 V 4×10 5 Ω -1 m -2 4×10 5 Ω -1 m -2 4.1×10 2 A -1/2 m -1 V -1 V. CONCLUSIONS An exhaustive set of analytical equations are derived for a PIN diode. Using these equations, the complete PIN current-voltage (IV) characteristic can be obtained easily. The truthfulness of the equations is confirmed for two different PIN devices, one with a linear and another with a parabolic IV, by comparing analytical calculations with numerical simulations. Simple expressions for the PIN series resistances and the knee voltages are derived. In brief, it is seen that a PIN diode’s IV can be anywhere in between a straight line and a parabola at high forward bias. Below the knee voltage, the PIN diodes’ IV obeys the Shockley Diode Equation. An analytical expression of the PIN diode’s knee voltage can be used to extract important device parameters from experiments. Although it can be calculated following a simple and fundamental technique, such an analytical expression was absent from the literature. This work fills this gap, and opens new directions towards reviving the fundamental physics of PIN solar cells. A CKNOWLEDGMENT ANRC acknowledges financial support from IIT Bombay DESE Grant - RD/0118-MNRE000-001. R EFERENCES [1] R. F. Pierret, Semiconductor Device Fundamentals , Addison-Wesley Publishing Company (1996) [2] D. A. Kleinman, “The forward characteristic of the PIN diode”, Bell Syst. Tech. J., 35 (1956) 685-706 [3] A. Herlet, “The forward characteristic of Silicon power rectifiers at high current densities”, Solid State Electron. 11 (1968) 717-742 [4] F. Berz, “A simplified theory of the PIN diode”, Solid State Electron. 20 (1977) 709-714 [5] J. Gray, X. Wang, R. V. K. Chavali, X. Sun, A. Kanti, and J. R. Wilcox, ADEPT 2.1 (2015) https://nanohub.org/resources/adeptnpt [6] W. M. Jubadi and S. N. M. Noor, “Simulations of variable I layer thickness effects on silicon PIN diode IV characteristics”, IEEE Symposium on Industrial Electronics and Applications (ISIEA 2010), Malaysia, 428-432 [7] T. C. Banwell and A. Jayakumar, “Exact analytical solution for current flow through diode with series resistance” IET Electron. Lett. (2000) 36, 291-292