8 7 6 5 4 3 2 1 CK 1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD REV ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ. J43 MLB SCHEMATIC DVT <REV> <ECN> <ECO_DESCRIPTION> <ECODATE> REV 6.5.0 4/09/13 D D (.csa) Date (.csa) Date Page TABLE_TABLEOFCONTENTS_HEAD Contents Sync Page TABLE_TABLEOFCONTENTS_HEAD Contents Sync 1 MASTER 61 04/02/2013 TABLE_TABLEOFCONTENTS_ITEM 1 Table of Contents MASTER TABLE_TABLEOFCONTENTS_ITEM 46 LPC+SPI Debug Connector J41_MLB 2 04/09/2013 64 02/06/2013 TABLE_TABLEOFCONTENTS_ITEM 2 BOM Configuration J41_MLB TABLE_TABLEOFCONTENTS_ITEM 47 Audio: Speaker Amp J41_MLB 3 11/16/2010 69 MASTER TABLE_TABLEOFCONTENTS_ITEM 3 BOM Variants K21_MLB TABLE_TABLEOFCONTENTS_ITEM 48 Battery Connector MASTER 4 MASTER 70 02/06/2013 TABLE_TABLEOFCONTENTS_ITEM 4 PD PARTS MASTER TABLE_TABLEOFCONTENTS_ITEM 49 DC-In & G3H Supply J41_MLB 5 02/06/2013 71 02/09/2013 TABLE_TABLEOFCONTENTS_ITEM 5 CPU GFX/NCTF/RSVD J41_MLB TABLE_TABLEOFCONTENTS_ITEM 50 PBus Supply & Battery Charger J41_MLB 6 04/02/2013 72 04/09/2013 TABLE_TABLEOFCONTENTS_ITEM 6 CPU Misc/JTAG/CFG/RSVD J41_MLB TABLE_TABLEOFCONTENTS_ITEM 51 CPU VR12.6 VCC Regulator IC J41_MLB 7 02/06/2013 73 04/09/2013 TABLE_TABLEOFCONTENTS_ITEM 7 CPU DDR3/LPDDR3 Interfaces J41_MLB TABLE_TABLEOFCONTENTS_ITEM 52 CPU VR12.5 VCC Power Stage J41_MLB 8 04/09/2013 74 02/09/2013 TABLE_TABLEOFCONTENTS_ITEM 8 CPU/PCH POWER J41_MLB TABLE_TABLEOFCONTENTS_ITEM 53 LPDDR3 Supply J41_MLB 9 02/06/2013 75 09/17/2012 TABLE_TABLEOFCONTENTS_ITEM 9 CPU/PCH GROUNDS J41_MLB TABLE_TABLEOFCONTENTS_ITEM 54 5V S4RS3 / 3.3V S5 Power Supply J41_MLB 10 01/08/2013 76 03/28/2013 TABLE_TABLEOFCONTENTS_ITEM 10 CPU Decoupling WILL_J43 TABLE_TABLEOFCONTENTS_ITEM 55 1.05V S0 Power Supply J41_MLB 12 02/07/2013 77 02/06/2013 TABLE_TABLEOFCONTENTS_ITEM 11 PCH Decoupling J41_MLB TABLE_TABLEOFCONTENTS_ITEM 56 LCD/KBD Backlight Driver J41_MLB 13 02/06/2013 78 02/06/2013 TABLE_TABLEOFCONTENTS_ITEM 12 PCH Audio/JTAG/SATA/CLK J41_MLB TABLE_TABLEOFCONTENTS_ITEM 57 Misc Power Supplies J41_MLB 14 02/06/2013 80 02/06/2013 TABLE_TABLEOFCONTENTS_ITEM 13 PCH PM/PCI/GFX J41_MLB TABLE_TABLEOFCONTENTS_ITEM 58 Power FETs J41_MLB 15 02/06/2013 81 02/06/2013 TABLE_TABLEOFCONTENTS_ITEM 14 PCH PCIe/USB/LPC/SPI/SMBus J41_MLB TABLE_TABLEOFCONTENTS_ITEM 59 Power Control J41_MLB 16 04/02/2013 83 02/06/2013 TABLE_TABLEOFCONTENTS_ITEM 15 PCH GPIO/MISC/LPIO J41_MLB TABLE_TABLEOFCONTENTS_ITEM 60 Internal DisplayPort Connector J41_MLB 18 02/06/2013 95 11/13/2012 16 CPU/PCH Merged XDP 61 Left I/O (LIO) Connector C TABLE_TABLEOFCONTENTS_ITEM 17 19 Chipset Support J41_MLB J41_MLB 02/06/2013 TABLE_TABLEOFCONTENTS_ITEM 62 100 Power Aliases CLEAN_J43 J41_MLB 01/30/2013 C TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM 20 02/15/2013 102 08/30/2012 TABLE_TABLEOFCONTENTS_ITEM 18 Project Chipset Support J41_MLB TABLE_TABLEOFCONTENTS_ITEM 63 Signal Aliases J41_MLB 22 02/12/2013 104 02/01/2013 TABLE_TABLEOFCONTENTS_ITEM 19 DDR3 VREF MARGINING J41_MLB TABLE_TABLEOFCONTENTS_ITEM 64 Func Test / No Test J41_MLB 23 02/06/2013 105 09/13/2012 TABLE_TABLEOFCONTENTS_ITEM 20 LPDDR3 DRAM Channel A (0-31) J41_MLB TABLE_TABLEOFCONTENTS_ITEM 65 Project FCT/NC/Aliases J41_MLB 24 02/06/2013 110 10/24/2012 TABLE_TABLEOFCONTENTS_ITEM 21 LPDDR3 DRAM Channel A (32-63) J41_MLB TABLE_TABLEOFCONTENTS_ITEM 66 PCB Rule Definitions CONSTRAINTS 25 02/06/2013 111 09/25/2012 TABLE_TABLEOFCONTENTS_ITEM 22 LPDDR3 DRAM Channel B (0-31) J41_MLB TABLE_TABLEOFCONTENTS_ITEM 67 CPU Constraints CONSTRAINTS 26 02/06/2013 112 11/13/2012 TABLE_TABLEOFCONTENTS_ITEM 23 LPDDR3 DRAM Channel B (32-63) J41_MLB TABLE_TABLEOFCONTENTS_ITEM 68 PCH Constraints 1 CLEAN_J43 27 02/06/2013 113 12/14/2012 TABLE_TABLEOFCONTENTS_ITEM 24 LPDDR3 DRAM Termination J41_MLB TABLE_TABLEOFCONTENTS_ITEM 69 PCH Constraints 2 J41_MLB 28 02/06/2013 114 09/25/2012 TABLE_TABLEOFCONTENTS_ITEM 25 Thunderbolt Host (1 of 2) J41_MLB TABLE_TABLEOFCONTENTS_ITEM 70 Memory Constraints CONSTRAINTS 29 02/06/2013 115 09/25/2012 TABLE_TABLEOFCONTENTS_ITEM 26 Thunderbolt Host (2 of 2) J41_MLB TABLE_TABLEOFCONTENTS_ITEM 71 Thunderbolt Constraints CONSTRAINTS 30 02/06/2013 116 01/30/2013 TABLE_TABLEOFCONTENTS_ITEM 27 TBT Power Support J41_MLB TABLE_TABLEOFCONTENTS_ITEM 72 Camera Constraints J41_MLB 32 02/07/2013 117 09/25/2012 TABLE_TABLEOFCONTENTS_ITEM 28 Thunderbolt Connector A J41_MLB TABLE_TABLEOFCONTENTS_ITEM 73 SMC Constraints CONSTRAINTS 35 02/06/2013 118 12/07/2012 TABLE_TABLEOFCONTENTS_ITEM 29 Wireless Connector J41_MLB TABLE_TABLEOFCONTENTS_ITEM 74 Project Specific Constraints J41_MLB 37 04/09/2013 119 09/25/2012 TABLE_TABLEOFCONTENTS_ITEM 30 SSD Connector J41_MLB TABLE_TABLEOFCONTENTS_ITEM 75 Project Specific Constraints CONSTRAINTS 39 04/02/2013 121 07/03/2012 TABLE_TABLEOFCONTENTS_ITEM 31 Camera 1 of 2 J41_MLB TABLE_TABLEOFCONTENTS_ITEM 76 Reference J41_MLB 40 03/20/2013 TABLE_TABLEOFCONTENTS_ITEM 32 Camera 2 of 2 J41_MLB 44 07/01/2011 TABLE_TABLEOFCONTENTS_ITEM 33 SD READER CONNECTOR MASTER 45 10/11/2010 B TABLE_TABLEOFCONTENTS_ITEM 34 46 SD CONTROLLER (GL3219) MASTER 02/07/2013 B TABLE_TABLEOFCONTENTS_ITEM 35 External A USB3 Connector J41_MLB 48 02/12/2013 TABLE_TABLEOFCONTENTS_ITEM 36 IPD Connector J41_MLB 50 02/06/2013 TABLE_TABLEOFCONTENTS_ITEM 37 SMC J41_MLB 51 02/06/2013 TABLE_TABLEOFCONTENTS_ITEM 38 SMC Shared Support J41_MLB 52 02/06/2013 TABLE_TABLEOFCONTENTS_ITEM 39 SMC Project Support J41_MLB 53 02/06/2013 TABLE_TABLEOFCONTENTS_ITEM 40 SMBus Connections J41_MLB 54 03/28/2013 TABLE_TABLEOFCONTENTS_ITEM 41 High Side Current Sensing J41_MLB 55 03/28/2013 TABLE_TABLEOFCONTENTS_ITEM 42 Voltage & Load Side Current Sensing J41_MLB 56 03/28/2013 TABLE_TABLEOFCONTENTS_ITEM 43 Debug Sensors 1 J41_MLB 58 02/06/2013 TABLE_TABLEOFCONTENTS_ITEM 44 Thermal Sensors J41_MLB 60 02/06/2013 TABLE_TABLEOFCONTENTS_ITEM 45 Fan J41_MLB A ALIASES RESOLVED Schematic / PCB #’s PRODUCT SAFETY REQUIREMENTS: PCB, UL RECOGNIZED, MIN. 130-C TEMP. RATING AND V-0 FLAME RATING PER UL 796 & UL 94. DRAWING TITLE <PART_DESCRIPTION> DRAWING NUMBER <SCH_NUM> D SIZE A PCB TO BE SILK-SCREENED WITH UL/CUL RECOGNITION MARK, MANUFACTURER’S UL FILE Apple Inc. REVISION PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION NUMBER, UL PCB MATERIAL DESIGNATION, 130-C TEMP. RATING AND V-0 FLAME RATING. R <E4LABEL> 051-9800 1 SCHEM,MLB,J43 SCH CRITICAL NOTICE OF PROPRIETARY PROPERTY: BRANCH 820-3437 1 PCBF,MLB,J43 PCB CRITICAL THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. <BRANCH> THE POSESSOR AGREES TO THE FOLLOWING: PAGE DRAWING TITLE=MLB I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 1 OF 121 ABBREV=DRAWING III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET LAST_MODIFIED=Tue Apr 9 20:06:04 2013 IV ALL RIGHTS RESERVED 1 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 BOM Groups TABLE_BOMGROUP_HEAD Alternate Parts BOM GROUP BOM OPTIONS TABLE_ALT_HEAD PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: TABLE_BOMGROUP_ITEM PART NUMBER MLB_COMMON ALTERNATE,COMMON,MLB_MISC,MLB_DEBUG:ENG,MLB_PROGPARTS TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM 376S1032 376S0855 ALL Toshiba alt for Diodes dual MLB_MISC PP5V5_DCIN:NO,TBTHV:P15V,EDP,CAM_XTAL:NO,CAM_WAKE:NO,APCLKRQ:ISOL,TPAD_INTWAKE:SHARED,USB_PWR:S3,SD_ON_MLB,VCORE_FETS TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM MLB_DEVEL:ENG ALTERNATE,BKLT:ENG,XDP_CONN,DDRVREF_DAC,S0PGOOD_ISL,DBGLED,ISNS:ENG 376S1129 376S0855 ALL NXP alt for Diodes dual TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM MLB_DEVEL:PVT XDP_CONN 376S1089 376S1128 ALL NXP alt for Diodes single TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM MLB_DEBUG:ENG DEVEL_BOM,XDP,LPCPLUS 138S0684 138S0660 ALL Murata alt to Taiyo Yuden TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM MLB_DEBUG:PVT DEVEL_BOM,BKLT:PROD,XDP,LPCPLUS,ISNS:PROD 138S0703 138S0648 ALL Murata alt to Taiyo Yuden D MLB_DEBUG:PROD BKLT:PROD,LPCPLUS,XDP,ISNS:PROD TABLE_BOMGROUP_ITEM 152S0586 152S1301 ALL Dale/Vishay alt to Cyntec TABLE_ALT_ITEM TABLE_ALT_ITEM D 372S0186 372S0185 ALL NXP alt to Diodes TABLE_ALT_ITEM 197S0479 197S0478 ALL Current Sensor Configuration 200uW Epson alt to NDK BOM GROUP BOM OPTIONS TABLE_BOMGROUP_HEAD CPU DRAM CFG Chart 376S1053 376S0604 ALL Diodes alt to Fairchild TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM 371S0713 371S0558 ALL Diodes alt to ST Micro ISNS:ENG CPU_HS_ISNS:YES,CPUVR_ISNS:YES,DRAM_ISNS:YES,P1V05_ISNS:YES,AIRPORT_ISNS:YES,SSD_ISNS:YES,LCDBKLT_ISNS:YES,P3V3S5_ISNS:YES,3V3S0_ISNS:YES,OTHER_HS_ISNS:YES,CAM_ISNS:YES,CPUDDR_ISNS:YES,PANEL_ISNS:YES VENDOR CFG 1 CFG 0 TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM 128S0371 128S0376 ALL Kemet alt to Sanyo ISNS:PROD CPU_HS_ISNS:YES,CPUVR_ISNS:YES,DRAM_ISNS:YES,P1V05_ISNS:NO,AIRPORT_ISNS:NO,SSD_ISNS:YES,LCDBKLT_ISNS:NO,P3V3S5_ISNS:NO,3V3S0_ISNS:NO,OTHER_HS_ISNS:NO,CAM_ISNS:NO,CPUDDR_ISNS:NO,PANEL_ISNS:NO HYNIX 0 0 TABLE_ALT_ITEM 128S0394 128S0415 ALL NEC alt to Sanyo SAMSUNG 1 0 TABLE_ALT_ITEM 152S1821 152S1757 ALL CPU DRAM SPD Straps MICRON 0 1 Cyntec alt to NEC TABLE_ALT_ITEM TABLE_BOMGROUP_HEAD 197S0480 197S0343 ALL NDK crystal alt to TXC BOM GROUP BOM OPTIONS ELPIDA 1 1 TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM 197S0481 197S0343 ALL Epson crystal alt to TXC DDR3:HYNIX_4GB RAMCFG0:L,RAMCFG1:L,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:HYNIX_4GB TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM 107S0254 107S0241 ALL Cyntec sense R alt to TFT DDR3:HYNIX_8GB RAMCFG0:L,RAMCFG1:L,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:HYNIX_8GB SIZE CFG 2 TABLE_ALT_ITEM 353S3452 353S1286 ALL Maxim alt to Microchip 4GB 0 TABLE_BOMGROUP_ITEM DDR3:SAMSUNG_4GB RAMCFG0:L,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:SAMSUNG_4GB TABLE_ALT_ITEM 128S0386 128S0284 ALL Kemet alt to Sanyo 8GB 1 TABLE_BOMGROUP_ITEM DDR3:SAMSUNG_8GB RAMCFG0:L,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:SAMSUNG_8GB TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM 128S0397 128S0325 ALL Kemet alt to Sanyo DDR3:ELPIDA_4GB RAMCFG0:H,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:ELPIDA_4GB TABLE_ALT_ITEM 377S0155 377S0104 ALL OnSemi alt to Infineon DIE REV CFG 3 TABLE_BOMGROUP_ITEM DDR3:ELPIDA_8GB RAMCFG0:H,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:ELPIDA_8GB TABLE_ALT_ITEM 128S0398 128S0220 ALL Kemet alt to Sanyo A 0 TABLE_BOMGROUP_ITEM DDR3:MICRON_4GB RAMCFG0:H,RAMCFG1:L,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:MICRON_4GB TABLE_ALT_ITEM 197S0542 197S0544 ALL NDK alt to TXC B 1 TABLE_ALT_ITEM 197S0545 197S0544 ALL C Programmable Parts Epson alt to TXC TABLE_ALT_ITEM C 138S0681 138S0638 ALL Taiyo alt to Samsung PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION TABLE_ALT_ITEM 138S0841 138S0638 ALL Murata alt to Samsung 335S0865 1 EEPROM,256KBIT,SPI,5MHZ,1.8V,2X3QFN U2890 CRITICAL TBTROM:BLANK TABLE_ALT_ITEM 376S1180 376S0761 ALL Renesas alt to Vishay 341S3802 1 IC,EEPROM,C/R (V23.4) EVT,J41/J41 U2890 CRITICAL TBTROM:PROG TABLE_ALT_ITEM 152S1876 152S1804 ALL TDK alt to Toko 338S1159 1 IC,SMC12-A3,40MHZ/50DMIPS MCU,9X9,157BGA U5000 CRITICAL SMC:BLANK TABLE_ALT_ITEM 107S0255 107S0240 ALL Cyntec alt to TFT 335S0809 1 64 MBIT SPI SERIAL DUAL I/O FLASH,8X6X0.8 U6100 CRITICAL BOOTROM_MAC:BLANK TABLE_ALT_ITEM 107S0250 107S0248 ALL Cyntec alt to TFT 335S0803 1 64 MBIT SPI SERIAL DUAL I/O FLASH,8X6X0.8 U6100 CRITICAL BOOTROM_NUM:BLANK 341S3809 1 IC,EFI ROM (V0071) DVT,J41/J43 U6100 CRITICAL BOOTROM:PROG Module Parts PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 337S4525 1 HSW,SR16M,PRQ,C0,1.3,15W,2+3,1.0,3M,BGA U0500 CRITICAL CPU:1.3GHZ 337S4526 1 HSW,SR16L,PRQ,C0,1.4,15W,2+3,1.1,3M,BGA U0500 CRITICAL CPU:1.4GHZ 337S4528 1 HSW,SR16H,PRQ,C0,1.7,15W,2+3,1.1,4M,BGA U0500 CRITICAL CPU:1.7GHZ 338S1113 1 IC,TBT,CR-4C,B1,PRQ,CIO,288,12X12 FC-CSP U2800 CRITICAL 338S1186 1 IC,BCM15700A2,S2 PCIE CAMERA PROCESSOR U3900 CRITICAL 607-6811 1 ASSEMBLY,SUBASSY,PCBA,HALL EFFECT,K99 J6955 CRITICAL J41_MLB 946-3892 1 J11/J13 MLB DYMAX ADHESIVE 29993-SC 0.4G GLUE CRITICAL B 825-7670 1 LABEL,TEXT,MLB,K21/K78 LABEL B 376S0964 2 MOSFET,N-CH,25V,30A,9.6M,8P 3.3X3.3 DFN Q7310,Q7320 CRITICAL VCORE_FET:REN 376S1104 2 MOSFET,N-CH,25V,30A,6.1M,8P 3.3X3.3 DFN Q7311,Q7321 CRITICAL VCORE_FET:REN 376S1173 2 MOSFET,N-CH,30V,15.3A,12M,8P 3.3X3.3 DFN Q7310,Q7320 CRITICAL VCORE_FET:VSHY 376S1174 2 MOSFET,N-CH,30V,22A,6.0M,8P 3.3X3.3 DFN Q7311,Q7321 CRITICAL VCORE_FET:VSHY 900-0090 1 SOLDERPASTE CRITICAL DRAM Parts PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 333S0677 4 IC,SDRAM,8Gb,LPDDR3-1600,178P FBGA U2300,U2400,U2500,U2600 CRITICAL DRAM_TYPE:HYNIX_4GB 333S0681 4 IC,SDRAM,16Gb,LPDDR3-1600,178P FBGA U2300,U2400,U2500,U2600 CRITICAL DRAM_TYPE:HYNIX_8GB 333S0676 4 IC,SDRAM,8Gb,LPDDR3-1600,178P FBGA U2300,U2400,U2500,U2600 CRITICAL DRAM_TYPE:SAMSUNG_4GB 333S0680 4 IC,SDRAM,16Gb,LPDDR3-1600,178P FBGA U2300,U2400,U2500,U2600 CRITICAL DRAM_TYPE:SAMSUNG_8GB 333S0678 4 IC,SDRAM,8Gb,LPDDR3-1600,178P FBGA U2300,U2400,U2500,U2600 CRITICAL DRAM_TYPE:ELPIDA_4GB 333S0666 4 CRITICAL A 333S0679 4 IC,SDRAM,16Gb,LPDDR3-1600,178P FBGA IC,SDRAM,8Gb,LPDDR3-1600,178P FBGA U2300,U2400,U2500,U2600 U2300,U2400,U2500,U2600 CRITICAL DRAM_TYPE:ELPIDA_8GB DRAM_TYPE:MICRON_4GB SYNC_MASTER=J41_MLB SYNC_DATE=04/09/2013 A PAGE TITLE BOM Configuration DRAWING NUMBER SIZE Apple Inc. <SCH_NUM> D REVISION R <E4LABEL> NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. <BRANCH> THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 2 OF 121 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 2 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 BOM Variants NOTE: All the "GOOD" BOM Configs have been de-activated TABLE_BOMGROUP_HEAD BOM NUMBER BOM NAME BOM OPTIONS TABLE_BOMGROUP_ITEM 639-4146 PCBA,MLB,GOOD,HY-4GB,J43 MLB_CMNPTS,CPU:1.3GHZ,DDR3:HYNIX_4GB TABLE_BOMGROUP_ITEM Alternate Parts 639-4293 PCBA,MLB,GOOD,HY-8GB,J43 MLB_CMNPTS,CPU:1.3GHZ,DDR3:HYNIX_8GB TABLE_ALT_HEAD PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: TABLE_BOMGROUP_ITEM PART NUMBER 639-4294 PCBA,MLB,GOOD,EL-4GB,J43 MLB_CMNPTS,CPU:1.3GHZ,DDR3:ELPIDA_4GB TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM 685-0064 685-0065 ALL Renesas alt for Vishay 639-4295 PCBA,MLB,GOOD,EL-8GB,J43 MLB_CMNPTS,CPU:1.3GHZ,DDR3:ELPIDA_8GB TABLE_BOMGROUP_ITEM 639-4745 PCBA,MLB,GOOD,MI-4GB,J43 MLB_CMNPTS,CPU:1.3GHZ,DDR3:MICRON_4GB TABLE_BOMGROUP_ITEM 639-4445 PCBA,MLB,BETTER,HY-4GB,J43 MLB_CMNPTS,CPU:1.3GHZ,DDR3:HYNIX_4GB TABLE_ALT_ITEM D 639-4446 PCBA,MLB,BETTER,HY-8GB,J43 MLB_CMNPTS,CPU:1.3GHZ,DDR3:HYNIX_8GB TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM 333S0704 333S0700 ALL Elpida CAM DRAM alt to Hynix D 639-4447 PCBA,MLB,BETTER,EL-4GB,J43 MLB_CMNPTS,CPU:1.3GHZ,DDR3:ELPIDA_4GB TABLE_BOMGROUP_ITEM 639-4448 PCBA,MLB,BETTER,EL-8GB,J43 MLB_CMNPTS,CPU:1.3GHZ,DDR3:ELPIDA_8GB TABLE_BOMGROUP_ITEM 639-4746 PCBA,MLB,BETTER,MI-4GB,J43 MLB_CMNPTS,CPU:1.3GHZ,DDR3:MICRON_4GB TABLE_BOMGROUP_ITEM 639-4755 PCBA,MLB,BEST,HY-4GB,J43 MLB_CMNPTS,CPU:1.7GHZ,DDR3:HYNIX_4GB TABLE_BOMGROUP_ITEM 639-4756 PCBA,MLB,BEST,HY-8GB,J43 MLB_CMNPTS,CPU:1.7GHZ,DDR3:HYNIX_8GB TABLE_BOMGROUP_ITEM 639-4757 PCBA,MLB,BEST,EL-4GB,J43 MLB_CMNPTS,CPU:1.7GHZ,DDR3:ELPIDA_4GB TABLE_BOMGROUP_ITEM 639-4758 PCBA,MLB,BEST,EL-8GB,J43 MLB_CMNPTS,CPU:1.7GHZ,DDR3:ELPIDA_8GB TABLE_BOMGROUP_ITEM 639-4759 PCBA,MLB,BEST,MI-4GB,J43 MLB_CMNPTS,CPU:1.7GHZ,DDR3:MICRON_4GB TABLE_BOMGROUP_ITEM 685-0025 CMN PTS,PCBA,MLB,J43 MLB_COMMON TABLE_BOMGROUP_ITEM 985-0018 J43 MLB DEVELOPMENT BOM MLB_DEVEL:ENG TABLE_BOMGROUP_ITEM 685-0064 VCORE FET,REN,J43 VCORE_FET:REN TABLE_BOMGROUP_ITEM 685-0065 VCORE FET,VSHY,J43 VCORE_FET:VSHY Programmable Parts C C PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 341S3758 1 IC,SMC-A3 SCPL,EXT,V22.12a19,PROTO 1,J43 U5000 CRITICAL SMC:PROG BOM Groups TABLE_BOMGROUP_HEAD BOM GROUP BOM OPTIONS TABLE_BOMGROUP_ITEM MLB_PROGPARTS BOOTROM:PROG,SMC:PROG,TBTROM:PROG B Module Parts B PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 338S1215 1 IC,GL3219,USB3 SD CARD READER,46P,LQFN U4500 CRITICAL A SYNC_MASTER=K21_MLB SYNC_DATE=11/16/2010 A PAGE TITLE Sub-BOMs BOM Variants DRAWING NUMBER SIZE PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION Apple Inc. <SCH_NUM> D 985-0018 1 J43 MLB DEVELOPMENT BOM DEVEL CRITICAL DEVEL_BOM REVISION R 685-0025 1 CMN PTS,PCBA,MLB,J43 CMNPTS CRITICAL MLB_CMNPTS <E4LABEL> NOTICE OF PROPRIETARY PROPERTY: BRANCH 685-0065 1 VCORE FET,VSHY,J43 VCOREFETS CRITICAL VCORE_FETS THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. <BRANCH> THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 3 OF 121 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 3 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 PD Module Parts PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 806-5107 1 CAN,TOPSIDE,ALT,J41/J43 TBTTOPSIDE_2P_FENCE CRITICAL 806-5108 1 CAN,TOPSIDE,COVER,ALT,J41/J43 TBTTOPSIDE_2P_COVER CRITICAL 806-3142 1 CAN,TBT,J11/J13 TBTFENCE CRITICAL 806-3215 1 CAN,COVER,TBT,J11/J13 TBTCOVER CRITICAL D 806-3216 1 CAN,MDP,J11/J13 MDPCAN CRITICAL D 806-3083 1 SHLD,USB,MLB,J11/J13 USBCAN CRITICAL 725-1792 1 INSULATOR,CPU,J41/J43 CPU_INSULATOR CRITICAL Plated Board Slot SL0400 TH-NSP 1 SL-2.3X3.9-2.9X4.5 CPU Heat Sink Mounting Bosses Can Slots Z0413 Z0410 STDOFF-4.5OD1.8H-SM STDOFF-4.5OD1.8H-SM SL0401 TH-NSP SL0402 TH-NSP 1 1 1 1 SL-1.1X0.4-1.4X0.7 SL-1.1X0.4-1.4X0.7 2x TBT pin diodes Z0411 Z0412 STDOFF-4.5OD1.8H-SM STDOFF-4.5OD1.8H-SM SL0403 SL0406 TH-NSP TH-NSP 1 C 1 4x 860-1327 1 1 SL-1.1X0.4-1.4X0.7 2x MDP Connector C SL-1.1X0.4-1.4X0.7 Fan Boss X21 Boss SSD Boss SL0405 TH-NSP SL0407 TH-NSP 1 1 Z0405 Z0414 Z0415 SL-1.1X0.45-1.4X0.75 SL-1.1X0.45-1.4X0.75 2x TBT chip STDOFF-4.5OD1.8H-SM STDOFF-4.5OD1.9H-SM STDOFF-4.5OD1.9H-SM 1 1 1 860-1327 860-1327 860-1327 SL0404 SL0408 TH-NSP TH-NSP 1 1 SL-1.1X0.4-1.4X0.7 2x USB Connector SL-1.1X0.4-1.4X0.7 EMI I/O Pogo Pins DisplayPort PogoUSB/SD Card Pogo CRITICAL CRITICAL ZS0405 ZS0406 POGO-2.0OD-3.6H-K86-K87 POGO-2.0OD-3.6H-K86-K87 SM SM 1 1 870-1938 870-1938 B B A SYNC_MASTER=MASTER SYNC_DATE=MASTER A PAGE TITLE PD PARTS DRAWING NUMBER SIZE Apple Inc. <SCH_NUM> D REVISION R <E4LABEL> NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. <BRANCH> THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 4 OF 121 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 4 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 CRITICAL OMIT_TABLE U0500 HASWELL-ULT 2C+GT2 BGA-TSP DDI Port Assignments: SYM 1 OF 19 eDP Port Assignment: 67 25 DP_TBTSNK0_ML_C_N<0> C54 DDI1_TXN0 EDP_TXN0 C45 DP_INT_ML_C_N<0> 60 67 D 67 25 OUT OUT DP_TBTSNK0_ML_C_P<0> C55 B58 DDI1_TXP0 EDP_TXP0 B46 A47 DP_INT_ML_C_P<0> OUT OUT 60 67 D 67 25 OUT DP_TBTSNK0_ML_C_N<1> DDI1_TXN1 EDP_TXN1 NC_INT_ML_CN<1> OUT 64 67 25 DP_TBTSNK0_ML_C_P<1> C58 DDI1_TXP1 EDP_TXP1 B47 NC_INT_ML_CP<1> 64 OUT OUT TBT Sink 0 DP_TBTSNK0_ML_C_N<2> B55 67 25 OUT DDI1_TXN2 C47 NC_INT_ML_CN<2> Internal panel A55 EDP_TXN2 OUT 64 67 25 OUT DP_TBTSNK0_ML_C_P<2> DDI1_TXP2 C46 A57 EDP_TXP2 NC_INT_ML_CP<2> OUT 64 67 25 OUT DP_TBTSNK0_ML_C_N<3> DDI1_TXN3 A49 B57 EDP_TXN3 NC_INT_ML_CN<3> OUT 64 67 25 OUT DP_TBTSNK0_ML_C_P<3> DDI1_TXP3 B49 DDI EDP EDP_TXP3 NC_INT_ML_CP<3> OUT 64 C51 PPVCOMP_S0_CPU 8 67 25 18 OUT DP_TBTSNK1_ML_C_N<0> DDI2_TXN0 67 25 18 DP_TBTSNK1_ML_C_P<0> C50 DDI2_TXP0 OUT 1 67 25 18 OUT DP_TBTSNK1_ML_C_N<1> C53 DDI2_TXN1 EDP_AUXN A45 DP_INT_AUXCH_C_N BI 60 67 R0530 DP_TBTSNK1_ML_C_P<1> B54 B45 DP_INT_AUXCH_C_P 24.9 67 25 18 OUT DDI2_TXP1 EDP_AUXP BI 60 67 1% TBT Sink 1 DP_TBTSNK1_ML_C_N<2> C49 1/20W 67 25 18 OUT DDI2_TXN2 MF (MUXed with HDMI DP_TBTSNK1_ML_C_P<2> B50 2 201 67 25 18 OUT DDI2_TXP2 if necessary) DP_TBTSNK1_ML_C_N<3> A53 D20 MCP_EDP_RCOMP 67 25 18 OUT DDI2_TXN3 EDP_RCOMP 67 25 18 DP_TBTSNK1_ML_C_P<3> B53 DDI2_TXP3 EDP_DISP_UTIL A43 TP_EDP_DISP_UTIL OUT MCP Daisy-Chain Strategy: CRITICAL Each corner of CPU has two testpoints. OMIT_TABLE Other corner test signals connected in U0500 daisy-chain fashion. Continuity should C HASWELL-ULT 2C+GT2 exist between both TP’s on each corner. C BGA-TSP NO_TEST SYM 17 OF 19 NO_TEST 5 MCP_DC_AW2_AY2 TRUE AY2 DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF A3 TRUE MCP_DC_A3_B3 5 MCP_DC_AW3_AY3 TRUE AY3 DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF A4 MCP_DC_A4 1 TP 5 MCP_DC_AY60 AY60 TP-P6 TP0500 TP 1 DAISY_CHAIN_NCTF TP0531 TP-P6 5 MCP_DC_AW61_AY61 TRUE AY61 DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF A60 MCP_DC_A60 1 TP TP0510 DAISY_CHAIN_NCTF A61 TRUE MCP_DC_A61_B61 TP-P6 MCP_DC_AW62_AY62 TRUE AY62 DAISY_CHAIN_NCTF 5 1 TP 5 MCP_DC_B2 B2 DAISY_CHAIN_NCTF A62 MCP_DC_A62 TP-P6 TP0511 TP 1 DAISY_CHAIN_NCTF TP0501 TP-P6 5 MCP_DC_A3_B3 TRUE B3 DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF AV1 MCP_DC_AV1 1 TP TP0520 DAISY_CHAIN_NCTF AW1 MCP_DC_AW1 TP-P6 MCP_DC_A61_B61 TRUE B61 DAISY_CHAIN_NCTF 1 TP 5 MCP_DC_B62_B63 TRUE B62 DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF AW2 TRUE MCP_DC_AW2_AY2 5 TP-P6 TP0521 DAISY_CHAIN_NCTF AW3 TRUE MCP_DC_AW3_AY3 5 B63 DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF AW61 TRUE MCP_DC_AW61_AY61 5 MCP_DC_C1_C2 TRUE C1 DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF AW62 TRUE MCP_DC_AW62_AY62 5 C2 DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF AW63 MCP_DC_AW63 1 TP TP-P6 TP0530 CRITICAL OMIT_TABLE U0500 B HASWELL-ULT 2C+GT2 BGA-TSP B SYM 18 OF 19 AT2 RSVD SPARE RSVD N23 NC NC AU44 RSVD RSVD R23 NC NC AV44 RSVD RSVD T23 NC NC D15 RSVD RSVD U10 NC NC F22 RSVD RSVD AL1 NC NC H22 RSVD RSVD AM11 NC NC J21 RSVD RSVD AP7 NC NC RSVD AU10 NC RSVD AU15 AW14 NC RSVD NC RSVD AY14 NC A SYNC_MASTER=J41_MLB SYNC_DATE=02/06/2013 A PAGE TITLE CPU GFX/NCTF/RSVD DRAWING NUMBER SIZE Apple Inc. <SCH_NUM> D REVISION R <E4LABEL> NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. <BRANCH> THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 5 OF 121 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 5 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 CRITICAL OMIT_TABLE U0500 D HASWELL-ULT 2C+GT2 D BGA-TSP 55 51 42 38 27 17 16 15 11 8 PP1V05_S0 D61 SYM 2 OF 19 64 62 59 58 NC PROC_DETECT* (IPU) PRDY* J62 XDP_CPU_PRDY_L OUT 16 64 67 (IPU) PREQ* K62 XDP_CPU_PREQ_L IN 16 64 67 R06101 MISC 67 37 CPU_CATERR_L K61 CATERR* 62 OUT 5% (IPD) PROC_TCK E60 XDP_CPU_TCK IN 16 64 67 1/20W N62 MF 67 38 BI CPU_PECI PECI (IPU) PROC_TMS E61 XDP_CPU_TMS IN 16 64 67 201 2 R0611 (IPU) PROC_TRST* E59 XDP_CPUPCH_TRST_L IN 12 16 64 67 CPU_PROCHOT_L 2 56 1 CPU_PROCHOT_R_L K63 67 51 38 37 BI PROCHOT* THERMAL JTAG 5% (IPU) PROC_TDI F63 XDP_CPU_TDI IN 16 64 67 1/20W PWR MF 67 CPU_PWRGD C61 PROCPWRGD PROC_TDO F62 XDP_CPU_TDO 16 64 67 201 OUT 67 CPU_SM_RCOMP<0> AU60 SM_RCOMP0 (IPU) BPM0* J60 XDP_BPM_L<0> 16 67 BI 67 CPU_SM_RCOMP<1> AV60 SM_RCOMP1 (IPU) BPM1* H60 XDP_BPM_L<1> 16 67 BI 67 CPU_SM_RCOMP<2> AU61 SM_RCOMP2 (IPU) BPM2* H61 XDP_BPM_L<2> 16 67 BI H62 DDR3 (IPU) BPM3* XDP_BPM_L<3> BI 16 67 1 1 1 1 TP_CPU_MEM_RESET_L AV15 K59 XDP_BPM_L<4> R0650 R0651 R0652 R0620 18 OUT SM_DRAMRST* (IPU) BPM4* H63 BI 16 67 200 121 100 10K (IPU) BPM5* XDP_BPM_L<5> BI 16 67 1% 1% 1% 5% AV61 K60 1/20W 1/20W 1/20W 1/20W 17 OUT CPU_MEMVTT_PWR_EN_LSVDDQ SM_PG_CNTL1 (IPU) BPM6* XDP_BPM_L<6> BI 16 67 MF MF MF MF J61 201 2 201 2 201 2 201 2 (IPU) BPM7* XDP_BPM_L<7> BI 16 67 PLACE_NEAR=U0500.AU60:12.7mm PLACE_NEAR=U0500.AV60:12.7mm PLACE_NEAR=U0500.AU61:12.7mm PLACE_NEAR=U0500.C61:12.7mm C C CRITICAL OMIT_TABLE U0500 HASWELL-ULT 2C+GT2 BGA-TSP SYM 19 OF 19 67 16 6 CPU_CFG<0> AC60 CFG0 (IPU) RESERVED RSVD_TP AV63 TP_MCP_RSVD_AV63 BI 67 16 6 CPU_CFG<1> AC62 CFG1 (IPU) RSVD_TP AU63 TP_MCP_RSVD_AU63 BI 67 16 CPU_CFG<2> AC63 CFG2 (IPU) BI 67 64 16 CPU_CFG<3> AA63 CFG3 (IPU) RSVD_TP C63 TP_MCP_RSVD_C63 BI 67 16 6 CPU_CFG<4> AA60 CFG4 (IPU) RSVD_TP C62 TP_MCP_RSVD_C62 BI 67 16 CPU_CFG<5> Y62 CFG5 (IPU) BI CPU_CFG<6> Y61 CFG6 (IPU) EDP_SPARE B43 67 16 BI NC 67 16 CPU_CFG<7> Y60 CFG7 (IPU) BI 67 16 6 CPU_CFG<8> V62 CFG8 (IPU) RSVD_TP A51 TP_MCP_RSVD_A51 BI 67 16 6 CPU_CFG<9> V61 CFG9 (IPU) RSVD_TP B51 TP_MCP_RSVD_B51 B 67 16 6 BI BI CPU_CFG<10> V60 U60 CFG10 (IPU) B 67 16 BI CPU_CFG<11> CFG11 (IPU) RSVD_TP L60 TP_MCP_RSVD_L60 67 16 CPU_CFG<12> T63 CFG12 (IPU) BI CPU_CFG<13> T62 CFG13 (IPU) RSVD N60 67 16 BI NC 67 16 CPU_CFG<14> T61 CFG14 (IPU) BI CPU_CFG<15> T60 CFG15 (IPU) RSVD W23 67 16 BI NC CFG<10>:SAFE MODE BOOT 1 = NORMAL OPERATION 0 = POWER FEATURES NOT ACTIVE AA62 RSVD Y22 NC 16 BI CPU_CFG<16> CFG16 (IPU) CFG<9> :NO SVID-CAPABLE VR 1 = VR SUPPORTS SVID 0 = VR DOES NOT SUPPORT SVID CPU_CFG<18> U63 16 BI CFG18 (IPU) CFG<8> :ALLOW NOA ON LOCKED UNITS 1 = NORMAL OPERATION 0 = NOA ALWAYS UNLOCKED AA61 PROC_OPI_COMP AY15 CPU_OPI_RCOMP 16 BI CPU_CFG<17> CFG17 (IPU) CFG<4> :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED CPU_CFG<19> U62 16 CFG19 (IPU) CFG<1> :PCH-LESS MODE 1 = NORMAL OPERATION 0 = PCH-LESS MODE BI RSVD AV62 NC 1 R0690 CFG<0> :RESET SEQUENCE STALL 1 = NORMAL OPERATION 0 = STALL AFTER PCU PLL LOCK CPU_CFG_RCOMP V63 CFG_RCOMP RSVD D58 49.9 NC 1% A5 1/20W NC RSVD MF These can be placed close to J1800 VSS P22 2 201 and are only for debug access E1 RSVD VSS N21 NC D1 RSVD CPU_CFG<10> 6 16 67 NC J20 RSVD CPU_CFG<9> 6 16 67 NC H18 RSVD RSVD P20 CPU_CFG<8> 6 16 67 NC NC PCH_TD_IREF B12 TD_IREF RSVD R20 CPU_CFG<1> 6 16 67 NC CPU_CFG<0> 6 16 67 NOSTUFF HSW_PRE_ES2 NOSTUFF NOSTUFF NOSTUFF R06801 1 R0685 49.9 8.25K R06401 1 R0639 R06381 1 R0631 1 R0630 1% 1/20W 1% 1/20W 1K 1K 1K 1K 1K MF MF 5% 5% 5% 5% 5% 201 2 2 201 1/20W 1/20W 1/20W 1/20W 1/20W MF MF MF MF MF 201 2 2 201 201 2 2 201 2 201 A SYNC_MASTER=J41_MLB SYNC_DATE=04/02/2013 A NOTE: Pre-ES2 CPUs have issue with Sx cycling, must set CFG<9> low to avoid PAGE TITLE issue, but this locks CPU VR at 1.7V Vboot (CPU Sighting #4391569). CPU Misc/JTAG/CFG/RSVD DRAWING NUMBER SIZE CPU_CFG<4> 6 16 67 Apple Inc. <SCH_NUM> D EDP REVISION R 1 R0634 <E4LABEL> 1K NOTICE OF PROPRIETARY PROPERTY: BRANCH 5% 1/20W MF THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. <BRANCH> 2 201 THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 6 OF 121 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 6 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 CRITICAL CRITICAL OMIT_TABLE OMIT_TABLE 70 63 BI MEM_A_DQ<0> AH63 SA_DQ0 U0500 SA_CLK0* AU37 MEM_A_CLK_N<0> OUT 20 24 70 70 63 BI MEM_B_DQ<0> AY31 SB_DQ0 U0500 SB_CK0* AM38 MEM_B_CLK_N<0> OUT 22 24 70 MEM_A_DQ<1> AH62 HASWELL-ULT AV37 MEM_A_CLK_P<0> MEM_B_DQ<1> AW31 HASWELL-ULT AN38 MEM_B_CLK_P<0> 70 63 BI SA_DQ1 2C+GT2 SA_CLK0 OUT 20 24 70 70 63 BI SB_DQ1 2C+GT2 SB_CK0 OUT 22 24 70 70 63 MEM_A_DQ<2> AK63 SA_DQ2 BGA-TSP SA_CLK1* AW36 MEM_A_CLK_N<1> 21 24 70 70 63 MEM_B_DQ<2> AY29 SB_DQ2 BGA-TSP SB_CK1* AK38 MEM_B_CLK_N<1> 23 24 70 BI OUT BI OUT AK62 SYM 3 OF 19 AY36 AW29 SYM 4 OF 19 AL38 70 63 BI MEM_A_DQ<3> SA_DQ3 SA_CLK1 MEM_A_CLK_P<1> OUT 21 24 70 70 63 BI MEM_B_DQ<3> SB_DQ3 SB_CK1 MEM_B_CLK_P<1> OUT 23 24 70 70 63 MEM_A_DQ<4> AH61 SA_DQ4 70 63 MEM_B_DQ<4> AV31 SB_DQ4 BI BI MEM_A_DQ<5> AH60 AU43 MEM_A_CKE<0> MEM_B_DQ<5> AU31 AY49 MEM_B_CKE<0> MEMORY CHANNEL A MEMORY CHANNEL B 70 63 BI SA_DQ5 SA_CKE0 OUT 20 24 70 70 63 BI SB_DQ5 SB_CKE0 OUT 22 24 70 70 63 MEM_A_DQ<6> AK61 SA_DQ6 SA_CKE1 AW43 MEM_A_CKE<1> 20 24 70 70 63 MEM_B_DQ<6> AV29 SB_DQ6 SB_CKE1 AU50 MEM_B_CKE<1> 22 24 70 BI OUT BI OUT 70 63 MEM_A_DQ<7> AK60 SA_DQ7 SA_CKE2 AY42 MEM_A_CKE<2> 21 24 70 70 63 MEM_B_DQ<7> AU29 SB_DQ7 SB_CKE2 AW49 MEM_B_CKE<2> 23 24 70 D 70 63 BI BI MEM_A_DQ<8> AM63 AM62 SA_DQ8 SA_CKE3 AY43 MEM_A_CKE<3> OUT OUT 21 24 70 70 63 BI BI MEM_B_DQ<8> AY27 AW27 SB_DQ8 SB_CKE3 AV50 MEM_B_CKE<3> OUT OUT 23 24 70 D 70 63 BI MEM_A_DQ<9> SA_DQ9 70 63 BI MEM_B_DQ<9> SB_DQ9 70 63 MEM_A_DQ<10> AP63 SA_DQ10 SA_CS0* AP33 MEM_A_CS_L<0> 20 21 24 70 70 63 MEM_B_DQ<10> AY25 SB_DQ10 SB_CS0* AM32 MEM_B_CS_L<0> 22 23 24 70 BI OUT BI OUT 70 63 MEM_A_DQ<11> AP62 SA_DQ11 SA_CS1* AR32 MEM_A_CS_L<1> 20 21 24 70 70 63 MEM_B_DQ<11> AW25 SB_DQ11 SB_CS1* AK32 MEM_B_CS_L<1> 22 23 24 70 BI OUT BI OUT 70 63 MEM_A_DQ<12> AM61 SA_DQ12 70 63 MEM_B_DQ<12> AV27 SB_DQ12 BI BI 70 63 MEM_A_DQ<13> AM60 SA_DQ13 SA_ODT0 AP32 MEM_A_ODT<0> 20 21 24 63 70 70 63 MEM_B_DQ<13> AU27 SB_DQ13 SB_ODT0 AL32 MEM_B_ODT<0> 22 23 24 63 70 BI OUT BI OUT 70 63 MEM_A_DQ<14> AP61 SA_DQ14 LPDDR3 70 63 MEM_B_DQ<14> AV25 SB_DQ14 LPDDR3 BI BI 70 63 MEM_A_DQ<15> AP60 SA_DQ15 CAB3 SA_RAS* AY34 =MEM_A_RAS_L 63 70 63 MEM_B_DQ<15> AU25 SB_DQ15 CAB3 SB_RAS* AM35 =MEM_B_RAS_L 63 BI OUT BI OUT 70 63 MEM_A_DQ<16> AP58 SA_DQ16 CAB2 SA_WE* AW34 =MEM_A_WE_L 63 70 63 MEM_B_DQ<16> AM29 SB_DQ16 CAB2 SB_WE* AK35 =MEM_B_WE_L 63 BI OUT BI OUT 70 63 MEM_A_DQ<17> AR58 SA_DQ17 CAB1 SA_CAS* AU34 =MEM_A_CAS_L 63 70 63 MEM_B_DQ<17> AK29 SB_DQ17 CAB1 SB_CAS* AM33 =MEM_B_CAS_L 63 BI OUT BI OUT 70 63 MEM_A_DQ<18> AM57 SA_DQ18 70 63 MEM_B_DQ<18> AL28 SB_DQ18 BI BI 70 63 MEM_A_DQ<19> AK57 SA_DQ19 CAB4 SA_BA0 AU35 =MEM_A_BA<0> 63 70 63 MEM_B_DQ<19> AK28 SB_DQ19 CAB4 SB_BA0 AL35 =MEM_B_BA<0> 63 BI OUT BI OUT 70 63 MEM_A_DQ<20> AL58 SA_DQ20 CAB6 SA_BA1 AV35 MEM_A_CAB<6> 21 24 63 70 70 63 MEM_B_DQ<20> AR29 SB_DQ20 CAB6 SB_BA1 AM36 MEM_B_CAB<6> 23 24 63 70 BI OUT BI OUT 70 63 MEM_A_DQ<21> AK58 SA_DQ21 CAA5 SA_BA2 AY41 =MEM_A_BA<2> 63 70 63 MEM_B_DQ<21> AN29 SB_DQ21 CAA5 SB_BA2 AU49 =MEM_B_BA<2> 63 BI OUT BI OUT 70 63 MEM_A_DQ<22> AR57 SA_DQ22 70 63 MEM_B_DQ<22> AR28 SB_DQ22 BI BI 70 63 MEM_A_DQ<23> AN57 SA_DQ23 CAB9 SA_MA0 AU36 =MEM_A_A<0> 63 70 63 MEM_B_DQ<23> AP28 SB_DQ23 CAB9 SB_MA0 AP40 =MEM_B_A<0> 63 BI OUT BI OUT 70 63 MEM_A_DQ<24> AP55 SA_DQ24 CAB8 SA_MA1 AY37 =MEM_A_A<1> 63 70 63 MEM_B_DQ<24> AN26 SB_DQ24 CAB8 SB_MA1 AR40 =MEM_B_A<1> 63 BI OUT BI OUT 70 63 MEM_A_DQ<25> AR55 SA_DQ25 CAB5 SA_MA2 AR38 =MEM_A_A<2> 63 70 63 MEM_B_DQ<25> AR26 SB_DQ25 CAB5 SB_MA2 AP42 =MEM_B_A<2> 63 BI OUT BI OUT 70 63 MEM_A_DQ<26> AM54 SA_DQ26 RSVD1 SA_MA3 AP36 TP_LPDDR3_RSVD1 63 70 63 MEM_B_DQ<26> AR25 SB_DQ26 RSVD3 SB_MA3 AR42 TP_LPDDR3_RSVD3 63 BI OUT BI OUT 70 63 MEM_A_DQ<27> AK54 SA_DQ27 RSVD2 SA_MA4 AU39 TP_LPDDR3_RSVD2 63 70 63 MEM_B_DQ<27> AP25 SB_DQ27 RSVD4 SB_MA4 AR45 TP_LPDDR3_RSVD4 63 BI OUT BI OUT 70 63 MEM_A_DQ<28> AL55 SA_DQ28 CAA0 SA_MA5 AR36 =MEM_A_A<5> 63 70 63 MEM_B_DQ<28> AK26 SB_DQ28 CAA0 SB_MA5 AP45 =MEM_B_A<5> 63 BI OUT BI OUT 70 63 MEM_A_DQ<29> AK55 SA_DQ29 CAA2 SA_MA6 AV40 =MEM_A_A<6> 63 70 63 MEM_B_DQ<29> AM26 SB_DQ29 CAA2 SB_MA6 AW46 =MEM_B_A<6> 63 BI OUT BI OUT 70 63 MEM_A_DQ<30> AR54 SA_DQ30 CAA4 SA_MA7 AW39 =MEM_A_A<7> 63 70 63 MEM_B_DQ<30> AK25 SB_DQ30 CAA4 SB_MA7 AY46 =MEM_B_A<7> 63 BI OUT BI OUT 70 63 MEM_A_DQ<31> AN54 SA_DQ31 CAA3 SA_MA8 AY39 =MEM_A_A<8> 63 70 63 MEM_B_DQ<31> AL25 SB_DQ31 CAA3 SB_MA8 AY47 =MEM_B_A<8> 63 BI OUT BI OUT 70 63 21 MEM_A_DQ<32> AY58 SA_DQ32 CAA1 SA_MA9 AU40 =MEM_A_A<9> 63 70 63 MEM_B_DQ<32> AY23 SB_DQ32 CAA1 SB_MA9 AU46 =MEM_B_A<9> 63 BI OUT BI OUT 70 63 MEM_A_DQ<33> AW58 SA_DQ33 CAB7 SA_MA10 AP35 =MEM_A_A<10> 63 70 63 23 MEM_B_DQ<33> AW23 SB_DQ33 CAB7 SB_MA10 AK36 =MEM_B_A<10> 63 BI OUT BI OUT MEM_A_DQ<34> AY56 AW41 =MEM_A_A<11> MEM_B_DQ<34> AY21 AV47 =MEM_B_A<11> C 70 63 70 63 BI BI MEM_A_DQ<35> AW56 SA_DQ34 SA_DQ35 CAA7 CAA6 SA_MA11 SA_MA12 AU41 MEM_A_CAA<6> OUT OUT 63 20 24 63 70 70 63 70 63 BI BI MEM_B_DQ<35> AW21 SB_DQ34 SB_DQ35 CAA7 CAA6 SB_MA11 SB_MA12 AU47 MEM_B_CAA<6> OUT OUT 63 22 24 63 70 C 70 63 MEM_A_DQ<36> AV58 SA_DQ36 CAB0 SA_MA13 AR35 =MEM_A_A<13> 63 70 63 MEM_B_DQ<36> AV23 SB_DQ36 CAB0 SB_MA13 AK33 =MEM_B_A<13> 63 BI OUT BI OUT 70 63 MEM_A_DQ<37> AU58 SA_DQ37 CAA9 SA_MA14 AV42 =MEM_A_A<14> 63 70 63 MEM_B_DQ<37> AU23 SB_DQ37 CAA9 SB_MA14 AR46 =MEM_B_A<14> 63 BI OUT BI OUT 70 63 MEM_A_DQ<38> AV56 SA_DQ38 CAA8 SA_MA15 AU42 =MEM_A_A<15> 63 70 63 MEM_B_DQ<38> AV21 SB_DQ38 CAA8 SB_MA15 AP46 =MEM_B_A<15> 63 BI OUT BI OUT 70 63 MEM_A_DQ<39> AU56 SA_DQ39 70 63 MEM_B_DQ<39> AU21 SB_DQ39 BI BI 70 63 MEM_A_DQ<40> AY54 SA_DQ40 SA_DQSN0 AJ61 MEM_A_DQS_N<0> 63 70 70 63 MEM_B_DQ<40> AY19 SB_DQ40 SB_DQSN0 AW30 MEM_B_DQS_N<0> 63 70 BI BI BI BI 70 63 MEM_A_DQ<41> AW54 SA_DQ41 SA_DQSN1 AN62 MEM_A_DQS_N<1> 63 70 70 63 MEM_B_DQ<41> AW19 SB_DQ41 SB_DQSN1 AV26 MEM_B_DQS_N<1> 63 70 BI BI BI BI 70 63 MEM_A_DQ<42> AY52 SA_DQ42 SA_DQSN2 AM58 MEM_A_DQS_N<2> 63 70 70 63 MEM_B_DQ<42> AY17 SB_DQ42 SB_DQSN2 AN28 MEM_B_DQS_N<2> 63 70 BI BI BI BI 70 63 MEM_A_DQ<43> AW52 SA_DQ43 SA_DQSN3 AM55 MEM_A_DQS_N<3> 63 70 70 63 MEM_B_DQ<43> AW17 SB_DQ43 SB_DQSN3 AN25 MEM_B_DQS_N<3> 63 70 BI BI BI BI 70 63 MEM_A_DQ<44> AV54 SA_DQ44 SA_DQSN4 AV57 MEM_A_DQS_N<4> 63 70 70 63 MEM_B_DQ<44> AV19 SB_DQ44 SB_DQSN4 AW22 MEM_B_DQS_N<4> 63 70 BI BI BI BI 70 63 MEM_A_DQ<45> AU54 SA_DQ45 SA_DQSN5 AV53 MEM_A_DQS_N<5> 63 70 70 63 MEM_B_DQ<45> AU19 SB_DQ45 SB_DQSN5 AV18 MEM_B_DQS_N<5> 63 70 BI BI BI BI 70 63 MEM_A_DQ<46> AV52 SA_DQ46 SA_DQSN6 AL43 MEM_A_DQS_N<6> 21 63 70 70 63 MEM_B_DQ<46> AV17 SB_DQ46 SB_DQSN6 AN21 MEM_B_DQS_N<6> 23 63 70 BI BI BI BI 70 63 MEM_A_DQ<47> AU52 SA_DQ47 SA_DQSN7 AL48 MEM_A_DQS_N<7> 63 70 70 63 MEM_B_DQ<47> AU17 SB_DQ47 SB_DQSN7 AN18 MEM_B_DQS_N<7> 63 70 BI BI BI BI 70 63 MEM_A_DQ<48> AK40 SA_DQ48 70 63 MEM_B_DQ<48> AR21 SB_DQ48 BI BI 70 63 MEM_A_DQ<49> AK42 SA_DQ49 SA_DQSP0 AJ62 MEM_A_DQS_P<0> 63 70 70 63 MEM_B_DQ<49> AR22 SB_DQ49 SB_DQSP0 AV30 MEM_B_DQS_P<0> 63 70 BI BI BI BI 70 63 MEM_A_DQ<50> AM43 SA_DQ50 SA_DQSP1 AN61 MEM_A_DQS_P<1> 63 70 70 63 MEM_B_DQ<50> AL21 SB_DQ50 SB_DQSP1 AW26 MEM_B_DQS_P<1> 63 70 BI BI BI BI 70 63 MEM_A_DQ<51> AM45 SA_DQ51 SA_DQSP2 AN58 MEM_A_DQS_P<2> 63 70 70 63 MEM_B_DQ<51> AM22 SB_DQ51 SB_DQSP2 AM28 MEM_B_DQS_P<2> 63 70 BI BI BI BI 70 63 MEM_A_DQ<52> AK45 SA_DQ52 SA_DQSP3 AN55 MEM_A_DQS_P<3> 63 70 70 63 MEM_B_DQ<52> AN22 SB_DQ52 SB_DQSP3 AM25 MEM_B_DQS_P<3> 63 70 BI BI BI BI 70 63 MEM_A_DQ<53> AK43 SA_DQ53 SA_DQSP4 AW57 MEM_A_DQS_P<4> 63 70 70 63 MEM_B_DQ<53> AP21 SB_DQ53 SB_DQSP4 AV22 MEM_B_DQS_P<4> 63 70 BI BI BI BI 70 63 MEM_A_DQ<54> AM40 SA_DQ54 SA_DQSP5 AW53 MEM_A_DQS_P<5> 63 70 70 63 MEM_B_DQ<54> AK21 SB_DQ54 SB_DQSP5 AW18 MEM_B_DQS_P<5> 63 70 BI BI BI BI 70 63 MEM_A_DQ<55> AM42 SA_DQ55 SA_DQSP6 AL42 MEM_A_DQS_P<6> 21 63 70 70 63 MEM_B_DQ<55> AK22 SB_DQ55 SB_DQSP6 AM21 MEM_B_DQS_P<6> 23 63 70 BI BI BI BI 70 63 MEM_A_DQ<56> AM46 SA_DQ56 SA_DQSP7 AL49 MEM_A_DQS_P<7> 63 70 70 63 MEM_B_DQ<56> AN20 SB_DQ56 SB_DQSP7 AM18 MEM_B_DQS_P<7> 63 70 BI BI BI BI 70 63 MEM_A_DQ<57> AK46 SA_DQ57 70 63 MEM_B_DQ<57> AR20 SB_DQ57 BI BI 70 63 MEM_A_DQ<58> AM49 SA_DQ58 70 63 MEM_B_DQ<58> AK18 SB_DQ58 BI BI 70 63 MEM_A_DQ<59> AK49 SA_DQ59 70 63 MEM_B_DQ<59> AL18 SB_DQ59 BI BI 70 63 MEM_A_DQ<60> AM48 SA_DQ60 SM_VREF_CA AP49 CPU_DIMM_VREFCA 19 70 63 MEM_B_DQ<60> AK20 SB_DQ60 B 70 63 BI BI MEM_A_DQ<61> AK48 AM51 SA_DQ61 SM_VREF_DQ0 AR51 CPU_DIMMA_VREFDQ OUT OUT 19 70 63 BI BI MEM_B_DQ<61> AM20 AR18 SB_DQ61 B 70 63 BI MEM_A_DQ<62> SA_DQ62 70 63 BI MEM_B_DQ<62> SB_DQ62 70 63 MEM_A_DQ<63> AK51 SA_DQ63 SM_VREF_DQ1 AP51 CPU_DIMMB_VREFDQ 19 70 63 MEM_B_DQ<63> AP18 SB_DQ63 BI OUT BI A SYNC_MASTER=J41_MLB SYNC_DATE=02/06/2013 A PAGE TITLE CPU DDR3/LPDDR3 Interfaces DRAWING NUMBER SIZE Apple Inc. <SCH_NUM> D REVISION R <E4LABEL> NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. <BRANCH> THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 7 OF 121 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 7 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 HSW-ULT current estimates from Haswell Mobile ULT Processor EDS vol 1, doc #502406, v0.9. LPT-LP current estimates from Lynx Point-LP PCH EDS, doc #503118, v1.0. CRITICAL Note [1] current numbers from clarification email, from Srini, dated 9/10/2012 2:11pm. OMIT_TABLE PPVCC_S0_CPU 8 10 42 52 62 64 NC L59 RSVD U0500 VCC C36 32A Max J58 HASWELL-ULT C40 NC RSVD 2C+GT2 VCC 42 10 PPVMEMIO_S0_CPU BGA-TSP VCC C44 AH26 SYM 12 OF 19 C48 1.4A Max (DDR3: 1.5-1.35V) VDDQ VCC 1.1A Max (LPDDR3: 1.2V) AJ31 VDDQ HSW ULT POWER VCC C52 AJ33 VDDQ VCC C56 AJ37 VDDQ VCC E23 AN33 VDDQ VCC E25 D AP43 AR48 VDDQ VCC E27 E29 D VDDQ VCC AY35 VDDQ VCC E31 64 62 52 42 10 8 PPVCC_S0_CPU AY40 VDDQ VCC E33 AY44 VDDQ VCC E35 AY50 VDDQ VCC E37 E39 R08601 F59 VCC E41 100 VCC VCC PLACE_NEAR=U0500.C50:50.8mm 5% N58 E43 1/20W NC RSVD VCC MF AC58 E45 201 2 NC RSVD VCC 51 42 38 27 17 16 15 11 8 6 PP1V05_S0 E47 64 62 59 58 55 E63 VCC 67 51 OUT CPU_VCCSENSE_P VCC_SENSE E49 VCC TP_PPVCCIO_S0_CPU E51 1 1 MIN_LINE_WIDTH=0.4 mm VCC R0800 R0802 Max load: 300mA MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V NC AB23 RSVD VCC E53 75 130 A59 E55 1% 1% 5 PPVCOMP_S0_CPU VCCIO_OUT VCC 1/20W 1/20W MIN_LINE_WIDTH=0.4 mm E20 E57 MF MF Max load: 300mA MIN_NECK_WIDTH=0.2 mm VCCIOA_OUT VCC 201 2 R0810 2 201 VOLTAGE=1.05V AD23 RSVD VCC F24 CPU_VIDALERT_L 1 43 2 NOTE: Aliases not used on CPU supply outputs NC AA23 F28 67 51 IN NC RSVD VCC 5% to avoid any extraneous connections. AE59 F32 NC RSVD VCC 1/20W F36 R0811 MF 201 CPU_VIDALERT_R_L L62 VIDALERT* VCC F40 CPU_VIDSCLK 0 N63 VCC 67 51 OUT 1 2 CPU_VIDSCLK_R VIDSCLK F44 L63 VCC 5% CPU_VIDSOUT_R VIDSOUT F48 1/20W B59 VCC MF R0812 R0802.2: PLACE_NEAR=U0500.L63:2.54mm 17 16 IN CPU_VCCST_PWRGD VCCST_PWRGD F52 0201 VCC 0 R0810.2: PLACE_NEAR=U0500.L62:38.1mm 51 17 CPU_VR_EN F60 VR_EN 67 51 CPU_VIDSOUT 1 2 OUT VCC F56 BI CPU_VR_READY C59 R0800.2: PLACE_NEAR=R0810.1:2.54mm 51 17 IN VR_READY G23 5% VCC 1/20W D63 G25 C MF 0201 16 IN CPU_PWR_DEBUG H59 VSS PWR_DEBUG* VCC VCC G27 C P62 VSS VCC G29 TP_CPU_RSVD_P60 P60 RSVD_TP VCC G31 TP_CPU_RSVD_P61 P61 RSVD_TP VCC G33 TP_CPU_RSVD_N59 N59 RSVD_TP VCC G35 TP_CPU_RSVD_N61 N61 RSVD_TP VCC G37 T59 RSVD VCC G39 NC AD60 RSVD VCC G41 NC AD59 RSVD VCC G43 NC AA59 RSVD VCC G45 NC AE60 RSVD VCC G47 NC AC59 RSVD VCC G49 NC AG58 RSVD VCC G51 NC U59 RSVD VCC G53 CRITICAL NC V59 RSVD VCC G55 OMIT_TABLE NC 51 42 38 27 17 16 15 11 8 6 PP1V05_S0 VCC G57 62 58 11 PP1V05_S0SW_PCH_HSIO K9 VCCHSIO U0500 VCCSUS3 AH11 PP3V3_SUS 8 11 14 18 46 57 58 59 62 64 64 62 59 58 55 ???mA Max AC22 VCCST VCC H23 L10 HASWELL-ULT PPVRTC_G3H AE22 J23 1838mA Max VCCHSIO 2C+GT2 0.3mA Max[1] 12 13 17 62 64 VCCST VCC M9 VCCHSIO BGA-TSP VCCRTC AG10 AE23 VCCST VCC K23 SYM 13 OF 19 K57 VCC BYPASS=U0500.AE7:6.35mm RTC 42 38 27 17 16 15 11 8 6 64 62 59 58 55 51 PP1V05_S0 N8 VCCIO DCPRTC AE7 PPVOUT_S0_PCH_DCPRTC MIN_LINE_WIDTH=0.2 mm C0892 1 C0891 1 1 C0890 AB57 VCC VCC L22 29mA Max[1] P9 VCCIO MIN_NECK_WIDTH=0.2 mm 0.1UF 0.1UF 1UF AD57 VCC VCC M23 VOLTAGE=1.05V 20% 20% 10% 1 C0895 10V 10V 6.3V AG57 VCC VCC M57 HSIO SPI VCCSPI Y8 PP3V3_SUS CERM 2 CERM 2 2 CERM 14 11 PP1V05_S0SW_PCH_VCCUSB3PLL B18 VCCUSB3PLL 8 11 14 18 46 57 58 59 62 64 0.1UF 402 402 402 C24 VCC VCC P57 18mA Max 20% 41mA Max 2 10V BYPASS=U0500.AG10:6.35mm C28 VCC VCC U57 CERM BYPASS=U0500.AG10:6.35mm 12 11 PP1V05_S0SW_PCH_VCCSATA3PLL B11 VCCSATA3PLL VCCASW AG14 PP1V05_S0 6 8 11 15 16 17 27 38 42 402 BYPASS=U0500.AG10:6.35mm C32 VCC VCC W57 B 42mA Max VCCASW AG13 185mA Max[1] 51 55 58 59 62 64 B WF: RSVD on Sawtooth Peak rev 1.0 NC Y20 VCCAPLL OPI 11 PP1V05_S0_PCH_VCCAPLL_OPI AA21 VCCAPLL VCC1P05 J11 PP1V05_S0 6 8 11 15 16 17 27 38 42 51 55 58 59 62 64 57mA Max W21 VCCAPLL VCC1P05 H11 1499mA Max[1] VCC1P05 H15 AE8 USB3 J13 VCC1P05 NC DCPSUS3 AF22 PLACE_NEAR=U0500.AG19:2.54mm VCC1P05 AZALIA/HDA R0899 CORE AH14 5.11 2 58 17 11 PP1V5_S0SW_AUDIO_HDA VCCHDA DCPSUSBYP AG19 PPVOUT_S5_PCH_DCPSUSBYP_R 1 PPVOUT_S5_PCH_DCPSUSBYP MIN_LINE_WIDTH=0.2 mm MIN_LINE_WIDTH=0.2 mm 11mA Max DCPSUSBYP AG20 Powered in DeepSx MIN_NECK_WIDTH=0.2 mm 1% MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V 1/20W VOLTAGE=1.05V AH13 VRM/USB2/AZALIA DCPSUS2 MF-LF 201 1 C0899 NC VCCASW AE9 PP1V05_S0 6 8 11 15 16 17 27 38 42 51 55 1UF 58 59 62 64 10% VCCASW AF9 473mA Max[1] 2 6.3V CERM 62 59 58 57 46 18 14 11 8 PP3V3_SUS AC9 VCCSUS3 VCCASW AG8 402 64 AA9 BYPASS=R0899:U0500:2.54mm 59mA Max[1] VCCSUS3 GPIO/LCC DCPSUS1 AD10 NC PP3V3_S5 AH10 VCCDSW3_3 DCPSUS1 AD8 42 34 29 28 18 17 16 15 13 11 74 64 62 60 59 58 57 NC 114mA Max 74 65 64 62 61 59 56 45 30 27 18 17 15 13 12 11 8 PP3V3_S0 V8 VCC3 THERMAL SENSOR 44 43 42 41 40 39 38 36 40mA Max[1] W9 VCC3 VCCTS1_5 J15 PP1V5_S0 57 58 59 62 64 3mA Max J18 VCC3 K14 PP3V3_S0 62 64 65 74 8 11 12 13 15 17 18 27 30 36 38 11 PP1V05_S0_PCH_VCC_ICC VCC1P05 39 40 41 42 43 44 45 56 59 61 K19 VCC3 K16 1mA Max[1] VCCCLK: 200mA Max VCC1P05 A20 SERIAL IO PP1V05_S0_PCH_VCCACLKPLL A 12 11 31mA Max VCCACLKPLL VCCSDIO U8 VCCSDIO T9 PP3V3_S0 17mA Max 62 64 65 74 8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59 61 SYNC_MASTER=J41_MLB SYNC_DATE=04/09/2013 A 42 38 27 17 16 15 11 8 6 PP1V05_S0 J17 VCCCLK PAGE TITLE 64 62 59 58 55 51 VCCCLK: 200mA Max R21 VCCCLK CPU/PCH POWER ICC T21 SUS OSCILLATOR VCCCLK DRAWING NUMBER SIZE DCPSUS4 AB8 NC NC K18 VCCCLK Apple Inc. <SCH_NUM> D WF: RSVD on Sawtooth Peak rev 1.0 M20 VCCCLK REVISION NC R NC V21 VCCCLK VCCAPLL AC20 NC WF: RSVD on Sawtooth Peak rev 1.0 <E4LABEL> USB2 NOTICE OF PROPRIETARY PROPERTY: BRANCH 62 59 58 57 46 18 14 11 8 64 PP3V3_SUS AE20 VCCSUS3 VCCIO AG16 PP1V05_S0 6 8 11 15 16 17 27 38 42 51 55 58 59 62 64 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. <BRANCH> 3.3mA Max[1] AE21 VCCSUS3 VCCIO AG17 213mA Max[1] THE POSESSOR AGREES TO THE FOLLOWING: PAGE LPT LP POWER I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 8 OF 121 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 8 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 CRITICAL CRITICAL CRITICAL OMIT_TABLE OMIT_TABLE OMIT_TABLE U0500 U0500 U0500 HASWELL-ULT HASWELL-ULT HASWELL-ULT 2C+GT2 2C+GT2 2C+GT2 BGA-TSP BGA-TSP BGA-TSP SYM 14 OF 19 SYM 15 OF 19 SYM 16 OF 19 A11 VSS VSS AJ35 AP22 VSS VSS AV59 D33 VSS VSS H17 A14 VSS VSS AJ39 AP23 VSS VSS AV8 D34 VSS VSS H57 A18 VSS VSS AJ41 AP26 VSS VSS AW16 D35 VSS VSS J10 A24 VSS VSS AJ43 AP29 VSS VSS AW24 D37 VSS VSS J22 D A28 A32 VSS VSS VSS VSS AJ45 AJ47 AP3 AP31 VSS VSS VSS AW33 VSS AW35 D38 D39 VSS VSS VSS VSS J59 J63 D A36 VSS VSS AJ50 AP38 VSS VSS AW37 D41 VSS VSS K1 A40 VSS VSS AJ52 AP39 VSS VSS AW4 D42 VSS VSS K12 A44 VSS VSS AJ54 AP48 VSS VSS AW40 D43 VSS VSS L13 A48 VSS VSS AJ56 AP52 VSS VSS AW42 D45 VSS VSS L15 A52 VSS VSS AJ58 AP54 VSS VSS AW44 D46 VSS VSS L17 A56 VSS VSS AJ60 AP57 VSS VSS AW47 D47 VSS VSS L18 AA1 VSS VSS AJ63 AR11 VSS VSS AW50 D49 VSS VSS L20 AA58 VSS VSS AK23 AR15 VSS VSS AW51 D5 VSS VSS L58 AB10 VSS VSS AK3 AR17 VSS VSS AW59 D50 VSS VSS L61 AB20 VSS VSS AK52 AR23 VSS VSS AW60 D51 VSS VSS L7 AB22 VSS VSS AL10 AR31 VSS VSS AY11 D53 VSS VSS M22 AB7 VSS VSS AL13 AR33 VSS VSS AY16 D54 VSS VSS N10 AC61 VSS VSS AL17 AR39 VSS VSS AY18 D55 VSS VSS N3 AD21 VSS VSS AL20 AR43 VSS VSS AY22 D57 VSS VSS P59 AD3 VSS VSS AL22 AR49 VSS VSS AY24 D59 VSS VSS P63 AD63 VSS VSS AL23 AR5 VSS VSS AY26 D62 VSS VSS R10 AE10 VSS VSS AL26 AR52 VSS VSS AY30 D8 VSS VSS R22 AE5 VSS VSS AL29 AT13 VSS VSS AY33 E11 VSS VSS R8 AE58 VSS VSS AL31 AT35 VSS VSS AY4 E17 VSS VSS T1 AF11 VSS VSS AL33 AT37 VSS VSS AY51 F20 VSS VSS T58 AF12 VSS VSS AL36 AT40 VSS VSS AY53 F26 VSS VSS U20 AF14 VSS VSS AL39 AT42 VSS VSS AY57 F30 VSS VSS U22 AF15 VSS VSS AL40 AT43 VSS VSS AY59 F34 VSS VSS U61 AF17 VSS VSS AL45 AT46 VSS VSS AY6 F38 VSS VSS U9 AF18 VSS VSS AL46 AT49 VSS VSS B20 F42 VSS VSS V10 C AG1 AG11 VSS VSS VSS VSS AL51 AL52 AT61 AT62 VSS VSS VSS B24 VSS B26 F46 F50 VSS VSS VSS VSS V3 V7 C AG21 VSS VSS AL54 AT63 VSS VSS B28 F54 VSS VSS W20 AG23 VSS VSS AL57 AU1 VSS VSS B32 F58 VSS VSS W22 AG60 VSS VSS AL60 AU16 VSS VSS B36 F61 VSS VSS Y10 AG61 VSS VSS AL61 AU18 VSS VSS B4 G18 VSS VSS Y59 AG62 VSS VSS AM1 AU20 VSS VSS B40 G22 VSS VSS Y63 AG63 VSS VSS AM17 AU22 VSS VSS B44 G3 VSS VSS V58 AH17 VSS VSS AM23 AU24 VSS VSS B48 G5 VSS VSS AH46 AH19 VSS VSS AM31 AU26 VSS VSS B52 G6 VSS VSS V23 AH20 VSS VSS AM52 AU28 VSS VSS B56 G8 VSS VSS_SENSE E62 CPU_VCCSENSE_N 51 67 AH22 VSS VSS AN17 AU30 VSS VSS B60 H13 VSS OUT VSS AH16 AH24 VSS VSS AN23 AU33 VSS VSS C11 1 AH28 VSS VSS AN31 AU51 VSS VSS C14 R0960 AH30 AN32 AU53 100 VSS VSS VSS VSS C18 5% PLACE_NEAR=U0500.E62:50.8mm AH32 AN35 AU55 1/20W VSS VSS VSS VSS C20 MF AH34 VSS VSS AN36 AU57 VSS VSS C25 2 201 AH36 VSS VSS AN39 AU59 VSS VSS C27 AH38 VSS VSS AN40 AV14 VSS VSS C38 AH40 VSS VSS AN42 AV16 VSS VSS C39 AH42 VSS VSS AN43 AV20 VSS VSS C57 AH44 VSS VSS AN45 AV24 VSS VSS D12 AH49 VSS VSS AN46 AV28 VSS VSS D14 AH51 VSS VSS AN48 AV33 VSS VSS D18 AH53 VSS VSS AN49 AV34 VSS VSS D2 AH55 VSS VSS AN51 AV36 VSS VSS D21 AH57 AN52 AV39 VSS D23 B AJ13 VSS VSS VSS VSS AN60 AV41 VSS VSS VSS D25 B AJ14 VSS VSS AN63 AV43 VSS VSS D26 AJ23 VSS VSS AN7 AV46 VSS VSS D27 AJ25 VSS VSS AP10 AV49 VSS VSS D29 AJ27 VSS VSS AP17 AV51 VSS VSS D30 AJ29 VSS VSS AP20 AV55 VSS VSS D31 A SYNC_MASTER=J41_MLB SYNC_DATE=02/06/2013 A PAGE TITLE CPU/PCH GROUNDS DRAWING NUMBER SIZE Apple Inc. <SCH_NUM> D REVISION R <E4LABEL> NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. <BRANCH> THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 9 OF 121 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 9 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 All Intel recommendations from Intel doc #503160 Shark Bay Ultrabook Platform Power Delivery Design Guide Rev 1.0 unless stated otherwise CPU VCC Decoupling Intel recommendation (Table 5-1): 23x 22uF 0805 stuff, 7x 22uF 0805 nostuff 64 62 52 42 8 PPVCC_S0_CPU Apple implementation : 18x 10uF 0402 mirrored stuff, 1x 470uF stuff, 50x 10uF mirrored no stuff, 50x 10uF single sided no stuff CRITICAL CRITICAL CRITICAL NO STUFF CRITICAL NO STUFF NO STUFF CRITICAL NO STUFF NO STUFF CRITICAL NO STUFF CRITICAL NO STUFF CRITICAL NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF 1 C1000 1 C1001 1 C1002 1 C1003 1 C1004 1 C1005 1 C1006 1 C1007 1 C1008 1 C1009 1 C1010 1 C1011 1 C1012 1 C1013 1 C1014 1 C105A 1 C105B 1 C105C 1 C105D 1 C105E 1 C105F 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S D 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 D NO STUFF CRITICAL CRITICAL CRITICAL NO STUFF NO STUFF CRITICAL NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF 1 C1015 1 C1016 1 C1017 1 C1018 1 C1019 1 C1020 1 C1021 1 C1030 1 C104A 1 C104B 1 C104C 1 C104D 1 C104E 1 C104F 1 C106A 1 C106B 1 C106C 1 C106D 1 C106E 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF CRITICAL CRITICAL NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF CRITICAL CRITICAL 1 C1070 1 C1071 1 C1072 1 C1073 1 C1074 1 C1075 1 C1076 1 C1077 1 C1078 1 C1079 1 C1080 1 C1081 1 C1082 1 C1083 1 C1084 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 4V 2 X6S 4V 2 X6S 2 4V 2 4V 4V 2 X6S 4V 2 X6S 2 4V 2 4V 4V 2 X6S 4V 2 X6S 4V 2 X6S 2 4V 2 4V 4V 2 X6S 4V 2 X6S X6S X6S X6S X6S X6S X6S 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 NO STUFF NO STUFF NO STUFF CRITICAL CRITICAL NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF 1 C1085 1 C1086 1 C1087 1 C1088 1 C1089 1 C1090 1 C1091 1 C1092 1 C1093 1 C1094 1 C1095 1 C1096 1 C1097 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 4V 2 X6S 4V 2 X6S 2 4V 2 4V 4V 2 X6S 4V 2 X6S 2 4V 2 4V 4V 2 X6S 4V 2 X6S 4V 2 X6S 2 4V 2 4V X6S X6S X6S X6S X6S X6S 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF C 1 C1022 10UF 1 C1023 10UF 1 C1024 10UF 1 C1025 10UF 1 C1026 10UF 1 C1027 10UF 1 C1028 10UF 1 C1029 10UF 1 C1032 10UF 1 C1033 10UF 1 C1034 10UF 1 C1035 10UF 1 C1036 10UF 1 C1037 10UF 1 C1038 10UF C 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF 1 C1039 1 C1044 1 C1045 1 C1046 1 C1047 1 C1048 1 C1049 10UF 10UF 10UF 10UF 10UF 10UF 10UF 20% 20% 20% 20% 20% 20% 20% 4V 4V 4V 4V 4V 4V 4V 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 0402 0402 0402 0402 0402 0402 0402 NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF 1 C1056 1 C1057 1 C1058 1 C1059 1 C1062 1 C1063 1 C1064 1 C1065 1 C1066 1 C1067 1 C1068 1 C1069 1 C1098 1 C1099 1 C109A 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 4V 2 X6S 4V 2 X6S 2 4V 2 4V 4V 2 X6S 4V 2 X6S 2 4V 2 4V 4V 2 X6S 4V 2 X6S 4V 2 X6S 2 4V 2 4V 4V 2 X6S 4V 2 X6S X6S X6S X6S X6S X6S X6S 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF 1 C109B 1 C109C 1 C109D 1 C109E 1 C109F 1 C108A 1 C108B 1 C108C 1 C108D 1 C108E 1 C108F 1 C107A 1 C107B 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 4V 2 X6S 4V 2 X6S 2 4V 2 4V 4V 2 X6S 4V 2 X6S 2 4V 2 4V 4V 2 X6S 4V 2 X6S 4V 2 X6S 2 4V 2 4V X6S X6S X6S X6S X6S X6S 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 B B CRITICAL 1 C1031 470UF-0.0045OHM 20% 3 2 2.5V POLY-TANT SM CPU VDDQ DECOUPLING Intel recommendation (Table 5-4): 4x 2.2uF 0402, 6x 10uF 0603 42 8 PPVMEMIO_S0_CPU Apple implementation : 4x 2.2uF 0402, 6x 10uF 0402, 2x 270uF B2 no stuff 1 C1040 1 C1041 1 C1042 1 C1043 2.2UF 2.2UF 2.2UF 2.2UF 20% 20% 20% 20% 2 6.3V CERM 2 6.3V CERM 2 6.3V CERM 2 6.3V CERM 402-LF 402-LF 402-LF 402-LF 1 C1050 1 C1051 1 C1052 1 C1053 1 C1054 1 C1055 10UF 10UF 10UF 10UF 10UF 10UF 20% 20% 20% 20% 20% 20% 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 6.3V A CERM-X5R 0402-1 CERM-X5R 0402-1 CERM-X5R 0402-1 CERM-X5R 0402-1 CERM-X5R 0402-1 2 CERM-X5R 0402-1 SYNC_MASTER=WILL_J43 SYNC_DATE=01/08/2013 A PAGE TITLE CPU Decoupling DRAWING NUMBER SIZE NO STUFF Apple Inc. <SCH_NUM> D 1 1 REVISION C1060 C1061 R <E4LABEL> 270UF 270UF 2x Bulk nostuff per Harris Beach v1.0 schematic 20% 20% NOTICE OF PROPRIETARY PROPERTY: BRANCH 2 2V 2 2V TANT CASE-B2-SM TANT CASE-B2-SM THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. <BRANCH> THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 10 OF 121 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 10 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 PCH VCCASW BYPASS PCH VCCDSW3_3 BYPASS PCH VCC3_3 BYPASS (PCH 1.05V ME CORE PWR) PCH VCCIO BYPASS (PCH 3.3V DSW PWR) (PCH 3.3V GPIO/LPC PWR) 51 42 38 27 17 16 15 11 8 6 PP1V05_S0 (PCH 1.05V USB2 PWR) 64 62 59 58 55 42 34 29 28 18 17 16 15 13 8 PP3V3_S5 74 65 64 62 36 30 27 18 17 15 13 12 11 61 8 PP3V3_S0 51 42 38 27 17 16 15 11 8 6 PP1V05_S0 74 64 62 60 59 58 57 59 56 45 44 43 42 41 40 39 38 64 62 59 58 55 NO STUFF NO STUFF C1200 1 C1212 1 C1250 1 1 C1251 C1264 1 1UF 22UF 22UF 1UF 1UF 10% 20% 20% 10% 10% 6.3V 2 6.3V 6.3V 2 6.3V 6.3V 2 CERM X5R-CERM-1 2 X5R-CERM-1 2 CERM CERM 402 603 603 402 402 BYPASS=U0500.AH10:6.35mm BYPASS=U0500.V8:12.7mm BYPASS=U0500.AG16:6.35mm BYPASS=U0500.AE9:12.7mm BYPASS=U0500.AE9:6.35mm PCH VCCSPI BYPASS PCH VCC3_3 BYPASS D (PCH 3.3V SPI PWR) (PCH 3.3V THERMAL PWR) PCH VCC BYPASS PCH VCCCLK BYPASS D 64 62 59 58 57 46 18 14 11 8 PP3V3_SUS 74 65 64 62 36 30 27 18 17 15 13 12 11 61 8 PP3V3_S0 (PCH 1.05V CORE PWR) (PCH 1.05V CLK PWR) 59 56 45 44 43 42 41 40 39 38 NO STUFF 51 42 38 27 17 16 15 11 8 6 PP1V05_S0 51 42 38 27 17 16 15 11 8 6 PP1V05_S0 64 62 59 58 55 64 62 59 58 55 C1202 1 C1214 1 0.1UF 0.1UF 20% 20% 10V CERM 2 10V CERM 2 C1255 1 1 C1256 1 C1257 C1266 1 C1267 1 402 402 10UF 1UF 1UF 1UF 1UF BYPASS=U0500.Y8:6.35mm BYPASS=U0500.K14:6.35mm 20% 10% 10% 10% 10% 6.3V 2 6.3V 2 CERM 6.3V 2 CERM 6.3V 6.3V X5R CERM 2 CERM 2 603 402 402 402 402 PCH VCCSUS3_3 BYPASS BYPASS=U0500.J11:12.7mm BYPASS=U0500.J17:6.35mm (PCH 3.3V SUSPEND PWR) BYPASS=U0500.J11:6.35mm BYPASS=U0500.R21:6.35mm BYPASS=U0500.AE8:6.35mm 64 62 59 58 57 46 18 14 11 8 PP3V3_SUS PCH VCCHSIO BYPASS C1204 1 (PCH 1.05V PCIe/SATA/USB3 PWR) 22UF 62 58 11 8 PP1V05_S0SW_PCH_HSIO 20% 6.3V X5R-CERM-1 2 603 BYPASS=U0500.AC9:12.7mm C1260 1 C1261 1 1 C1262 1UF 1UF 10UF PCH VCCSUS3_3 BYPASS 10% 10% 20% 6.3V 2 6.3V 2 2 6.3V (PCH 3.3V SUSPEND RTC PWR) CERM CERM CERM-X5R 402 402 0402-1 64 62 59 58 57 46 18 14 11 8 PP3V3_SUS BYPASS=U0500.K9:6.35mm BYPASS=U0500.L10:6.35mm BYPASS=U0500.M9:6.35mm C1206 1 1UF 10% 6.3V 2 CERM 402 BYPASS=U0500.AH11:6.35mm C C CRITICAL PCH VCCACLKPLL FILTER/BYPASS PCH VCCSDIO BYPASS L1270 (PCH 1.05V ACLK PLL PWR) 51 42 38 27 17 16 15 11 8 6 PP1V05_S0 R1270 2.2UH-240MA-0.221OHM PP1V05_S0_PCH_VCCACLKPLL 8 12 (PCH 3.3V/1.8V SDIO PWR) 64 62 59 58 55 0 1 2 MIN_LINE_WIDTH=0.2 MM ??mA Max 1 2 PP1V05_S0_PCH_VCCACLKPLL_R MIN_NECK_WIDTH=0.075 MM 31mA Max 74 65 64 62 61 36 30 27 18 17 15 13 12 11 8 PP3V3_S0 MIN_LINE_WIDTH=0.2 MM 0603 VOLTAGE=1.05V 59 56 45 44 43 42 41 40 39 38 5% MIN_NECK_WIDTH=0.2 MM 1/16W VOLTAGE=1.05V C1208 1 MF-LF 402 C1270 1 C1271 1 1 C1272 47UF 47UF 1UF 1UF 20% 20% 10% 10% 6.3V 4V CERM-X5R 2 4V CERM-X5R 2 2 10V X5R CERM 2 0805-1 0805-1 402 402 BYPASS=U0500.U8:6.35mm BYPASS=U0500.A20:12.7mm BYPASS=U0500.A20:12.7mm BYPASS=U0500.A20:6.35mm CRITICAL PCH VCCCLK FILTER/BYPASS PCH VCCSUSHDA BYPASS (PCH 3.3V/1.5V HDA PWR) L1275 (PCH 1.05V VCCCLK PWR) R1275 2.2UH-240MA-0.221OHM PP1V05_S0_PCH_VCC_ICC 8 58 17 8 PP1V5_S0SW_AUDIO_HDA 0 1 2 MIN_LINE_WIDTH=0.2 MM 1 2 PP1V05_S0_PCH_VCC_ICC_R MIN_NECK_WIDTH=0.075 MM ??mA Max MIN_LINE_WIDTH=0.2 MM 0603 VOLTAGE=1.05V 5% MIN_NECK_WIDTH=0.2 MM C1210 1 1/16W MF-LF VOLTAGE=1.05V C1275 1 C1276 1 1 C1277 1UF 402 10% 47UF 47UF 1UF 6.3V 2 20% 20% 10% CERM 4V 4V 2 10V 402 CERM-X5R 2 CERM-X5R 2 X5R 0805-1 0805-1 402 BYPASS=U0500.AH14:6.35mm R1280 1 0 2 BYPASS=U0500.J18:12.7mm BYPASS=U0500.J18:12.7mm BYPASS=U0500.J18:6.35mm 5% 1/16W MF-LF CRITICAL B 402 NO STUFF PCH OPI VCCAPLL FILTER/BYPASS B L1280 (PCH 1.05V OPI PLL PWR) 2.2UH-240MA-0.221OHM PP1V05_S0_PCH_VCCAPLL_OPI 8 1 2 MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.075 MM 57mA Max 0603 VOLTAGE=1.05V NO STUFF NO STUFF C1280 1 C1281 1 1 C1282 47UF 47UF 1UF 20% 20% 10% 4V CERM-X5R 2 4V CERM-X5R 2 2 10V X5R 0805-1 0805-1 402 BYPASS=U0500.AA21:12.7mm BYPASS=U0500.AA21:12.7mm BYPASS=U0500.AA21:6.35mm CRITICAL PCH VCCSATA3PLL FILTER/BYPASS L1290 (PCH 1.05V SATA3 PLL PWR) 62 58 11 8 PP1V05_S0SW_PCH_HSIO 2.2UH-240MA-0.221OHM PP1V05_S0SW_PCH_VCCSATA3PLL 8 12 1 2 MIN_LINE_WIDTH=0.2 MM 83mA Max MIN_NECK_WIDTH=0.075 MM 42mA Max 0603 VOLTAGE=1.05V NO STUFF C1290 1 C1291 1 1 C1292 47UF 47UF 1UF 20% 20% 10% 4V CERM-X5R 2 4V CERM-X5R 2 2 10V X5R 0805-1 0805-1 402 BYPASS=U0500.B11:12.7mm BYPASS=U0500.B11:12.7mm BYPASS=U0500.B11:6.35mm A CRITICAL PCH VCCUSB3PLL FILTER/BYPASS SYNC_MASTER=J41_MLB SYNC_DATE=02/07/2013 A L1295 (PCH 1.05V USB3 PLL PWR) PAGE TITLE 2.2UH-240MA-0.221OHM 1 2 PP1V05_S0SW_PCH_VCCUSB3PLL MIN_LINE_WIDTH=0.2 MM 8 14 PCH Decoupling MIN_NECK_WIDTH=0.075 MM 41mA Max DRAWING NUMBER SIZE VOLTAGE=1.05V 0603 NO STUFF Apple Inc. <SCH_NUM> D C1295 1 C1296 1 1 C1297 REVISION 47UF 47UF 1UF R <E4LABEL> 20% 20% 10% 4V CERM-X5R 2 4V CERM-X5R 2 2 10V X5R NOTICE OF PROPRIETARY PROPERTY: BRANCH 0805-1 0805-1 402 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. <BRANCH> BYPASS=U0500.B18:12.7mm THE POSESSOR AGREES TO THE FOLLOWING: PAGE BYPASS=U0500.B18:12.7mm LPT-LP current estimates from Lynx Point-LP PCH EDS, doc #503118, v1.0 BYPASS=U0500.B18:6.35mm I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 12 OF 121 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET as well as from clarification email, from Srini, dated 9/10/2012 2:11pm. IV ALL RIGHTS RESERVED 11 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 64 62 17 13 8 PPVRTC_G3H CRITICAL OMIT_TABLE R13001 1 R1303 R13021 1 R1301 AW5 U0500 20K 20K 330K 1M 17 IN PCH_CLK32K_RTCX1 RTCX1 5% 5% 5% 5% NC_RTC_CLK32K_RTCX2 AY5 HASWELL-ULT 1/20W 1/20W 1/20W 1/20W 17 OUT RTCX2 2C+GT2 MF MF MF MF BGA-TSP 201 2 2 201 201 2 2 201 PCIe Port assignments: SATA Port assignments: SYM 5 OF 19 PCH_INTRUDER_L AU6 INTRUDER* SATA_RN0/PERN6_L3 J5 PCIE_SSD_D2R_N<3> 30 64 67 IN AV7 SATA_RP0/PERP6_L3 H5 PCIE_SSD_D2R_P<3> IN 30 64 67 PCH_INTVRMEN INTVRMEN SSD Lane 3 Primary HDD/SSD SATA_TN0/PETN6_L3 B15 RTC AV6 PCIE_SSD_R2D_C_N<3> OUT 30 67 PCH_SRTCRST_L SRTCRST* SATA_TP0/PETP6_L3 A15 PCIE_SSD_R2D_C_P<3> 30 67 D RTC_RESET_L AU7 RTCRST* OUT D SATA_RN1/PERN6_L2 J8 PCIE_SSD_D2R_N<2> IN 30 64 67 C1300 1 1 C1303 HDA_BIT_CLK R1310 33 1 2 69 HDA_BIT_CLK_R AW8 HDA_BCLK/I2S0_SCLK SATA_RP1/PERP6_L2 H8 PCIE_SSD_D2R_P<2> IN 30 64 67 1UF 1UF 69 65 61 OUT 5% 1/20W MF 201 SSD Lane 2 Reserved: ODD 10% 10V 2 10% PLACE_NEAR=U0500.AW8:1.27mm SATA_TN1/PETN6_L2 A17 PCIE_SSD_R2D_C_N<2> OUT 30 67 2 10V X5R 402 X5R 402 69 65 61 OUT HDA_SYNC R1311 33 1 2 69 5% 1/20W MF HDA_SYNC_R 201 AV11 HDA_SYNC/I2S0_SFRM (IPD-PLTRST#) SATA_TP1/PETP6_L2 B17 PCIE_SSD_R2D_C_P<2> OUT 30 67 PLACE_NEAR=U0500.AV11:1.27mm 69 65 61 OUT HDA_RST_L R1312 33 1 2 69 5% 1/20W MF HDA_RST_R_L 201 AU8 HDA_RST*/I2S_MCLK SATA_RN2/PERN6_L1 J6 PCIE_SSD_D2R_N<1> IN 30 64 67 PLACE_NEAR=U0500.AU8:1.27mm SATA_RP2/PERP6_L1 H6 PCIE_SSD_D2R_P<1> IN 30 64 67 AUDIO 69 65 61 HDA_SDIN0 AY10 HDA_SDI0/I2S0_RXD SSD Lane 1 Unused IN AU12 SATA_TN2/PETN6_L1 B14 PCIE_SSD_R2D_C_N<1> OUT 30 67 64 NC_HDA_SDIN1 HDA_SDI1/I2S1_RXD SATA_TP2/PETP6_L1 C15 PCIE_SSD_R2D_C_P<1> OUT 30 67 (IPD) SATA 69 65 61 OUT HDA_SDOUT R1313 33 1 2 69 17 5% 1/20W MF HDA_SDOUT_R 201 AU11 HDA_SDO/I2S0_TXD (IPD-PLTRST#) SATA_RN3/PERN6_L0 F5 PCIE_SSD_D2R_N<0> 30 64 67 IN PLACE_NEAR=U0500.AU11:1.27mm AW10 SATA_RP3/PERP6_L0 E5 PCIE_SSD_D2R_P<0> IN 30 64 67 TP_PCH_I2S1_TXD HDA_DOCK_EN*/I2S1_TXD AV10 SSD Lane 0 Secondary HDD/SSD TP_PCH_I2S1_SFRM HDA_DOCK_RST*/I2S1_SFRM SATA_TN3/PETN6_L0 C17 PCIE_SSD_R2D_C_N<0> OUT 30 67 SATA_TP3/PETP6_L0 D17 PCIE_SSD_R2D_C_P<0> OUT 30 67 TP_PCH_I2S1_SCLK AY8 I2S1_SCLK SATA0GP/GPIO34 V1 XDP_SSD_PCIE3_SEL_L 16 IN SATA1GP/GPIO35 U1 XDP_SSD_PCIE2_SEL_L 16 67 64 16 6 XDP_CPUPCH_TRST_L AU62 PCH_TRST* IN IN SATA2GP/GPIO36 V6 XDP_SSD_PCIE1_SEL_L 16 IN 69 64 16 XDP_PCH_TCK AE62 PCH_TCK (IPD) SATA3GP/GPIO37 AC1 XDP_SSD_PCIE0_SEL_L 16 IN IN (IPU) 69 64 16 XDP_PCH_TDI AD61 PCH_TDI (IPU) SATA_IREF A12 IN PP1V05_S0SW_PCH_VCCSATA3PLL 8 11 69 64 16 XDP_PCH_TDO AE61 PCH_TDO OUT 1 JTAG 69 64 16 IN XDP_PCH_TMS AD62 PCH_TMS (IPU) RSVD L11 NC R1370 3.01K C NC AL11 RSVD RSVD K10 NC 1% 1/20W MF C AC4 RSVD 2 201 PLACE_NEAR=U0500.C12:2.54mm NC AE63 SATA_RCOMP C12 PCH_SATA_RCOMP 16 BI PCH_JTAGX JTAGX AV2 RSVD SATALED* U3 PCH_SATALED_L 12 NC CRITICAL OMIT_TABLE U0500 HASWELL-ULT 2C+GT2 BGA-TSP SYM 6 OF 19 TP_PCIE_CLK100M_ENETSDN C43 XTAL24_IN A25 PCH_CLK24M_XTALIN CLOCK SIGNALS CLKOUT_PCIE_N0 IN 17 TP_PCIE_CLK100M_ENETSDP C42 CLKOUT_PCIE_P0 XTAL24_OUT B25 PCH_CLK24M_XTALOUT 17 OUT 12 ENETSD_CLKREQ_L U2 PCIECLKRQ0*/GPIO18 PP1V05_S0_PCH_VCCACLKPLL 8 11 PCIE_CLK100M_CAMERA_N B41 RSVD K21 1 69 32 OUT A41 CLKOUT_PCIE_N1 NC R1380 69 32 OUT PCIE_CLK100M_CAMERA_P CLKOUT_PCIE_P1 RSVD M21 NC 3.01K 1% Y5 1/20W 31 12 IN CAMERA_CLKREQ_L PCIECLKRQ1*/GPIO19 MF 2 201 PLACE_NEAR=U0500.C26:2.54mm C41 DIFFCLK_BIASREF C26 B 69 64 29 69 64 29 OUT OUT PCIE_CLK100M_AP_N PCIE_CLK100M_AP_P B42 CLKOUT_PCIE_N2 CLKOUT_PCIE_P2 PCH_DIFFCLK_BIASREF B AP_CLKREQ_L AD1 PCIECLKRQ2*/GPIO20 29 12 IN TESTLOW C35 PCH_TESTLOW_C35 R1390 10K 1 2 C34 R1391 10K 5% 1/20W MF 201 B38 TESTLOW PCH_TESTLOW_C34 1 2 NC_PCIE_CLK100M_FWN CLKOUT_PCIE_N3 5% 1/20W MF 201 64 NC_PCIE_CLK100M_FWP C37 TESTLOW AK8 PCH_TESTLOW_AK8 R1392 10K 1 2 CLKOUT_PCIE_P3 5% 1/20W MF 201 64 TESTLOW AL8 PCH_TESTLOW_AL8 R1393 10K 1 2 N1 5% 1/20W MF 201 12 FW_CLKREQ_L PCIECLKRQ3*/GPIO21 69 25 PCIE_CLK100M_TBT_N A39 CLKOUT_PCIE_N4 CLKOUT_LPC_0 AN15 LPC_CLK24M_SMC_R 17 69 OUT OUT 69 25 PCIE_CLK100M_TBT_P B39 CLKOUT_PCIE_P4 OUT CLKOUT_LPC_1 AP15 LPC_CLK24M_LPCPLUS_R OUT 17 69 U5 (IPD-PWROK) 27 12 IN TBT_CLKREQ_L PCIECLKRQ4*/GPIO22 67 64 30 PCIE_CLK100M_SSD_N B37 CLKOUT_PCIE_N5 CLKOUT_ITPXDP_N B35 TP_ITPXDP_CLK100MN OUT 67 64 30 PCIE_CLK100M_SSD_P A37 CLKOUT_PCIE_P5 CLKOUT_ITPXDP_P A35 TP_ITPXDP_CLK100MP OUT 30 12 SSD_CLKREQ_L T2 PCIECLKRQ5*/GPIO23 IN A SYNC_MASTER=J41_MLB SYNC_DATE=02/06/2013 A PAGE TITLE PP3V3_S0 64 65 74 8 11 13 15 17 18 27 30 36 38 39 PCH Audio/JTAG/SATA/CLK 40 41 42 43 44 45 56 59 61 62 DRAWING NUMBER SIZE R1375 100K 1 2 PCH_SATALED_L 12 Apple Inc. <SCH_NUM> D 5% 1/20W MF 201 REVISION R1340 100K 1 2 5% 1/20W MF 201 ENETSD_CLKREQ_L 12 R <E4LABEL> R1341 100K 1 2 5% 1/20W MF 201 CAMERA_CLKREQ_L 12 31 NOTICE OF PROPRIETARY PROPERTY: BRANCH R1342 100K 1 2 5% 1/20W MF 201 AP_CLKREQ_L 12 29 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. <BRANCH> R1343 100K 1 2 5% 1/20W MF 201 FW_CLKREQ_L 12 THE POSESSOR AGREES TO THE FOLLOWING: PAGE R1344 100K 1 2 TBT_CLKREQ_L 12 27 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 13 OF 121 5% 1/20W MF 201 R1345 100K 1 2 5% 1/20W MF 201 SSD_CLKREQ_L 12 30 II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 12 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 CRITICAL PPVRTC_G3H 8 12 17 62 64 OMIT_TABLE U0500 1 R1450 HASWELL-ULT 2C+GT2 330K 5% D R1400 kept for debug purposes. BGA-TSP SYM 8 OF 19 1/20W MF 2 201 D SYSTEM POWER MANAGEMENT 39 PCH_SUSACK_L AK2 SUSACK* (IPU) DSWVRMEN AW7 PCH_DSWVRMEN IN 64 37 17 PM_SYSRST_L AC3 SYS_RESET* DPWROK AV5 PM_DSW_PWRGD 37 IN IN NO STUFF 37 17 16 PM_PCH_SYS_PWROK AG2 SYS_PWROK (IPD-DeepSx) WAKE* AJ5 PCIE_WAKE_L 13 29 31 64 IN IN 1 SLP_S0# Isolation R14001 AY7 R1451 17 13 IN PM_PCH_PWROK PCH_PWROK CLKRUN*/GPIO32 V5 PM_CLKRUN_L BI 13 37 46 64 100K 0 5% 74 65 64 62 61 36 30 27 18 17 15 13 12 11 8 PP3V3_S0 5% AB5 1/20W 59 56 45 44 43 42 41 40 39 38 1/20W 17 13 IN PM_PCH_PWROK APWROK SUS_STAT*/GPIO61 AG4 LPC_PWRDWN_L OUT 37 46 64 MF MF 2 201 0201 2 AG7 18 16 15 OUT PLT_RESET_L PLTRST* SUSCLK/GPIO62 AE6 PM_CLK32K_SUSCLK_R OUT 38 69 1 C1420 PM_RSMRST_L AW6 RSMRST* SLP_S5*/GPIO63 AP5 PM_SLP_S5_L 0.1UF 64 59 IN OUT 13 37 59 10% 10V 2 X5R-CERM 39 PCH_SUSWARN_L AV4 SUSWARN*/SUSPWRDNACK/GPIO30 SLP_S4* AJ6 PM_SLP_S4_L 13 18 29 36 37 59 OUT OUT 0201 37 16 13 PM_PWRBTN_L AL7 PWRBTN* (IPU) SLP_S3* AT4 PM_SLP_S3_L 13 17 18 37 59 IN OUT CRITICAL 74LVC1G08 6 38 37 SMC_ADAPTER_EN AJ8 ACPRESENT/GPIO31 SLP_A* AL5 TP_PM_SLP_A_L IN SOT891 2 (IPD-DeepSx) 37 13 PM_BATLOW_L AN4 BATLOW*/GPIO72 SLP_SUS* AP4 PM_SLP_SUS_L 13 42 59 PM_SLP_S0_L IN OUT 37 18 13 OUT 4 U1420 AF3 08 1 PCH_PM_SLP_S0_L SLP_S0* SLP_LAN* AJ7 TP_PCH_SLP_LAN_L NC 3 5 TP_PCH_SLP_WLAN_L AM5 SLP_WLAN*/GPIO29 NC SLP_S0# can be driven high outside of S0 CRITICAL U1420 ensures signal will only be high in S0. OMIT_TABLE U0500 C HASWELL-ULT 2C+GT2 C BGA-TSP SYM 9 OF 19 EDP_BKLT_PWM B8 B9 DP_TBTSNK0_DDC_CLK SIDEBAND 56 OUT EDP_BKLCTL DDPB_CTRLCLK OUT 18 28 DDPB_CTRLDATA C9 DP_TBTSNK0_DDC_DATA eDP 18 28 56 13 EDP_BKLT_EN A9 EDP_BKLEN (IPD-PLTRST#) BI OUT DDPC_CTRLCLK D9 DP_TBTSNK1_DDC_CLK 18 60 13 EDP_PANEL_PWR C6 EDP_VDDEN OUT OUT DDPC_CTRLDATA D11 DP_TBTSNK1_DDC_DATA 18 BI (IPD-PLTRST#) DISPLAY 27 25 13 TBT_EN_CIO_PWR_L U6 PIRQA*/GPIO77 IN 37 13 SMC_RUNTIME_SCI_L P4 PIRQB*/GPIO78 IN N4 DDPB_AUXN C5 DP_TBTSNK0_AUXCH_C_N BI 25 67 64 13 AUD_IP_PERIPHERAL_DET PIRQC*/GPIO79 IN N2 DDPC_AUXN B6 DP_TBTSNK1_AUXCH_C_N BI 18 25 67 64 13 IN AUD_I2C_INT_L PIRQD*/GPIO80 DDPB_AUXP B5 DP_TBTSNK0_AUXCH_C_P BI 25 67 AD4 DDPC_AUXP A6 PCI 64 NC_PCI_PME_L PME* (IPU) DP_TBTSNK1_AUXCH_C_P BI 18 25 67 64 13 ODD_PWR_EN_L U7 GPIO55 OUT 28 13 DP_AUXCH_ISOL_L L1 GPIO52 DDPB_HPD C8 DP_TBTSNK0_HPD 25 OUT IN 64 13 ENET_LOW_PWR L3 GPIO54 OUT R5 DDPC_HPD A8 DP_TBTSNK1_HPD IN 18 25 65 61 59 13 OUT AUD_PWR_EN GPIO51 64 13 AUD_IPHS_SWITCH_EN L4 GPIO53 EDP_HPD D6 DP_INT_HPD 60 OUT IN B B PP3V3_S5 8 11 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74 PP3V3_S0 62 64 65 74 8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59 61 R1405 1K 1 2 PM_PWRBTN_L 13 16 37 5% 1/20W MF 201 R1410 10K 1 2 PM_BATLOW_L 13 37 5% 1/20W MF 201 R1452 10K 1 2 PCIE_WAKE_L 13 29 31 64 5% 1/20W MF 201 R1455 10K 1 2 PM_CLKRUN_L 13 37 46 64 5% 1/20W MF 201 R1460 100K 1 2 5% 1/20W MF 201 PM_SLP_S5_L 13 37 59 R1461 100K 1 2 5% 1/20W MF 201 PM_SLP_S4_L 13 18 29 36 37 59 R1462 100K 1 2 PM_SLP_S3_L 13 17 18 37 59 R1463 100K 1 2 5% 5% 1/20W 1/20W MF MF 201 201 PM_SLP_S0_L 13 18 37 R1464 100K 1 2 5% 1/20W MF 201 PM_SLP_SUS_L 13 42 59 R1430 100K 1 2 EDP_BKLT_EN 13 56 R1431 100K 1 2 5% 1/20W MF 201 EDP_PANEL_PWR A R1440 100K 1 2 5% 1/20W MF 201 TBT_EN_CIO_PWR_L 13 60 13 25 27 SYNC_MASTER=J41_MLB SYNC_DATE=02/06/2013 A PAGE TITLE R1441 10K 2 5% 1/20W MF 201 SMC_RUNTIME_SCI_L R1442 100K 1 1 2 5% 1/20W MF 201 AUD_IP_PERIPHERAL_DET 13 37 13 64 PCH PM/PCI/GFX R1443 100K 1 2 5% 1/20W MF 201 AUD_I2C_INT_L DRAWING NUMBER SIZE 5% 1/20W MF 201 13 64 Apple Inc. <SCH_NUM> D R1445 100K 1 2 ODD_PWR_EN_L 13 64 REVISION R1446 100K 1 2 5% 1/20W MF 201 DP_AUXCH_ISOL_L 13 28 R <E4LABEL> R1447 100K 1 2 5% 1/20W MF 201 ENET_LOW_PWR 13 64 NOTICE OF PROPRIETARY PROPERTY: BRANCH R1448 100K 1 2 5% 1/20W MF 201 AUD_PWR_EN 13 59 61 65 THE INFORMATION CONTAINED HEREIN IS THE <BRANCH> R1449 100K 1 2 5% 1/20W MF 201 AUD_IPHS_SWITCH_EN 13 64 PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE 5% 1/20W MF 201 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 14 OF 121 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 13 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 CRITICAL PCIe Port Assignments: OMIT_TABLE USB Port Assignments: 69 25 IN PCIE_TBT_D2R_N<0> F10 PERN5_L0 U0500 USB2N0 AN8 USB_EXTA_N BI 35 68 E10 HASWELL-ULT Ext A (LS/FS/HS) 69 25 IN PCIE_TBT_D2R_P<0> PERP5_L0 2C+GT2 USB2P0 AM8 USB_EXTA_P BI 35 68 Thunderbolt lane 0 BGA-TSP 69 25 PCIE_TBT_R2D_C_N<0> C23 PETN5_L0 SYM 11 OF 19 OUT C22 USB2N1 AR7 USB_EXTB_N BI 61 65 68 69 25 OUT PCIE_TBT_R2D_C_P<0> PETP5_L0 Ext B (LS/FS/HS) USB2P1 AT7 USB_EXTB_P BI 61 65 68 69 25 PCIE_TBT_D2R_N<1> F8 PERN5_L1 IN E8 USB2N2 AR8 USB_BT_N BI 29 68 69 25 PCIE_TBT_D2R_P<1> PERP5_L1 USB2P2 AP8 IN USB_BT_P 29 68 BT D Thunderbolt lane 1 69 25 OUT PCIE_TBT_R2D_C_N<1> B23 A23 PETN5_L1 BI D 69 25 OUT PCIE_TBT_R2D_C_P<1> PETP5_L1 USB2N3 AR10 NC_USB_IRN BI 64 IR USB2P3 AT10 NC_USB_IRP BI 64 69 25 PCIE_TBT_D2R_N<2> H10 PERN5_L2 IN 69 25 PCIE_TBT_D2R_P<2> G10 PERP5_L2 USB2N4 AM15 USB_TPAD_N 36 64 68 Trackpad IN BI Thunderbolt lane 2 B21 USB2P4 AL15 USB_TPAD_P BI 36 64 68 69 25 OUT PCIE_TBT_R2D_C_N<2> PETN5_L2 69 25 PCIE_TBT_R2D_C_P<2> C21 PETP5_L2 OUT USB2N5 AM13 TP_USB_5N Unused E6 USB2P5 AN13 TP_USB_5P 69 25 IN PCIE_TBT_D2R_N<3> PERN5_L3 69 25 PCIE_TBT_D2R_P<3> F6 PERP5_L3 USB2N6 AP11 IN NC_USB_CAMERAN 64 Thunderbolt lane 3 B22 Reserved: Camera 69 25 OUT PCIE_TBT_R2D_C_N<3> PETN5_L3 USB2P6 AN11 NC_USB_CAMERAP 64 69 25 PCIE_TBT_R2D_C_P<3> A21 PETP5_L3 OUT USB2N7 AR13 NC_USB_SDN 64 G11 Reserved: SD (HS) 69 64 29 IN PCIE_AP_D2R_N PERN3 USB2P7 AP13 NC_USB_SDP 64 F11 (IPD) PCIE_AP_D2R_P PCI-E 69 64 29 IN PERP3 USB AirPort PCIE_AP_R2D_C_N C29 USB3 Port Assignments: 69 29 OUT PETN3 69 29 PCIE_AP_R2D_C_P B30 PETP3 USB3RN0 G20 USB3_EXTA_D2R_N 35 68 OUT IN USB3RP0 H20 USB3_EXTA_D2R_P IN 35 68 64 NC_PCIE_FW_D2RN F13 PERN4 Ext A (SS) G13 USB3TN0 C33 USB3_EXTA_R2D_C_N OUT 35 68 64 NC_PCIE_FW_D2RP PERP4 USB3TP0 B34 USB3_EXTA_R2D_C_P OUT 35 68 Reserved: FireWire NC_PCIE_FW_R2D_CN B29 64 PETN4 64 NC_PCIE_FW_R2D_CP A29 PETP4 USB3RN1 E18 USB3_EXTB_D2R_N 61 65 68 IN USB3RP1 F18 USB3_EXTB_D2R_P IN 61 65 68 68 65 34 USB3_SD_D2R_N G17 PERN1/USB3RN2 Ext B (SS) USB3TN1 B33 IN USB3_EXTB_R2D_C_N F17 OUT 61 65 68 USB3_SD_D2R_P C SD Card Reader (& Ethernet if combo) 68 65 34 68 65 34 IN USB3_SD_R2D_C_N C30 PERP1/USB3RP2 PETN1/USB3TN2 USB3TP1 A33 USB3_EXTB_R2D_C_P OUT 61 65 68 C OUT 68 65 34 USB3_SD_R2D_C_P C31 PETP1/USB3TP2 OUT F15 USBRBIAS* AJ10 68 PCH_USB_RBIAS 69 32 IN PCIE_CAMERA_D2R_N PERN2/USB3RN3 G15 USBRBIAS AJ11 PLACE_NEAR=U0500.AJ10:2.54mm 69 32 IN PCIE_CAMERA_D2R_P PERP2/USB3RP3 1 Camera B31 R1570 69 32 OUT PCIE_CAMERA_R2D_C_N PETN2/USB3TN3 RSVD AN10 NC 22.6 A31 1% 69 32 OUT PCIE_CAMERA_R2D_C_P PETP2/USB3TP3 RSVD AM10 NC 1/20W MF 2 201 E15 RSVD OC0*/GPIO40 AL3 XDP_USB_EXTA_OC_L NC IN 14 16 35 E13 RSVD OC1*/GPIO41 AT1 XDP_USB_EXTB_OC_L NC IN 14 16 61 65 11 8 PP1V05_S0SW_PCH_VCCUSB3PLL PCH_PCIE_RCOMP A27 PCIE_RCOMP OC2*/GPIO42 AH2 XDP_USB_EXTC_OC_L 14 16 IN B27 PCIE_IREF OC3*/GPIO43 AV3 XDP_USB_EXTD_OC_L 14 16 IN 1 R1500 3.01K 1% 1/20W MF 201 CRITICAL PLACE_NEAR=U0500.A27:2.54mm 2 OMIT_TABLE U0500 HASWELL-ULT 2C+GT2 BGA-TSP SYM 7 OF 19 (IPU) 69 64 46 37 BI LPC_AD<0> R1540 33 1 2 LPC_AD_R<0> AU14 LAD0 SMBALERT*/GPIO11 AN2 PCH_SMBALERT_L 14 69 64 46 37 BI LPC_AD<1> R1541 33 1 2 5% 1/20W MF 201 LPC_AD_R<1> AW12 LAD1 2 5% 1/20W MF 201 SMBCLK AP2 SMBUS_PCH_CLK LPC_AD<2> R1542 33 1 LPC_AD_R<2> AY12 LAD2 OUT 16 19 25 40 56 69 LPC 69 64 46 37 SMBDATA AH1 B 69 64 46 37 BI BI LPC_AD<3> R1543 33 1 2 5% 5% 1/20W 1/20W MF MF 201 201 LPC_AD_R<3> AW11 LAD3 SMBUS_PCH_DATA BI 16 19 25 40 56 69 B 69 64 46 37 OUT LPC_FRAME_L R1544 33 1 2 LPC_FRAME_R_L AV12 LFRAME* SML0ALERT*/GPIO60 AL2 WOL_EN OUT 14 64 SMBUS 5% 1/20W MF 201 SML0CLK AN1 SML_PCH_0_CLK OUT 40 69 69 46 SPI_CLK_R AA3 SPI_CLK SML0DATA AK1 SML_PCH_0_DATA 40 69 OUT BI (IPU) SPI_CS0_R_L Y7 SML1ALERT# pull-up not provided on this 69 46 OUT SPI_CS0* (IPU) SML1ALERT*/PCHHOT*/GPIO73 AU4 PCH_SML1ALERT_L OUT 39 page, may be wire-ORed into other signals. TP_SPI_CS1_L Y4 SPI_CS1* Otherwise, 100k pull-up to 3.3V SUS required. (IPU) SML1CLK_GPIO75 AU3 SMBUS_SMC_1_S0_SCLOUT 32 37 40 43 44 64 69 73 TP_SPI_CS2_L AC2 SPI_CS2* SML1DATA/GPIO74 AH3 SMBUS_SMC_1_S0_SDA BI 32 37 40 43 44 64 69 73 SPI (IPU) 69 46 SPI_MOSI_R AA2 SPI_MOSI BI (IPU/IPD) 69 46 SPI_MISO AA4 SPI_MISO (IPU/IPD) CL_CLK AF2 NC_CLINK_CLK 64 BI (IPU) C-LINK 14 SPI_IO<2> Y6 SPI_IO2 (IPU/IPD) CL_DATA AD2 NC_CLINK_DATA 64 BI (IPU) 14 SPI_IO<3> AF1 SPI_IO3 CL_RST* AF4 NC_CLINK_RESET_L 64 BI (IPU) PP3V3_SUS 8 11 14 18 46 57 58 59 62 64 PP3V3_SUS A 8 11 14 18 46 57 58 59 62 64 SYNC_MASTER=J41_MLB SYNC_DATE=02/06/2013 A R1580 100K 1 2 XDP_USB_EXTA_OC_L 14 16 35 PAGE TITLE R1581 100K 1 2 5% 1/20W MF 201 XDP_USB_EXTB_OC_L 14 16 61 65 PCH PCIe/USB/LPC/SPI/SMBus R1582 100K 1 2 5% 1/20W MF 201 XDP_USB_EXTC_OC_L 14 16 DRAWING NUMBER SIZE 5% 1/20W MF 201 R1583 100K 1 2 5% 1/20W MF 201 XDP_USB_EXTD_OC_L 14 16 Apple Inc. <SCH_NUM> D REVISION R1548 1K 1 2 SPI_IO<2> 14 R <E4LABEL> R1549 1K 1 2 5% 1/20W MF 201 SPI_IO<3> 14 5% 1/20W MF 201 NOTICE OF PROPRIETARY PROPERTY: BRANCH R1590 100K 1 2 PCH_SMBALERT_L 14 THE INFORMATION CONTAINED HEREIN IS THE <BRANCH> R1591 100K 1 2 5% 1/20W MF 201 WOL_EN 14 64 PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE 5% 1/20W MF 201 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 15 OF 121 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 14 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 TABLE_BOMGROUP_HEAD BOM GROUP BOM OPTIONS PP1V05_S0 55 51 42 38 27 17 16 11 8 6 TABLE_BOMGROUP_ITEM 64 62 59 58 RAMCFG_SLOT RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H R16501 PP3V3_S0 62 64 65 74 8 11 12 13 15 17 18 27 30 36 38 1K 39 40 41 42 43 44 45 56 59 61 5% CRITICAL 1/20W MF RAMCFG3:H RAMCFG2:H RAMCFG1:H RAMCFG0:H OMIT_TABLE 201 2 R16311 1 R1636 R16351 1 R1611 U0500 THRMTRIP* D60 PM_THRMTRIP_L OUT 38 67 100K 100K 100K 100K HASWELL-ULT Pull-up/down on chipset support page (depends on TBT controller) 5% 5% 5% 5% 2C+GT2 1/20W 1/20W 1/20W 1/20W BGA-TSP RCIN*/GPIO82 V4 TBT_CIO_PLUG_EVENT IN 18 25 Cactus Ridge: Alias to TBT_CIO_PLUG_EVENT, requires pull-down. CPU/MISC MF MF MF MF 201 2 2 201 201 2 2 201 SYM 10 OF 19 Redwood Ridge: Alias to TBT_CIO_PLUG_EVENT_L, requires pull-up (S0). P1 SERIRQ T4 LPC_SERIRQ BI 15 37 46 64 16 15 XDP_PCH_GPIO76 BMBUSY*/GPIO76 D XDP_MLB_RAMCFG0 XDP_MLB_RAMCFG1 15 16 18 15 16 18 18 16 15 BI BI XDP_MLB_RAMCFG0 AU2 GPIO8 PCH_OPI_COMP AW15 PCH_OPI_COMP D PLACE_NEAR=U0500.AW15:2.54mm XDP_MLB_RAMCFG2 15 16 18 AM7 RSVD AF20 NC 1 25 18 BI TBT_GO2SX_BIDIR LAN_PHY_PWR_CTRL/GPIO12 R1655 XDP_MLB_RAMCFG3 15 16 18 RSVD AB21 NC AD6 49.9 18 OUT TP_MEM_VDD_SEL_1V5_L GPIO15 (IPD-RSMRST#) 1% GPIO12: 1/20W Y1 MF 64 46 16 15 BI XDP_LPCPLUS_GPIO GPIO16 GSPI0_CS*/GPIO83 R6 PCH_GSPI0_CS_L 15 2 201 CR: TBT_GO2SX_BIDIR, requires 100k pull-up to SUS RR/FR: DPHDMIMUX_SEL_TBT, requires 100k pull-up to TBTLC 16 15 XDP_PCH_GPIO17 T3 GPIO17 GSPI0_CLK/GPIO84 L6 PCH_GSPI0_CLK 15 IN 34 15 SD_RESET_L AD5 GPIO24 GSPI0_MISO/GPIO85 N6 PCH_GSPI0_MISO 15 OUT (IPD) 18 16 15 13 PLT_RESET_L AN5 IN 37 15 IN SMC_WAKE_SCI_L GPIO27 (IPD-DeepSx) GSPI0_MOSI/GPIO86 L8 PCH_GSPI0_MOSI 15 (IPD-PLTRST#) TPAD_SPI_INT_L AD7 R16211 36 15 IN GPIO28 GSPI1_CS*/GPIO87 R7 TPAD_SPI_CS_L OUT 15 36 100K AN3 5% 36 15 TPAD_USB_IF_EN GPIO26 1/20W OUT GSPI1_CLK/GPIO88 L5 TPAD_SPI_CLK OUT 15 36 68 MF AG6 201 2 64 59 58 30 15 SSD_PWR_EN GPIO56 OUT GSPI1_MISO/GPIO89 N7 TPAD_SPI_MISO IN 15 36 68 AP1 (IPD) 27 18 PCH_TBT_PCIE_RESET_L GPIO57 OUT GSPI_MOSI/GPIO90 K2 TPAD_SPI_MOSI OUT 15 36 68 PLT_RESET_L IN 13 15 16 18 64 15 HDD_PWR_EN AL4 GPIO58 OUT AT5 UART0_RXD/GPIO91 J1 AP_S0IX_WAKE_L IN 15 29 1 R1671 33 16 15 BI XDP_SDCONN_STATE_CHANGE_L GPIO59 100K AK4 UART0_TXD/GPIO92 K3 HDMITBTMUX_FLAG_L IN 15 64 5% 34 15 OUT SD_PWR_EN GPIO44 1/20W MF AB6 UART0_RTS*/GPIO93 J2 JTAG_ISP_TDO IN 15 18 25 2 201 25 15 OUT TBT_PWR_EN GPIO47 U4 UART0_CTS*/GPIO94 G1 AP_RESET_L OUT 29 25 18 16 15 OUT XDP_JTAG_ISP_TCK GPIO48 Y3 UART1_RXD/GPIO0 K4 GPIO LPIO 25 18 16 15 OUT XDP_JTAG_ISP_TDI GPIO49 PCH_UART1_RXD 15 JTAG_TBT_TMS P3 UART1_TXD/GPIO1 G2 PCH_UART1_TXD C 25 18 15 58 15 OUT PCH_HSIO_PWR_EN Y2 GPIO50 HSIOPC/GPIO71 UART1_RST*/GPIO2 J3 PCH_UART1_RTS_L 15 15 C OUT 36 15 TPAD_SPI_IF_EN AT3 GPIO13 UART1_CTS*/GPIO3 J4 PCH_UART1_CTS_L 15 OUT 18 16 15 XDP_MLB_RAMCFG3 AH4 GPIO14 BI I2C0_SDA/GPIO4 F2 PCH_I2C0_SDA 15 64 46 15 SPIROM_USE_MLB AM4 GPIO25 BI I2C0_SCL/GPIO5 F3 PCH_I2C0_SCL 15 18 15 CAMERA_PWR_EN_PCH AG5 GPIO45 OUT AG3 I2C1_SDA/GPIO6 G4 PCH_I2C1_SDA 15 64 15 OUT FW_PWR_EN GPIO46 AM3 I2C1_SCL/GPIO7 F1 PCH_I2C1_SCL 15 18 16 15 BI XDP_MLB_RAMCFG1 GPIO9 1 XDP_MLB_RAMCFG2 AM2 SDIO_CLK/GPIO64 E3 TBT_POC_RESET_L Pull-up on TBT page R1639 18 16 15 BI GPIO10 OUT 27 100K P2 5% 64 30 15 OUT SSD_DEVSLP DEVSLP0*/GPIO33 SDIO_CMD/GPIO65 F4 BT_PWRRST_L OUT 15 64 1/20W MF C4 201 2 29 15 OUT AP_S0IX_WAKE_SEL SDIO_POWER_EN/GPIO70 SDIO_D0/GPIO66 D3 PCH_STRP_TOPBLK_SWP_L IN 39 Requires connection to SMC via 1K series R (IPD-PLTRST#) 30 SSD_RESET_L L2 DEVSLP1*/GPIO38 SDIO_D1/GPIO67 E4 ENET_MEDIA_SENSE 15 64 OUT IN 64 15 FW_PME_L N5 DEVSLP2*/GPIO39 SDIO_D2/GPIO68 C3 LCD_IRQ_L 15 64 74 65 64 62 61 PP3V3_S0 IN IN 36 30 27 18 17 15 13 12 11 8 59 56 45 44 43 42 41 40 39 38 NO STUFF R1641 1K 1 2 5% 1/20W MF 201 PCH_TCO_TIMER_DISABLE V2 SPKR/GPIO81 (IPD-PLTRST#) SDIO_D3/GPIO69 E2 LCD_PSR_EN OUT 15 64 PP3V3_S5 8 11 13 16 17 18 28 29 34 42 57 58 59 60 62 64 74 PP3V3_S3 15 18 19 33 36 40 41 58 62 64 PP3V3_S0SW_SD 34 37 39 65 PP3V3_S3 15 18 19 33 36 40 41 58 62 64 PP3V3_S3RS0_CAMERA 31 41 74 65 64 62 61 36 30 27 18 17 15 13 12 11 8 PP3V3_S0 PP3V3_S0 62 64 65 74 8 11 12 13 15 17 18 27 30 36 38 59 56 45 44 43 42 41 40 39 38 B PP3V3_TBTLC 39 40 41 42 43 44 45 56 59 61 17 25 26 27 62 64 15 PCH_GSPI0_CS_L R1660 100K 1 2 B TBTLC for CR, S0 for RR PCH_GSPI0_CLK R1661 100K 1 2 5% 1/20W MF 201 15 5% 1/20W MF 201 R1610 100K 1 2 5% 1/20W MF 201 XDP_PCH_GPIO76 15 16 15 PCH_GSPI0_MISO R1662 100K 1 2 5% 1/20W MF 201 R1614 100K 1 2 XDP_LPCPLUS_GPIO 15 16 46 64 15 PCH_GSPI0_MOSI R1663 100K 1 2 5% 1/20W MF 201 R1615 100K 1 2 5% 1/20W MF 201 XDP_PCH_GPIO17 15 16 36 15 TPAD_SPI_CS_L R1664 47K 1 2 5% 1/20W MF 201 2 5% 1/20W MF 201 SD_ON_MLB 68 36 15 TPAD_SPI_CLK R1665 47K 1 R1616 should also be stuffed if TPAD_SPI_MISO R1666 47K 1 2 5% 1/20W MF 201 R1616 100K 1 2 5% 1/20W MF 201 SD_RESET_L 15 34 platform does not use SD card 68 36 15 TPAD_SPI_MOSI R1667 47K 1 2 5% 1/20W MF 201 R1617 100K 1 2 5% 1/20W MF 201 SMC_WAKE_SCI_L 15 37 68 36 15 5% 1/20W MF 201 R1618 100K 1 2 5% 1/20W MF 201 TPAD_SPI_INT_L 15 36 29 15 AP_S0IX_WAKE_L R1668 100K 1 2 R1619 100K 1 2 TPAD_USB_IF_EN 15 36 64 15 HDMITBTMUX_FLAG_L R1669 100K 1 2 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 R1620 100K 1 2 5% 1/20W MF 201 SSD_PWR_EN 15 30 58 59 64 15 PCH_UART1_RXD R1672 100K 1 2 R1622 100K 1 2 HDD_PWR_EN 15 64 15 PCH_UART1_TXD R1673 100K 1 2 5% 1/20W MF 201 5% 1/20W MF 201 2 5% 1/20W MF 201 R1623 100K 1 2 XDP_SDCONN_STATE_CHANGE_L 15 16 33 15 PCH_UART1_RTS_L R1674 100K 1 5% 1/20W MF 201 5% 1/20W MF 201 R1624 100K 1 2 5% 1/20W MF 201 SD_PWR_EN 15 34 15 PCH_UART1_CTS_L R1675 100K 1 2 5% 1/20W MF 201 R1625 100K 1 2 5% 1/20W MF 201 TBT_PWR_EN 15 25 PCH_I2C0_SDA R1676 100K 1 2 R1626 100K 1 2 XDP_JTAG_ISP_TCK 15 16 18 25 15 PCH_I2C0_SCL R1677 100K 1 2 5% 1/20W MF 201 5% 1/20W MF 201 R1627 100K 1 2 5% 1/20W MF 201 XDP_JTAG_ISP_TDI 15 16 18 25 15 5% 1/20W MF 201 R1628 100K 1 2 5% 1/20W MF 201 JTAG_TBT_TMS 15 18 25 15 PCH_I2C1_SDA R1678 100K 1 2 R1629 100K 1 2 PCH_HSIO_PWR_EN 15 58 15 PCH_I2C1_SCL R1679 100K 1 2 5% 1/20W MF 201 5% 1/20W MF 201 5% 1/20W MF 201 R1630 100K 1 2 5% 1/20W MF 201 TPAD_SPI_IF_EN 15 36 R1632 100K NO 1 STUFF 2 SPIROM_USE_MLB 15 46 64 R1633 100K 1 2 5% 1/20W MF 201 CAMERA_PWR_EN_PCH 15 18 R1634 100K 1 2 5% 1/20W MF 201 FW_PWR_EN 15 64 A R1637 100K 1 2 5% 1/20W MF 201 SSD_DEVSLP 15 30 64 SYNC_MASTER=J41_MLB SYNC_DATE=04/02/2013 A R1638 100K 1 2 5% 1/20W MF 201 AP_S0IX_WAKE_SEL 15 29 PAGE TITLE R1640 100K 1 2 5% 1/20W MF 201 FW_PME_L 15 64 PCH GPIO/MISC/LPIO 5% 1/20W MF 201 DRAWING NUMBER SIZE R1652 10K 1 2 5% 1/20W MF 201 LPC_SERIRQ 15 37 46 64 Apple Inc. <SCH_NUM> D REVISION R1670 100K 1 2 5% 1/20W MF 201 JTAG_ISP_TDO 15 18 25 R <E4LABEL> R1691 100K 1 2 5% 1/20W MF 201 BT_PWRRST_L 15 64 NOTICE OF PROPRIETARY PROPERTY: BRANCH R1693 100K 1 2 ENET_MEDIA_SENSE 15 64 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. <BRANCH> R1694 100K 1 2 5% 1/20W MF 201 LCD_IRQ_L THE POSESSOR AGREES TO THE FOLLOWING: PAGE R1695 100K 1 2 5% 1/20W MF 201 LCD_PSR_EN 15 64 15 64 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 16 OF 121 5% 1/20W MF 201 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 15 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 Extra BPM Testpoints 51 42 38 27 17 16 15 11 8 6 64 62 59 58 55 PP1V05_S0 Merged (CPU/PCH) Micro2-XDP 51 42 38 27 17 16 15 11 8 6 64 62 59 58 55 PP1V05_S0 CRITICAL NOTE: This is not the standard XDP pinout. XDP 67 6 XDP_BPM_L<2> 1 TP XDP_CONN Use with 921-0133 Adapter Flex to 67 64 16 6 XDP_CPU_TDO R1810 51 1 2 IN TP1802 support chipset debug. PLACE_NEAR=U0500.F62:28mm 5% 1/20W MF 201 67 6 XDP_BPM_L<3> 1 TP TP-P6 J1800 XDP IN TP-P6 TP1803 DF40RC-60DP-0.4V M-ST-SM1 67 64 16 6 XDP_CPU_TCK R1813 51 2 1 XDP_BPM_L<4> 1 TP 1 67 6 IN TP1804 R1830 62 61 PLACE_NEAR=U0500.E60:28mm 5% 1/20W MF 201 TP-P6 150 XDP_BPM_L<5> 1 TP 5% TDI and TMS are terminated in CPU. 67 6 IN TP-P6 TP1805 1/16W MF-LF XDP_BPM_L<6> 1 TP 2 402 67 6 IN TP-P6 TP1806 2 1 XDP_BPM_L<7> 1 TP XDP_CPU_PREQ_L OBSFN_A0 4 3 OBSFN_C0 CPU_CFG<17> 67 6 IN TP1807 67 64 6 BI IN 6 D D TP-P6 67 64 6 IN XDP_CPU_PRDY_L OBSFN_A1 6 8 5 7 OBSFN_C1 CPU_CFG<16> IN 6 67 6 CPU_CFG<0> OBSDATA_A0 10 9 OBSDATA_C0 CPU_CFG<8> 6 67 IN IN 67 6 CPU_CFG<1> OBSDATA_A1 12 11 OBSDATA_C1 CPU_CFG<9> 6 67 IN IN 14 13 67 6 CPU_CFG<2> OBSDATA_A2 16 15 OBSDATA_C2 CPU_CFG<10> 6 67 IN IN 67 64 6 CPU_CFG<3> OBSDATA_A3 18 17 OBSDATA_C3 CPU_CFG<11> 6 67 IN IN 20 19 67 6 XDP_BPM_L<0> OBSFN_B0 22 21 OBSFN_D0 CPU_CFG<19> 6 IN IN 67 6 XDP_BPM_L<1> OBSFN_B1 24 23 OBSFN_D1 CPU_CFG<18> 6 IN IN 26 25 67 6 CPU_CFG<4> OBSDATA_B0 28 27 OBSDATA_D0 CPU_CFG<12> 6 67 IN IN 67 6 CPU_CFG<5> OBSDATA_B1 30 29 OBSDATA_D1 CPU_CFG<13> 6 67 IN IN 32 31 67 6 CPU_CFG<6> OBSDATA_B2 34 33 OBSDATA_D2 CPU_CFG<14> 6 67 IN IN XDP CPU_CFG<7> 36 35 CPU_CFG<15> CPU_VCCST_PWRGD R1800 1K 1 2 67 6 IN OBSDATA_B3 OBSDATA_D3 IN 6 67 17 8 IN PLACE_NEAR=U0500.C61:2.54mm 5% 1/20W MF 201 38 37 XDP 64 XDP_CPU_VCCST_PWRGD PWRGD/HOOK0 40 39 ITPCLK/HOOK4 NC 37 13 OUT PM_PWRBTN_L R1802 0 1 2 5% 1/20W MF 0201 XDP_CPU_PWRBTN_L HOOK1 42 41 ITPCLK#/HOOK5 NC PLACE_NEAR=U5000.J3:2.54mm 44 43 VCC_OBS_AB VCC_OBS_CD XDP XDP 8 OUT CPU_PWR_DEBUG HOOK2 46 45 RESET#/HOOK6 67 XDP_CPURST_L R1805 1K 1 2 PLT_RESET_L 5% 1/20W MF 201 IN 13 15 18 37 17 13 OUT PM_PCH_SYS_PWROK R1804 0 1 2 5% 1/16W MF-LF 402 64 XDP_SYS_PWROK HOOK3 48 47 DBR#/HOOK7 XDP_DBRESET_L OUT 17 67 PLACE_NEAR=U0500.AG7:2.54mm 50 49 NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page 69 56 40 25 19 14 SMBUS_PCH_DATA SDA 52 51 TDO XDP_PCH_TDO 12 16 64 69 BI IN 69 56 40 25 19 14 SMBUS_PCH_CLK SCL 54 53 TRSTn XDP_TRST_L IN 69 64 16 12 XDP_PCH_TCK TCK1 56 55 TDI XDP_PCH_TDI 12 16 64 69 OUT OUT XDP_CPU_TCK TCK0 58 57 TMS XDP_PCH_TMS C 67 64 16 6 OUT XDP 60 59 XDP_PRESENT# CRITICAL OUT 12 16 64 69 C 16 12 OUT PCH_JTAGX R1835 0 1 2 5% 1/20W MF 0201 XDP XDP XDP XDP XDP XDP PLACE_NEAR=J1800.58:28mm C1804 1 R1831 C1800 1 1 64 63 1 C1801 1 C1806 Q1840 0.1UF 1K 0.1UF 0.1UF 0.1UF 5 10% 5% 10% 10% 10% DMN5L06VK-7 G 6.3V 6.3V 2 6.3V 2 6.3V CERM-X5R 2 0201 1/16W MF-LF 2 402 CERM-X5R 2 0201 518S0847 CERM-X5R 0201 CERM-X5R 0201 SOT-563 D S XDP_CPU_TDO IN 6 16 64 67 PLACE_NEAR=J1800.51:28mm 3 4 XDP_CPU_PRESENT_L CRITICAL XDP Q1840 2 DMN5L06VK-7 G SOT-563 D S XDP_CPUPCH_TRST_L 6 12 16 64 67 PLACE_NEAR=J1800.53:28mm MAKE_BASE=TRUE 6 1 XDP_CPUPCH_TRST_L OUT 6 12 16 64 67 CRITICAL XDP_CPUPCH_TRST_L OUT 6 12 16 64 67 XDP PCH XDP Signals Q1842 5 DMN5L06VK-7 G SOT-563 These signals do not connect to XDP connector in this architecture, only accessible via Top-Side Probe. Nets are listed here to show XDP associations and to make clear CPU JTAG Isolation D S XDP_CPU_TDI OUT 6 64 67 what restrictions exist on PCH GPIOs when Top-Side Probe is used for PCH debug. PLACE_NEAR=J1800.55:28mm 3 4 PP5V_S0 CRITICAL PCH/XDP Signals Non-XDP Signals 61 59 58 56 52 51 46 45 32 17 64 62 42 34 29 28 18 17 15 13 11 8 PP3V3_S5 XDP 74 64 62 60 59 58 57 18 15 XDP_MLB_RAMCFG0 1 TP TP1870 Q1842 B BI B 2 TP-P6 DMN5L06VK-7 G 35 16 14 OUT XDP_USB_EXTA_OC_L XDP_USB_EXTA_OC_L IN 14 16 35 1 SOT-563 MAKE_BASE=TRUE C1845 1 R1845 6 65 61 16 14 XDP_USB_EXTB_OC_L XDP_USB_EXTB_OC_L 14 16 61 65 0.1UF VCC 330K D S OUT IN XDP_CPU_TMS MAKE_BASE=TRUE 10% 5% OUT 6 64 67 U1845 1/20W PLACE_NEAR=J1800.57:28mm 6 1 XDP_USB_EXTC_OC_L 1 TP 16V 14 OUT TP1873 X5R-CERM 2 74LVC1G07GF MF TP-P6 0201 SOT891 2 201 XDP_USB_EXTD_OC_L 1 TP PP1V05_SUS 14 IN TP-P6 TP1874 59 37 17 IN ALL_SYS_PWRGD 2 A Y 4 XDP_JTAG_CPU_ISOL_L 62 57 33 16 15 OUT XDP_SDCONN_STATE_CHANGE_L XDP_SDCONN_STATE_CHANGE_L IN 15 16 33 MAKE_BASE=TRUE NC 1 NC NC 5 NC NO STUFF 18 15 BI XDP_MLB_RAMCFG1 1 TP TP1876 GND 16 12 PCH_JTAGX R1899 PLACE_NEAR=U0500.AE63:28mm 1K 2 1 5% 1/20W MF 201 TP-P6 3 18 15 XDP_MLB_RAMCFG2 1 TP XDP BI TP-P6 TP1877 69 64 16 12 XDP_PCH_TDO R1890 51 2 1 18 15 XDP_MLB_RAMCFG3 1 TP PLACE_NEAR=U0500.AE61:28mm 5% 1/20W MF 201 BI TP-P6 TP1878 XDP 25 18 16 15 XDP_JTAG_ISP_TCK XDP_JTAG_ISP_TCK 15 16 18 25 69 64 16 12 XDP_PCH_TDI R1891 51 2 PLACE_NEAR=U0500.AD61:28mm 1 5% 1/20W MF 201 IN OUT MAKE_BASE=TRUE XDP_SSD_PCIE3_SEL_L R1881 1K 1 2 XDP 12 OUT 5% 1/20W MF 201 69 64 16 12 XDP_PCH_TMS R1892 51 2 1 PLACE_NEAR=U0500.AD62:28mm 5% 1/20W MF 201 12 OUT XDP_SSD_PCIE2_SEL_L R1882 1K 1 2 5% 1/20W MF 201 NOTE: Must not short XDP pins together! NO STUFF 12 OUT XDP_SSD_PCIE1_SEL_L R1883 1K 1 2 5% 1/20W MF 201 69 64 16 12 XDP_PCH_TCK R1896 51 2 PLACE_NEAR=U0500.AE62:28mm 1 5% 1/20W MF 201 12 OUT XDP_SSD_PCIE0_SEL_L R1884 1K 1 2 5% 1/20W MF 201 SSD_PCIE_SEL_L IN 30 64 NO STUFF 64 46 16 15 XDP_LPCPLUS_GPIO XDP_LPCPLUS_GPIO 15 16 46 64 67 64 16 12 6 R1897 51 XDP_CPUPCH_TRST_L PLACE_NEAR=U0500.AU62:28mm 2 1 5% 1/20W MF 201 BI BI MAKE_BASE=TRUE XDP_PCH_GPIO17 1 TP 15 OUT TP-P6 TP1886 XDP_PCH_GPIO76 1 TP 15 BI TP-P6 TP1887 A 25 18 16 15 IN XDP_JTAG_ISP_TDI MAKE_BASE=TRUE XDP_JTAG_ISP_TDI OUT 15 16 18 25 SYNC_MASTER=J41_MLB SYNC_DATE=02/06/2013 A PAGE TITLE Unused & MLB_RAMCFGx GPIOs have TPs. CPU/PCH Merged XDP USB Overcurrents are aliased, do not cause USB OC# events during PCH debug. DRAWING NUMBER SIZE SDCONN_STATE_CHANGE_L is aliased, do not plug/unplug SD Cards during PCH debug. Apple Inc. <SCH_NUM> D REVISION R JTAG_ISP (non-TMS) nets are aliased, do not attempt bit-banged JTAG during PCH debug. <E4LABEL> NOTICE OF PROPRIETARY PROPERTY: BRANCH NOTE: Should force PCH GPIO47 high to ensure TBT router powered to avoid leakage/clamping of signals. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. <BRANCH> SSD_PCIEx_SEL_L straps are connected via 1K to common net. THE POSESSOR AGREES TO THE FOLLOWING: PAGE LPCPLUS_GPIO is aliased, do not attempt use during PCH debug. I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 18 OF 121 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 16 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 System RTC Power Source & 32kHz / 25MHz Clock Generator Chipset uses 24MHz crystal, GreenCLK kept to save 1x 25MHz crystal & 1x 32kHz crystal PCH Reset Button Memory VTT Enable Level-Shifter 50 49 46 40 38 37 36 35 30 17 65 64 62 61 59 PP3V42_G3H CPU output is on VDDQ rail (1.2V), TPS51916 has 1.8V Vih(min). Coin-Cell: VBAT (300-ohm & 10uF RC) 74 65 64 62 61 36 30 27 18 17 15 13 12 11 8 PP3V3_S0 This looks a little ugly to support 59 56 45 44 43 42 41 40 39 38 PP1V2_S3 No Coin-Cell: 3.42V G3Hot (no RC) 70 62 53 42 23 22 21 20 19 new and old parts. With GreenCLK Rev C 1 PP3V3_S0 62 64 65 74 pin 5 must receive S5 power (Stuff R2042) PP3V3_S5 64 62 60 59 15 13 11 8 R1995 8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59 61 58 57 42 34 29 28 18 17 16 10K Coin-Cell & G3Hot: 3.42V G3Hot 74 5% 1 XDP 1/20W R1970 C1970 1 6 Coin-Cell & No G3Hot: 3.3V S5 MF R1996 2 201 0.1UF VCC 330K TPS51916 I(leak) = +/- 1uA, No Coin-Cell: 3.3V S5 5% D GreenCLK 25MHz Power 18 PP3V3_S5RS3RS0_SYSCLKGEN No bypass necessary 67 16 IN XDP_DBRESET_L 1 0 2 PM_SYSRST_L BI 13 37 64 10% 16V X5R-CERM 2 0201 U1970 74AUP1G07GF 1/20W MF 2 201 Vih(min) = 1.8V 33uW when driven-low D 1/20W NO STUFF SOT891 Must be powered if any VDDIO is powered. 0201 1 CPU_MEMVTT_PWR_EN_LSVDDQ MEMVTT_PWR_EN MF 5% R1997 6 IN 2 A Y 4 MAKE_BASE=TRUE 17 53 0 VG3HOT 13 CAM XTAL Power PP1V2_CAM_XTALPCIEVDD 1 NC NC 5 MEMVTT_PWR_EN NC 2 VDD 5 31 5% NC NC OUT 17 53 1/16W TBT XTAL Power 64 62 27 26 25 15 PP3V3_TBTLC VBAT and +V3.3A are MF-LF GND internally ORed to 2 402 3 SILK_PART=SYS RESET create VDD_RTC_OUT. C1924 1 C1922 1 1 C1902 +V3.3A should be first 0.1UF 0.1UF 1UF U1900 10% 10% 20% available ~3.3V power 16V 16V 2 6.3V SLG3NB148CV X5R-CERM 2 X5R-CERM 2 X5R to reduce VBAT draw. 0201 0201 0201 TQFN CRITICAL PP5V_S0 61 59 58 56 52 51 46 45 32 16 11 VIOE_25M_A 32.768K 12 PCH_CLK32K_RTCX1 12 64 62 OUT CKPLUS_WAIVE=PwrTerm2Gnd 6 VIOE_25M_B 1 R1920 C1905 12PF R1905 0 14 VIOE_25M_C 25M_A 9 25M_B 8 NC SYSCLK_CLK25M_CAMERA OUT 32 69 PCH ME Disable Strap 100K 5% 1/20W 2 1 69 SYSCLK_CLK25M_X2 1 2 SYSCLK_CLK25M_X2_R 69 3 X2 25M_C 15 SYSCLK_CLK25M_TBT 25 69 MF OUT 5% 5% NO STUFF 4 X1 PPVRTC_G3H 8 12 13 62 64 Q1920 2 201 25V 1/20W 1 DMN5L06VK-7 VOUT 1 SPI_DESCRIPTOR_OVERRIDE_LS5V G 5 CRITICAL MF R1906 For SB RTC Power 1 NP0-C0G-CERM 0201 SOT-563 0201 NC Y1905 1M 2 4 5% GND THRM NC 25.000MHZ-12PF-20PPM 1/20W PAD 1 C1910 58 11 8 PP1V5_S0SW_AUDIO_HDA C1906 MF 10 16 17 3 1UF D S SPI_DESCRIPTOR_OVERRIDE 7 SM-3.2X2.5MM 2 201 20% 12PF 3 4 1 2 2 6.3V X5R SYSCLK_CLK25M_X1 69 0201 1 NOTE: 30 PPM or better required for RTC accuracy D 6 R1921 5% 25V Q1920 5% 1K NP0-C0G-CERM DMN5L06VK-7 1/20W 0201 SOT-563 MF C 17 12 NC_RTC_CLK32K_RTCX2 NC_RTC_CLK32K_RTCX2 IN 12 17 2 201 HDA_SDOUT_R C PCH 24MHz Crystal MAKE_BASE=TRUE NO_TEST=TRUE 2 G S 1 IPD = 9-50k OUT 12 69 C1915 R1915 6.8PF 37 IN SPI_DESCRIPTOR_OVERRIDE_L 1 2 0 PCH_CLK24M_XTALOUT_R 1 2 PCH_CLK24M_XTALOUT IN 12 PCH uses HDA_SDO as a power-up strap. If low, ME functions normally. +/-0.1PF CRITICAL 5% 1/20W If high, ME is disabled. This allows for full re-flashing of SPI ROM. 25V Y1915 MF 1 R1916 1 C0G SMC controls strap enable to allow in-field control of strap setting. 0201 NC NC 24.000MHZ-20PPM-6PF 0201 1M 2 NC NC 3.20X2.50MM-SM1 5% Q1920 & 5V pull-up allows circuit to work regardless of HDA voltage. 1/20W 4 C1916 MF 3 6.8PF 2 201 1 2 PCH_CLK24M_XTALIN 12 OUT +/-0.1PF 25V C0G VCCST (1.05V S0) PWRGD 0201 PCH 24MHz Outputs 34 29 28 18 17 16 15 13 11 8 74 64 62 60 59 58 57 42 PP3V3_S5 PP1V05_S0 6 8 11 15 16 27 38 42 51 55 58 59 62 64 R1927 LPC_CLK24M_SMC 17 37 69 1 22 MAKE_BASE=TRUE C1930 1 CRITICAL R1931 69 12 IN LPC_CLK24M_SMC_R 1 2 LPC_CLK24M_SMC OUT 17 37 69 0.1UF 10K PLACE_NEAR=U0500.AN15:5.1mm 5% 10% U1930 5% 1/20W 1/20W 16V 74AUP1G09 X5R-CERM 2 MF 6 MF SOT891 201 R1926 0201 VCC 2 201 22 69 12 IN LPC_CLK24M_LPCPLUS_R 1 2 LPC_CLK24M_LPCPLUS OUT 46 64 69 59 37 17 16 ALL_SYS_PWRGD 2 A Y 4 CPU_VCCST_PWRGD OUT 8 16 PLACE_NEAR=U0500.AP15:5.1mm 5% 1/20W 59 37 18 13 IN PM_SLP_S3_L 1 B MF 201 5 NC NC B GND B 3 50 49 46 40 38 37 36 35 30 17 PP3V42_G3H PCH PWROK Generation PM_PCH_PWROK OUT 13 17 65 64 62 61 59 PM_PCH_PWROK OUT 13 17 MAKE_BASE=TRUE BYPASS=U1950:5MM 74 65 64 62 61 PP3V3_S0 36 30 27 18 17 15 13 12 11 8 59 56 45 44 43 42 41 40 39 38 1 C1950 0.1UF 1 10% 51 8 IN CPU_VR_EN R1950 16V 2 X5R-CERM NO STUFF WF: Do we need this? 10K 0201 1 5% 1/20W R19632 2 R1960 R1955 MF 0 0 201 2 5% 5% 10K 1/20W 1/20W CKPLUS_WAIVE=UNCONNECTED_PINS 5% NO STUFF 8 74LVC2G08GT MF MF A 1/20W MF 201 2 R1951 59 37 17 16 IN ALL_SYS_PWRGD 1 A SOT833 PM_S0_PGOOD 0201 1 1 0201 8 74LVC2G08GT SOT833 R1962 SYNC_MASTER=J41_MLB SYNC_DATE=02/06/2013 A 0 U1950Y 7 5 A 1K PAGE TITLE CPU_VR_READY CPUVR_PGOOD_R 2 U1950Y 3 SYS_PWROK_R PM_PCH_SYS_PWROK 51 17 8 OUT MAKE_BASE=TRUE 1 5% 2 B 08 NO STUFF R19611 6 08 1 5% 2 OUT 13 16 37 Chipset Support 51 17 8 IN CPU_VR_READY 1/20W 4 B 1/20W DRAWING NUMBER SIZE MF 100K MF 0201 5% 1/20W 4 201 Apple Inc. <SCH_NUM> D MF CKPLUS_WAIVE=UNCONNECTED_PINS REVISION 201 2 R <E4LABEL> NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. <BRANCH> THE POSESSOR AGREES TO THE FOLLOWING: PAGE 38 37 27 IN SMC_DELAYED_PWRGD I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 19 OF 121 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 17 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 GreenCLK 25MHz Power DDC Pull-Ups Platform Reset Connections 2.2k pull-ups are required by PCH NO STUFF to indicate active display interface. Unbuffered R2040 R2081 0 DP++ spec violation, should remove! 64 62 58 41 40 36 33 19 15 PP3V3_S3 1 2 PP3V3_S5RS3RS0_SYSCLKGEN 17 18 33 16 15 13 IN PLT_RESET_L 1 2 LPCPLUS_RESET_L OUT 46 64 69 5% 74 65 64 62 61 36 30 27 18 17 15 13 12 11 8 PP3V3_S0 1/20W PP3V3_S5RS3RS0_SYSCLKGEN 17 18 59 56 45 44 43 42 41 40 39 38 5% MF MIN_LINE_WIDTH=0.5 MM 1/20W 0201 MIN_NECK_WIDTH=0.2 MM MF R2071 VOLTAGE=3.3V NO STUFF NO STUFF 201 NO STUFF MAKE_BASE=TRUE 1 0 2 PCA9557D_RESET_L OUT 19 R2041 R20201 1 R2021 R20221 1 R2023 2.2K 2.2K 2.2K 2.2K 5% 0 R2041/2 should be stuffed for 5% 5% 5% 5% 1/20W 74 65 64 62 61 36 30 27 18 17 15 13 12 11 8 PP3V3_S0 1 2 1/20W 1/20W 1/20W 1/20W D MF 0201 59 56 45 44 43 42 41 40 39 38 5% 1/20W GreekCLK A or B depending on S2 rail MF 201 2 MF 2 201 MF 201 2 MF 2 201 D MF 74 65 64 62 61 0201 R2042 should be stuffed for GreenCLK C 28 18 13 DP_TBTSNK0_DDC_CLK 42 15 36 41 13 30 40 12 27 39 11 18 38 8 17 PP3V3_S0 Scrub for Layout Optimization 28 18 13 DP_TBTSNK0_DDC_DATA 59 56 45 44 43 R2042 DP_TBTSNK1_DDC_CLK CRITICAL Buffered 34 29 28 18 17 16 15 13 11 8 PP3V3_S5 1 0 2 18 13 18 13 DP_TBTSNK1_DDC_DATA 5 MC74VHC1G08 1 SC70-HF R2072 74 64 62 60 59 58 57 42 5% TBTSNK1_DDC is pulled-up just to indicate that 4 0 1/20W U2071 PLT_RST_BUF_L 1 2 SMC_LRESET_L OUT 37 MF DP port is used. No DDC on this port, AUX-only. 2 0201 5% 1 1/20W NOTE: Only DDC_DATA is sensed by PCH, so 3 R2070 MF 0201 R2088 DDC_CLK pull-ups are unstuffed. 1 C2071 100K 5% 1 0 2 BKLT_PLT_RST_L 0.1UF 1/20W OUT 56 10% 16V 2 X5R-CERM 0201 MF 2 201 R2089 5% 1/20W MF Thunderbolt Pull-up/downs 0201 0 Cactus Ridge GO2SX signal pulled-up to SUS rail 1 2 CAM_PCIE_RESET_L OUT 31 5% 64 62 59 58 57 46 14 11 8 PP3V3_SUS 1/20W MF 0201 R20131 27 18 15 IN PCH_TBT_PCIE_RESET_L PCH_TBT_PCIE_RESET_L OUT 15 18 27 10K MAKE_BASE=TRUE 5% 1/20W MF 201 2 MAKE_BASE 25 18 15 BI TBT_GO2SX_BIDIR TRUE TBT_GO2SX_BIDIR BI 15 18 25 Cactus Ridge PLUG_EVENT is active-high, always driven (pull-down) 25 18 15 OUT TBT_CIO_PLUG_EVENT TRUE TBT_CIO_PLUG_EVENT IN 15 18 25 34 29 28 18 17 16 15 13 11 8 PP3V3_S5 C 74 64 62 60 59 58 57 42 NOSTUFF BYPASS=U2030:3mm Required for unused second TBT port C 25 TBT_B_CIO_SEL C2030 1 IN DP_TBTPB_HPD R20151 0.1UF 25 OUT 100K 10% TBT_B_CONFIG2_RC 5% 10V 25 OUT 1/20W X5R-CERM 2 25 TBT_B_CONFIG1_BUF MF 0201 NOSTUFF OUT 201 2 25 TBT_B_LSRX CRITICAL 6 74LVC1G08 59 37 36 29 18 13 IN PM_SLP_S4_L 2 SOT891 R20161 1 R2017 R20181 1 R2019 1 R2014 4 CAMERA_PWR_EN 10K 10K 10K 10K 10K U2030 OUT 31 5% 1/20W 5% 1/20W 5% 1/20W 5% 1/20W 5% 1/20W 15 IN CAMERA_PWR_EN_PCH 1 08 MF MF MF MF MF NC 201 2 2 201 201 2 2 201 2 201 5 3 NC Power State Debug LEDs DBGLED (For development only) TBT Aliases 60 29 13 59 28 11 58 18 8 PP3V3_S5 R2094 R2030 MAKE_BASE 17 57 16 42 15 34 2 0 1 PP3V3_S5_DBGLED 1 0 2 DP_TBTSNK0_DDC_CLK DP_TBTSNK0_DDC_CLK 74 64 62 28 18 13 IN TRUE OUT 13 18 28 MIN_LINE_WIDTH=0.5 MM PLACE_SIDE=BOTTOM 5% MIN_NECK_WIDTH=0.25 MM 5% 28 18 13 BI DP_TBTSNK0_DDC_DATA TRUE DP_TBTSNK0_DDC_DATA BI 13 18 28 1/16W VOLTAGE=3.3V 1/20W MF-LF MF MAKE_BASE 402 0201 25 18 13 OUT DP_TBTSNK1_HPD TRUE DP_TBTSNK1_HPD IN 13 18 25 DBGLED DBGLED DBGLED DBGLED DBGLED =DP_TBTSNK1_ML_C_P<3..0> DP_TBTSNK1_ML_C_P<3..0> OUT IN TRUE 5 25 67 R20901 R20911 R20921 R20931 R20951 IN =DP_TBTSNK1_ML_C_N<3..0> TRUE DP_TBTSNK1_ML_C_N<3..0> OUT 5 25 67 20K 20K 20K 20K 20K 5% 5% 5% 5% 5% 67 25 18 13 BI DP_TBTSNK1_AUXCH_C_P TRUE DP_TBTSNK1_AUXCH_C_P BI 13 18 25 67 1/20W 1/20W 1/20W 1/20W 1/20W MF MF MF MF MF 67 25 18 13 BI DP_TBTSNK1_AUXCH_C_N TRUE DP_TBTSNK1_AUXCH_C_N BI 13 18 25 201 2 201 2 201 2 201 2 201 2 67 B DBGLED_S5 DBGLED_S4 DBGLED_S3 DBGLED_S0I3 DBGLED_S0 18 13 18 13 IN BI DP_TBTSNK1_DDC_CLK DP_TBTSNK1_DDC_DATA TRUE TRUE DP_TBTSNK1_DDC_CLK DP_TBTSNK1_DDC_DATA 13 18 13 18 B Single-port TBT implementation does not require DDC Crossbar A DBGLED A DBGLED A DBGLED A DBGLED A DBGLED MAKE_BASE MAKE_BASE D2090 D2091 D2092 D2093 D2095 JTAG_ISP_TDO TRUE JTAG_ISP_TDO GREEN-56MCD-2MA-2.65V GREEN-56MCD-2MA-2.65V GREEN-56MCD-2MA-2.65V GREEN-56MCD-2MA-2.65V GREEN-56MCD-2MA-2.65V 25 18 15 OUT IN 15 18 25 LTQH9G-SM LTQH9G-SM LTQH9G-SM LTQH9G-SM LTQH9G-SM 25 18 16 15 XDP_JTAG_ISP_TCK XDP_JTAG_ISP_TCK 15 16 18 IN OUT K PLACE_SIDE=BOTTOM K PLACE_SIDE=BOTTOM K PLACE_SIDE=BOTTOM K PLACE_SIDE=BOTTOM K PLACE_SIDE=BOTTOM 25 SILK_PART=S5_ON SILK_PART=STBY_ON SILK_PART=S3_ON SILK_PART=S0I3_ON SILK_PART=S0_ON 25 18 16 15 IN XDP_JTAG_ISP_TDI XDP_JTAG_ISP_TDI OUT 15 16 18 25 DBGLED_S4_D DBGLED_S3_D DBGLED_S0I3_D DBGLED_S0_D 25 18 15 IN JTAG_TBT_TMS TRUE JTAG_TBT_TMS OUT 15 18 25 DBGLED DBGLED DBGLED DBGLED No MAKE_BASE on TCK/TDI as these are provided on XDP page. Q2090 D 6 Q2090 D 3 Q2091 D 6 Q2091 D 3 DMN5L06VK-7 DMN5L06VK-7 DMN5L06VK-7 DMN5L06VK-7 SOT-563 SOT-563 SOT-563 SOT-563 RAM Configuration Straps 2 G S 1 5 G S 4 2 G S 1 5 G S 4 Pull-downs for chip-down RAM systems 16 15 OUT XDP_MLB_RAMCFG0 16 15 OUT XDP_MLB_RAMCFG1 59 58 28 IN S4_PWR_EN 16 15 OUT XDP_MLB_RAMCFG2 59 37 36 29 18 13 IN PM_SLP_S4_L 16 15 OUT XDP_MLB_RAMCFG3 59 37 17 13 IN PM_SLP_S3_L PM_SLP_S0_L RAMCFG3:L RAMCFG2:L RAMCFG1:L RAMCFG0:L 37 13 IN R20501 R20511 R20521 R20531 10K 10K 10K 10K 5% 5% 5% 5% 1/20W 1/20W 1/20W 1/20W MF MF MF MF 201 2 201 2 201 2 201 2 A SYNC_MASTER=J41_MLB SYNC_DATE=02/15/2013 A PAGE TITLE LPDDR3 Alias Support Project Chipset Support DRAWING NUMBER SIZE TP_CPU_MEM_RESET_L TP_CPU_MEM_RESET_L 18 6 IN MAKE_BASE=TRUE 6 18 Apple Inc. <SCH_NUM> D 18 15 IN TP_MEM_VDD_SEL_1V5_L TP_MEM_VDD_SEL_1V5_L 15 18 REVISION MAKE_BASE=TRUE R 70 21 20 19 18 PP0V6_S3_MEM_VREFDQ_A PP0V6_S3_MEM_VREFDQ_A 18 19 20 21 70 <E4LABEL> MAKE_BASE=TRUE VOLTAGE=0.6V NOTICE OF PROPRIETARY PROPERTY: BRANCH 70 21 20 19 18 PP0V6_S3_MEM_VREFCA_A PP0V6_S3_MEM_VREFCA_A MAKE_BASE=TRUE VOLTAGE=0.6V 18 19 20 21 70 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. <BRANCH> THE POSESSOR AGREES TO THE FOLLOWING: PAGE PP0V6_S3_MEM_VREFDQ_B PP0V6_S3_MEM_VREFDQ_B 70 23 22 19 18 MAKE_BASE=TRUE VOLTAGE=0.6V 18 19 22 23 70 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 20 OF 121 70 23 22 19 18 PP0V6_S3_MEM_VREFCA_B PP0V6_S3_MEM_VREFCA_B 18 19 22 23 70 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET MAKE_BASE=TRUE VOLTAGE=0.6V IV ALL RIGHTS RESERVED 18 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 Page Notes CPU-Based Margining CPU_MEM_VREFDQ_A_ISOL VRef Dividers PP1V2_S3 17 20 21 22 23 42 53 62 70 Power aliases required by this page: FETs for CPU isolation during DAC margining DDRVREF_DAC EN RC’s to avoid drain glitches CRITICAL Always used, regardless - =PP3V3_S3_VREFMRGN 1 R2225 May not be necessary due to C22x0 DDRVREF_DAC of margining option. R2221 - =PPDDR_S3_MEMVREF CRITICAL Q2220 100K 2 VREFMRGN_DQ_A_EN_RC Q2225 8.2K 2 1 1% DMN5L06VK-7 2 Signal aliases required by this page: 1/20W G DMN5L06VK-7 DDRVREF_DAC 5% DDRVREF_DAC SOT-563 MF G - =I2C_VREFDACS_SCL SOT-563 R2201 1 1/20W MF C2225 1 R2223 2 201 PLACE_NEAR=Q2220.6:3mm - =I2C_VREFDACS_SDA 201 0.1UF 10 S D 100K 1 2 PP0V6_S3_MEM_VREFDQ_A 18 20 21 70 S D - =I2C_PCA9557D_SCL CPU_DIMMA_VREFDQ 5% 10% MIN_LINE_WIDTH=0.3 mm 6 7 1 IN 6.3V 1% 1/20W CERM-X5R 2 PLACE_NEAR=R2221.2:1mm MIN_NECK_WIDTH=0.2 mm 6 1 - =I2C_PCA9557D_SDA MF 0201 1/20W 1 201 2 Q2225 pin 6: MF 201 R2222 BOM options provided by this page: PLACE_NEAR=Q2220.6:2.54mm 8.2K D - DDRVREF_DAC - Stuffs DAC margining circuit. PLACE_NEAR=Q2220.6:2mm 1 C2220 1% 1/20W MF D CRITICAL 0.022UF 201 2 Q2260 CPU_MEM_VREFDQ_B_ISOL 10% 2 6.3V 2 DMN5L06VK-7 DDRVREF_DAC CRITICAL X5R-CERM R2220 G SOT-563 0201 DDRVREF_DAC 24.9 2 1 R2245 MEM_VREFDQ_A_RC 1 R2241 100K 2 Q2265 8.2K S D CPU_DIMMB_VREFDQ VREFMRGN_DQ_B_EN_RC 2 1 1% 1% 7 IN DMN5L06VK-7 1/20W 1/20W 6 G 1 DDRVREF_DAC 5% DDRVREF_DAC SOT-563 MF MF R2202 1 1/20W MF C2245 1 R2243 201 2 201 PLACE_NEAR=Q2260.6:3mm NOTE: CPU DAC output step sizes: 201 0.1UF 10 S D 100K 10% 1 2 PP0V6_S3_MEM_VREFDQ_B 18 22 23 70 DDR3 (1.5V) 7.70mV per step 5% MIN_LINE_WIDTH=0.3 mm 6 1 6.3V 1% 1/20W CERM-X5R 2 PLACE_NEAR=R2241.2:1mm MIN_NECK_WIDTH=0.2 mm DDR3L (1.35V) 6.99mV per step CRITICAL MF 0201 1/20W LPDDR3 (1.2V) ?.??mV per step Q2220 201 2 Q2265 pin 6: MF 201 R22421 5 DMN5L06VK-7 PLACE_NEAR=Q2260.6:2.54mm 8.2K PLACE_NEAR=Q2260.6:2mm 1% G SOT-563 1/20W 1 C2240 MF 201 2 0.022UF S D 7 IN CPU_DIMM_VREFCA CPU_MEM_VREFCA_A_ISOL 10% 2 6.3V 3 4 X5R-CERM DDRVREF_DAC CRITICAL 0201 R2240 NOTE: CPU has single output for 1 R2265 DDRVREF_DAC 24.9 2 R2261 VREFCA. Split into two MEM_VREFDQ_B_RC 1 100K 2 VREFMRGN_CA_A_EN_RC Q2225 8.2K 5 signals for independent DAC 1 DMN5L06VK-7 1% 1/20W 1% 1/20W G margining support. When CRITICAL DDRVREF_DAC 5% DDRVREF_DAC SOT-563 MF MF DAC margining VREFCA ensure Q2260 R2215 1 1/20W MF C2265 1 R2263 201 2 201 PLACE_NEAR=Q2220.3:3mm 10 5 201 DMN5L06VK-7 0.1UF S D VREFMRGN_CPU_EN is low 100K 1 2 PP0V6_S3_MEM_VREFCA_A G 18 20 21 70 SOT-563 5% 10% MIN_LINE_WIDTH=0.3 mm 3 4 6.3V to remove short due to CPU. 1/20W CERM-X5R 2 1% 1/20W PLACE_NEAR=R2261.2:1mm MIN_NECK_WIDTH=0.2 mm MF 0201 1 201 2 MF R2262 S D 201 8.2K 3 4 C DAC-Based Margining PLACE_NEAR=Q2220.3:2mm 1 C2260 0.022UF 1% 1/20W MF 201 2 C DAC sets voltage level, PCA9557 & FETs enable outputs CPU_MEM_VREFCA_B_ISOL 10% 2 6.3V X5R-CERM and disables margining after platform reset. DDRVREF_DAC CRITICAL 0201 R2260 OMIT DDRVREF_DAC 24.9 2 1 R2285 MEM_VREFCA_A_RC 1 R2281 PP3V3_S3 R2218 100K 2 VREFMRGN_CA_B_EN_RC Q2265 8.2K 5 1 1% 1% 36 33 19 18 15 64 62 58 41 40 SHORT2 DMN5L06VK-7 1/20W 1/20W G 1 PP3V3_S3_VREFMRGN_DAC DDRVREF_DAC 5% DDRVREF_DAC SOT-563 MF MF NONE MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm R2207 1 1/20W MF C2285 1 R2283 201 2 201 PLACE_NEAR=Q2260.3:3mm NONE VOLTAGE=3.3V 201 0.1UF 10 S D NONE DDRVREF_DAC DDRVREF_DAC 100K 10% 1 2 PP0V6_S3_MEM_VREFCA_B 18 22 23 70 402 5% MIN_LINE_WIDTH=0.3 mm 3 C2200 1 C2201 4 1 6.3V 1% 1/20W CERM-X5R 2 PLACE_NEAR=R2281.2:1mm MIN_NECK_WIDTH=0.2 mm MF 1/20W 2.2UF 0.1UF 0201 20% 6.3V 10% 6.3V 201 2 MF 201 R22821 CERM 2 2 CERM-X5R CRITICAL 8.2K 402-LF 0201 PLACE_NEAR=Q2260.3:2mm 1% 8 DDRVREF_DAC (All 4 R’s) 1 C2280 1/20W MF VDD DDRVREF_DAC 0.022UF 201 2 40 25 19 16 14 69 56 IN SMBUS_PCH_CLK 6 SCL U2200 VOUTA 1 VREFMRGN_DQ_A R2226 4.02K 1 2 VREFMRGN_DQ_A_RDIV 1% 1/20W MF 201 R22x6 pin 2: 10% 2 6.3V MSOP X5R-CERM PLACE_NEAR=Q2225.1:2.54mm R2280 DAC5574 40 25 19 16 14 69 56 BI SMBUS_PCH_DATA 7 SDA VOUTB 2 VREFMRGN_DQ_B R2246 4.02K 1 2 VREFMRGN_DQ_B_RDIV 1% 1/20W MF 201 PLACE_NEAR=Q2265.1:2.54mm 0201 24.9 2 MEM_VREFCA_B_RC 1 9 A0 VOUTC 4 VREFMRGN_CA_AB R2266 4.02K 1 2 VREFMRGN_CA_A_RDIV 1% 1/20W MF 201 PLACE_NEAR=Q2225.4:2.54mm 1% Addr=0x98(WR)/0x99(RD) 10 A1 VREFMRGN_MEMVREG R2286 4.02K VREFMRGN_CA_B_RDIV PLACE_NEAR=Q2265.4:2.54mm 1/20W VOUTD 5 1 2 MF 1% 1/20W MF 201 201 GND 3 NOTE: MEMVREG and SPARE share a DAC output, cannot enable both at the same time! PP3V3_S3 15 18 19 33 36 40 41 58 62 64 CRITICAL DDRVREF_DAC B DDRVREF_DAC CRITICAL C2205 0.1UF 1 DDRVREF_DAC B DDRVREF_DAC R22001 16 C2202 1 100K 10% 6.3V B1 U2204 DDRVREF_DAC 0.1UF VCC CERM-X5R 2 C2 10% 5% 1/20W 0201 V+ MAX4253 UCSP R2214 6.3V CERM-X5R 2 U2201 MF 201 2 C1 VREFMRGN_MEMVREG_BUF 1 38.3K2 DDRREG_FB 0201 PCA9557 OUT 53 QFN C4 1% PLACE_NEAR=R7415.2:1mm (OD) P0 6 VREFMRGN_CPU_EN C3 V- 1/20W MF 3 A0 P1 7 VREFMRGN_DQ_A_EN B4 201 Addr=0x30(WR)/0x31(RD) 4 A1 P2 9 VREFMRGN_DQ_B_EN 5 A2 P3 10 VREFMRGN_CA_A_EN P4 11 VREFMRGN_CA_B_EN P5 12 VREFMRGN_MEMVREG_EN CRITICAL 69 56 40 25 19 16 14 IN SMBUS_PCH_CLK 1 SCL P6 13 VREFMRGN_SPARE_EN DDRVREF_DAC DDRVREF_DAC 69 56 40 25 19 16 14 BI SMBUS_PCH_DATA 2 SDA P7 14 NC R2213 1 100K B1 U2204 THRM RESET* 15 5% A2 PAD GND 1/20W MAX4253 MF V+ UCSP 201 2 17 8 RST* on ’platform reset’ so that system A1 VREFMRGN_SPARE_BUF watchdog will disable margining. A3 A4 DDRVREF_DAC V- 1 NOTE: Margining will be disabled across all B4 R2217 1M soft-resets and sleep/wake cycles. Pins B1 & B4: 5% 1/20W PCA9557D_RESET_L CKPLUS_WAIVE=unconnected_pins MF 18 IN DDRVREF_DAC 2 201 R22121 100K 5% 1/20W MEM A VREF DQ MEM B VREF DQ MEM A VREF CA MEM B VREF CA MEM VREG A MF 201 2 SYNC_MASTER=J41_MLB SYNC_DATE=02/12/2013 A DAC Channel: A B C C D PAGE TITLE PCA9557D Pin: 1 2 3 4 5 DDR3 VREF MARGINING DRAWING NUMBER SIZE NOTE: LPDDR3 assumes TPS51916 supply with 28.7k/57.6k divider LPDDR3 (1.2V) DDR3L (1.35V) LPDDR3 (1.2V) DDR3L (1.35V) DDR3L assumes TPS51916 supply with 19.6k/57.6k divider Apple Inc. <SCH_NUM> D REVISION Nominal value 0.600V (DAC: 0x2E.5) 0.675V (DAC: 0x34) 1.200V (DAC: 0x5D) 1.343V (DAC: 0x68) R <E4LABEL> Margined target: 0.300V - 0.900V (+/- 300mV) 0.337V - 1.013V (+/- 337.5mV) 0.800V - 1.600V (+/- 400mV) 0.972V - 1.714V (+/- 371mV) NOTICE OF PROPRIETARY PROPERTY: BRANCH DAC range: 0.000V - 1.199V (0x00 - 0x5D) 0.000V - 1.354V (0x00 - 0x69) 0.000V - 2.397V (0x00 - 0xBA) 0.000V - 2.694V (0x00 - 0xD1) THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. <BRANCH> THE POSESSOR AGREES TO THE FOLLOWING: PAGE VRef current: +73uA - -73uA (- = sourced) +82uA - -82uA (- = sourced) +21uA - -21uA (- = sourced) +25uA - -25uA (- = sourced) I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 22 OF 121 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET DAC step size: 6.36mV / step @ output 6.36mV / step @ output 4.28mV / step @ output 3.53mV / step @ output IV ALL RIGHTS RESERVED 19 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 D LPDDR3 CHANNEL A (0-31) D U2300 U2300 LPDDR3-16GB LPDDR3-16GB FBGA FBGA MEM_A_CAA<0> R2 (1 OF 2) P9 =MEM_A_DQ<0> PP1V8_S3 A3 (2 OF 2) B2 EDFA232A1MA-GD-F 70 63 24 IN CA0 DQ0 BI 63 62 57 23 22 21 20 EDFA232A1MA-GD-F 70 63 24 MEM_A_CAA<1> P2 CA1 DQ1 N9 =MEM_A_DQ<1> 63 A4 B5 IN BI 70 63 24 MEM_A_CAA<2> N2 CA2 DQ2 N10 =MEM_A_DQ<2> 63 A5 C5 IN BI 70 63 24 MEM_A_CAA<3> N3 CA3 DQ3 N11 =MEM_A_DQ<3> 63 A6 E4 IN BI 70 63 24 MEM_A_CAA<4> M3 CA4 DQ4 M8 =MEM_A_DQ<4> 63 A10 E5 IN BI 70 63 24 MEM_A_CAA<5> F3 CA5 DQ5 M9 =MEM_A_DQ<5> 63 U3 VDD1 F5 IN BI 70 63 24 7 MEM_A_CAA<6> E3 CA6 DQ6 M10 =MEM_A_DQ<6> 63 U4 J12 IN BI 70 63 24 MEM_A_CAA<7> E2 CA7 DQ7 M11 =MEM_A_DQ<7> 63 U5 K2 IN BI 70 63 24 MEM_A_CAA<8> D2 CA8 DQ8 F11 =MEM_A_DQ<8> 63 U6 L6 IN BI 70 63 24 MEM_A_CAA<9> C2 CA9 DQ9 F10 =MEM_A_DQ<9> 63 U10 M5 IN BI DQ10 F9 =MEM_A_DQ<10> 63 VSS N4 MEM_A_CKE<0> K3 CKE0 BI PP1V2_S3 A8 70 24 7 IN OMIT_TABLE F8 =MEM_A_DQ<11> 70 62 53 42 23 22 21 20 19 17 OMIT_TABLE N5 K4 CKE1 DQ11 BI 63 A9 70 24 7 IN MEM_A_CKE<1> E11 R4 CRITICAL DQ12 =MEM_A_DQ<12> BI 63 D4 CRITICAL 70 24 7 MEM_A_CLK_P<0> J3 CK_T DQ13 E10 =MEM_A_DQ<13> 63 R5 IN BI D5 70 24 7 MEM_A_CLK_N<0> J2 CK_C DQ14 E9 =MEM_A_DQ<14> 63 T2 IN BI D6 D9 =MEM_A_DQ<15> T3 C 70 24 21 7 70 24 21 7 IN MEM_A_CS_L<0> MEM_A_CS_L<1> L3 CS0* L4 CS1* DQ15 DQ16 T8 =MEM_A_DQ<16> BI BI 63 63 G5 H5 T4 C IN T9 =MEM_A_DQ<17> T5 DQ17 BI 63 H6 L8 DM0 DQ18 T10 =MEM_A_DQ<18> 63 H2 BI H12 G8 DM1 DQ19 T11 =MEM_A_DQ<19> 63 BI J5 C3 P8 DM2 DQ20 R8 =MEM_A_DQ<20> 63 BI J6 VDD2 D3 D8 DM3 DQ21 R9 =MEM_A_DQ<21> 63 BI K5 F4 DQ22 R10 =MEM_A_DQ<22> 70 63 24 21 7 MEM_A_ODT<0> J8 ODT BI 63 K6 G3 IN R11 =MEM_A_DQ<23> DQ23 BI 63 K12 VSSCA G4 DQ24 C11 =MEM_A_DQ<24> 63 BI L5 P3 MEM_A_ZQ<0> B3 ZQ0 DQ25 C10 =MEM_A_DQ<25> 63 BI P4 M4 MEM_A_ZQ<1> B4 ZQ1 DQ26 C9 =MEM_A_DQ<26> 63 BI P5 J4 DQ27 C8 =MEM_A_DQ<27> 63 PP0V6_S3_MEM_VREFCA_A H4 VREFCA BI P6 R23001 R23011 70 21 19 18 J11 VREFDQ DQ28 B11 =MEM_A_DQ<28> BI 63 U8 B6 243 243 70 21 19 18 PP0V6_S3_MEM_VREFDQ_A B10 B12 1% 1% DQ29 =MEM_A_DQ<29> BI 63 U9 1/20W 1/20W A1 B9 C6 MF MF NC DQ30 =MEM_A_DQ<30> BI 63 201 2 201 2 C2340 1 1 C2341 NC A2 DQ31 B8 =MEM_A_DQ<31> BI 63 70 62 53 42 23 22 21 20 19 17 PP1V2_S3 F2 D12 0.047UF 0.047UF A12 G2 E6 10% 10% NC DQS0_C L11 =MEM_A_DQS_N<0> 63 6.3V 6.3V A13 BI H3 VDDCA F6 X5R 2 2 X5R NC G11 =MEM_A_DQS_N<1> 201 201 B1 DQS1_C BI 63 L2 F12 NC DQS2_C P11 =MEM_A_DQS_N<2> B13 BI 63 M2 G6 NC NU DQS3_C D11 =MEM_A_DQS_N<3> 63 T1 BI G9 NC 70 62 53 42 23 22 21 20 19 17 PP1V2_S3 A11 T13 DQS0_T L10 =MEM_A_DQS_P<0> H10 NC BI 63 C12 U1 DQS1_T G10 =MEM_A_DQS_P<1> VSSQ K10 NC BI 63 E8 U2 DQS2_T P10 =MEM_A_DQS_P<2> 63 L9 NC BI E12 U12 DQS3_T D10 =MEM_A_DQS_P<3> M6 NC BI 63 G12 U13 M12 NC H8 B NC C4 H9 N6 P12 B K9 NC H11 NC R6 R3 J9 NC T6 J10 VDDQ T12 K8 K11 70 62 53 42 23 22 21 20 19 17 PP1V2_S3 L12 N8 1 C2300 1 C2301 1 C2302 1 C2303 1 C2304 1 C2305 1 C2306 1 C2307 N12 0.1UF 0.1UF 1UF 1UF 1UF 1UF 10UF 10UF R12 10% 10% 10% 10% 10% 10% 20% 20% 16V 16V 10V 10V 10V 10V 25V 25V 2 X5R-CERM 2 X5R-CERM 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R-CERM 2 X5R-CERM U11 0201 0201 402 402 402 402 0603 0603 70 62 53 42 23 22 21 20 19 17 PP1V2_S3 1 C2320 1 C2321 1 C2322 1 C2323 1 C2324 1UF 1UF 1UF 10UF 10UF 10% 10% 10% 20% 20% 10V 10V 10V 25V 25V 2 X5R 2 X5R 2 X5R 2 X5R-CERM 2 X5R-CERM 402 402 402 0603 0603 70 62 53 42 23 22 21 20 19 17 PP1V2_S3 PLACEMENT_NOTE: 1 C2310 1 C2311 1 C2312 1UF 1UF 10UF A 10% 10V 2 X5R 10% 10V 2 X5R 20% 25V 2 X5R-CERM 10uF caps are shared between DRAM. Distribute evenly. SYNC_MASTER=J41_MLB SYNC_DATE=02/06/2013 A 402 402 0603 PAGE TITLE LPDDR3 DRAM Channel A (0-31) DRAWING NUMBER SIZE 62 57 23 22 21 20 PP1V8_S3 Apple Inc. <SCH_NUM> D REVISION R 1 C2330 1 C2331 1 C2332 1 C2333 <E4LABEL> 1UF 1UF 10UF 10UF NOTICE OF PROPRIETARY PROPERTY: BRANCH 10% 10% 20% 20% 10V 10V 25V 25V 2 X5R 2 X5R 2 X5R-CERM 2 X5R-CERM THE INFORMATION CONTAINED HEREIN IS THE <BRANCH> 402 402 0603 0603 PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 23 OF 121 II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 20 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 D LPDDR3 CHANNEL A (32-63) D U2400 U2400 LPDDR3-16GB LPDDR3-16GB FBGA FBGA MEM_A_CAB<0> R2 (1 OF 2) P9 =MEM_A_DQ<32> PP1V8_S3 A3 (2 OF 2) B2 EDFA232A1MA-GD-F 70 63 24 IN CA0 DQ0 BI 63 62 57 23 22 21 20 EDFA232A1MA-GD-F 70 63 24 MEM_A_CAB<1> P2 CA1 DQ1 N9 =MEM_A_DQ<33> 63 A4 B5 IN BI 70 63 24 MEM_A_CAB<2> N2 CA2 DQ2 N10 =MEM_A_DQ<34> 63 A5 C5 IN BI 70 63 24 MEM_A_CAB<3> N3 CA3 DQ3 N11 =MEM_A_DQ<35> 63 A6 E4 IN BI 70 63 24 MEM_A_CAB<4> M3 CA4 DQ4 M8 =MEM_A_DQ<36> 63 A10 E5 IN BI 70 63 24 MEM_A_CAB<5> F3 CA5 DQ5 M9 =MEM_A_DQ<37> 63 U3 VDD1 F5 IN BI 70 63 24 7 MEM_A_CAB<6> E3 CA6 DQ6 M10 =MEM_A_DQ<38> 63 U4 J12 IN BI 70 63 24 MEM_A_CAB<7> E2 CA7 DQ7 M11 =MEM_A_DQ<39> 63 U5 K2 IN BI 70 63 24 MEM_A_CAB<8> D2 CA8 DQ8 F11 =MEM_A_DQ<40> 63 U6 L6 IN BI 70 63 24 MEM_A_CAB<9> C2 CA9 DQ9 F10 =MEM_A_DQ<41> 63 U10 M5 IN BI DQ10 F9 =MEM_A_DQ<42> 63 VSS N4 MEM_A_CKE<2> K3 CKE0 BI PP1V2_S3 A8 70 24 7 IN OMIT_TABLE F8 =MEM_A_DQ<43> 70 62 53 42 23 22 21 20 19 17 OMIT_TABLE N5 K4 CKE1 DQ11 BI 63 A9 70 24 7 IN MEM_A_CKE<3> E11 R4 CRITICAL DQ12 MEM_A_DQ<32> BI 7 63 70 D4 CRITICAL 70 24 7 MEM_A_CLK_P<1> J3 CK_T DQ13 E10 =MEM_A_DQ<45> 63 R5 IN BI D5 70 24 7 MEM_A_CLK_N<1> J2 CK_C DQ14 E9 =MEM_A_DQ<46> 63 T2 IN BI D6 D9 =MEM_A_DQ<47> T3 C 70 24 20 7 70 24 20 7 IN MEM_A_CS_L<0> MEM_A_CS_L<1> L3 CS0* L4 CS1* DQ15 DQ16 T8 =MEM_A_DQ<48> BI BI 63 63 G5 H5 T4 C IN T9 =MEM_A_DQ<49> T5 DQ17 BI 63 H6 L8 DM0 DQ18 T10 =MEM_A_DQ<50> 63 H2 BI H12 G8 DM1 DQ19 T11 =MEM_A_DQ<51> 63 BI J5 C3 P8 DM2 DQ20 R8 =MEM_A_DQ<52> 63 BI J6 VDD2 D3 D8 DM3 DQ21 R9 =MEM_A_DQ<53> 63 BI K5 F4 DQ22 R10 =MEM_A_DQ<54> 70 63 24 20 7 MEM_A_ODT<0> J8 ODT BI 63 K6 G3 IN R11 =MEM_A_DQ<55> DQ23 BI 63 K12 VSSCA G4 DQ24 C11 =MEM_A_DQ<56> 63 BI L5 P3 MEM_A_ZQ<2> B3 ZQ0 DQ25 C10 =MEM_A_DQ<57> 63 BI P4 M4 MEM_A_ZQ<3> B4 ZQ1 DQ26 C9 =MEM_A_DQ<58> 63 BI P5 J4 DQ27 C8 =MEM_A_DQ<59> 63 PP0V6_S3_MEM_VREFCA_A H4 VREFCA BI P6 R24001 R24011 70 20 19 18 J11 VREFDQ DQ28 B11 =MEM_A_DQ<60> BI 63 U8 B6 243 243 70 20 19 18 PP0V6_S3_MEM_VREFDQ_A B10 B12 1% 1% DQ29 =MEM_A_DQ<61> BI 63 U9 1/20W 1/20W A1 B9 C6 MF MF NC DQ30 =MEM_A_DQ<62> BI 63 201 2 201 2 C2440 1 1 C2441 NC A2 DQ31 B8 =MEM_A_DQ<63> BI 63 70 62 53 42 23 22 21 20 19 17 PP1V2_S3 F2 D12 0.047UF 0.047UF A12 G2 E6 10% 10% NC DQS0_C L11 =MEM_A_DQS_N<4> 63 6.3V 6.3V A13 BI H3 VDDCA F6 X5R 2 2 X5R NC G11 =MEM_A_DQS_N<5> 201 201 B1 DQS1_C BI 63 L2 F12 NC DQS2_C P11 MEM_A_DQS_N<6> B13 BI 7 63 70 M2 G6 NC NU DQS3_C D11 =MEM_A_DQS_N<7> 63 T1 BI G9 NC 70 62 53 42 23 22 21 20 19 17 PP1V2_S3 A11 T13 DQS0_T L10 =MEM_A_DQS_P<4> H10 NC BI 63 C12 U1 DQS1_T G10 =MEM_A_DQS_P<5> VSSQ K10 NC BI 63 E8 U2 DQS2_T P10 MEM_A_DQS_P<6> 7 63 70 L9 NC BI E12 U12 DQS3_T D10 =MEM_A_DQS_P<7> M6 NC BI 63 G12 U13 M12 NC H8 B NC C4 H9 N6 P12 B K9 NC H11 NC R6 R3 J9 NC T6 J10 VDDQ T12 K8 K11 70 62 53 42 23 22 21 20 19 17 PP1V2_S3 L12 N8 1 C2400 1 C2401 1 C2402 1 C2403 1 C2404 1 C2405 1 C2406 N12 0.1UF 0.1UF 1UF 1UF 1UF 1UF 10UF R12 10% 10% 10% 10% 10% 10% 20% 16V 16V 10V 10V 10V 10V 25V 2 X5R-CERM 2 X5R-CERM 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R-CERM U11 0201 0201 402 402 402 402 0603 70 62 53 42 23 22 21 20 19 17 PP1V2_S3 1 C2420 1 C2421 1 C2422 1 C2423 1UF 1UF 1UF 10UF 10% 10% 10% 20% 10V 10V 10V 25V 2 X5R 2 X5R 2 X5R 2 X5R-CERM 402 402 402 0603 70 62 53 42 23 22 21 20 19 17 PP1V2_S3 PLACEMENT_NOTE: 1 C2410 1 C2411 1 C2412 1UF 1UF 10UF A 10% 10V 2 X5R 10% 10V 2 X5R 20% 25V 2 X5R-CERM 10uF caps are shared between DRAM. Distribute evenly. SYNC_MASTER=J41_MLB SYNC_DATE=02/06/2013 A 402 402 0603 PAGE TITLE LPDDR3 DRAM Channel A (32-63) DRAWING NUMBER SIZE 62 57 23 22 21 20 PP1V8_S3 Apple Inc. <SCH_NUM> D REVISION R 1 C2430 1 C2431 1 C2432 <E4LABEL> 1UF 1UF 10UF NOTICE OF PROPRIETARY PROPERTY: BRANCH 10% 10% 20% 10V 10V 25V 2 X5R 2 X5R 2 X5R-CERM THE INFORMATION CONTAINED HEREIN IS THE <BRANCH> 402 402 0603 PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 24 OF 121 II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 21 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 D LPDDR3 CHANNEL B (0-31) D U2500 U2500 LPDDR3-16GB LPDDR3-16GB FBGA FBGA MEM_B_CAA<0> R2 (1 OF 2) P9 =MEM_B_DQ<0> PP1V8_S3 A3 (2 OF 2) B2 EDFA232A1MA-GD-F 70 63 24 IN CA0 DQ0 BI 63 62 57 23 22 21 20 EDFA232A1MA-GD-F 70 63 24 MEM_B_CAA<1> P2 CA1 DQ1 N9 =MEM_B_DQ<1> 63 A4 B5 IN BI 70 63 24 MEM_B_CAA<2> N2 CA2 DQ2 N10 =MEM_B_DQ<2> 63 A5 C5 IN BI 70 63 24 MEM_B_CAA<3> N3 CA3 DQ3 N11 =MEM_B_DQ<3> 63 A6 E4 IN BI 70 63 24 MEM_B_CAA<4> M3 CA4 DQ4 M8 =MEM_B_DQ<4> 63 A10 E5 IN BI 70 63 24 MEM_B_CAA<5> F3 CA5 DQ5 M9 =MEM_B_DQ<5> 63 U3 VDD1 F5 IN BI 70 63 24 7 MEM_B_CAA<6> E3 CA6 DQ6 M10 =MEM_B_DQ<6> 63 U4 J12 IN BI 70 63 24 MEM_B_CAA<7> E2 CA7 DQ7 M11 =MEM_B_DQ<7> 63 U5 K2 IN BI 70 63 24 MEM_B_CAA<8> D2 CA8 DQ8 F11 =MEM_B_DQ<8> 63 U6 L6 IN BI 70 63 24 MEM_B_CAA<9> C2 CA9 DQ9 F10 =MEM_B_DQ<9> 63 U10 M5 IN BI DQ10 F9 =MEM_B_DQ<10> 63 VSS N4 MEM_B_CKE<0> K3 CKE0 BI PP1V2_S3 A8 70 24 7 IN OMIT_TABLE F8 =MEM_B_DQ<11> 70 62 53 42 23 22 21 20 19 17 OMIT_TABLE N5 K4 CKE1 DQ11 BI 63 A9 70 24 7 IN MEM_B_CKE<1> E11 R4 CRITICAL DQ12 =MEM_B_DQ<12> BI 63 D4 CRITICAL 70 24 7 MEM_B_CLK_P<0> J3 CK_T DQ13 E10 =MEM_B_DQ<13> 63 R5 IN BI D5 70 24 7 MEM_B_CLK_N<0> J2 CK_C DQ14 E9 =MEM_B_DQ<14> 63 T2 IN BI D6 D9 =MEM_B_DQ<15> T3 C 70 24 23 7 70 24 23 7 IN MEM_B_CS_L<0> MEM_B_CS_L<1> L3 CS0* L4 CS1* DQ15 DQ16 T8 =MEM_B_DQ<16> BI BI 63 63 G5 H5 T4 C IN T9 =MEM_B_DQ<17> T5 DQ17 BI 63 H6 L8 DM0 DQ18 T10 =MEM_B_DQ<18> 63 H2 BI H12 G8 DM1 DQ19 T11 =MEM_B_DQ<19> 63 BI J5 C3 P8 DM2 DQ20 R8 =MEM_B_DQ<20> 63 BI J6 VDD2 D3 D8 DM3 DQ21 R9 =MEM_B_DQ<21> 63 BI K5 F4 DQ22 R10 =MEM_B_DQ<22> 70 63 24 23 7 MEM_B_ODT<0> J8 ODT BI 63 K6 G3 IN R11 =MEM_B_DQ<23> DQ23 BI 63 K12 VSSCA G4 DQ24 C11 =MEM_B_DQ<24> 63 BI L5 P3 MEM_B_ZQ<0> B3 ZQ0 DQ25 C10 =MEM_B_DQ<25> 63 BI P4 M4 MEM_B_ZQ<1> B4 ZQ1 DQ26 C9 =MEM_B_DQ<26> 63 BI P5 J4 DQ27 C8 =MEM_B_DQ<27> 63 PP0V6_S3_MEM_VREFCA_B H4 VREFCA BI P6 R25001 R25011 70 23 19 18 J11 VREFDQ DQ28 B11 =MEM_B_DQ<28> BI 63 U8 B6 243 243 70 23 19 18 PP0V6_S3_MEM_VREFDQ_B B10 B12 1% 1% DQ29 =MEM_B_DQ<29> BI 63 U9 1/20W 1/20W A1 B9 C6 MF MF NC DQ30 =MEM_B_DQ<30> BI 63 201 2 201 2 C2540 1 1 C2541 NC A2 DQ31 B8 =MEM_B_DQ<31> BI 63 70 62 53 42 23 22 21 20 19 17 PP1V2_S3 F2 D12 0.047UF 0.047UF A12 G2 E6 10% 10% NC DQS0_C L11 =MEM_B_DQS_N<0> 63 6.3V 6.3V A13 BI H3 VDDCA F6 X5R 2 2 X5R NC G11 =MEM_B_DQS_N<1> 201 201 B1 DQS1_C BI 63 L2 F12 NC DQS2_C P11 =MEM_B_DQS_N<2> B13 BI 63 M2 G6 NC NU DQS3_C D11 =MEM_B_DQS_N<3> 63 T1 BI G9 NC 70 62 53 42 23 22 21 20 19 17 PP1V2_S3 A11 T13 DQS0_T L10 =MEM_B_DQS_P<0> H10 NC BI 63 C12 U1 DQS1_T G10 =MEM_B_DQS_P<1> VSSQ K10 NC BI 63 E8 U2 DQS2_T P10 =MEM_B_DQS_P<2> 63 L9 NC BI E12 U12 DQS3_T D10 =MEM_B_DQS_P<3> M6 NC BI 63 G12 U13 M12 NC H8 B NC C4 H9 N6 P12 B K9 NC H11 NC R6 R3 J9 NC T6 J10 VDDQ T12 K8 K11 70 62 53 42 23 22 21 20 19 17 PP1V2_S3 L12 N8 1 C2500 1 C2501 1 C2502 1 C2503 1 C2504 1 C2505 1 C2506 N12 0.1UF 0.1UF 1UF 1UF 1UF 1UF 10UF R12 10% 10% 10% 10% 10% 10% 20% 16V 16V 10V 10V 10V 10V 25V 2 X5R-CERM 2 X5R-CERM 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R-CERM U11 0201 0201 402 402 402 402 0603 70 62 53 42 23 22 21 20 19 17 PP1V2_S3 1 C2520 1 C2521 1 C2522 1 C2523 1UF 1UF 1UF 10UF 10% 10% 10% 20% 10V 10V 10V 25V 2 X5R 2 X5R 2 X5R 2 X5R-CERM 402 402 402 0603 70 62 53 42 23 22 21 20 19 17 PP1V2_S3 PLACEMENT_NOTE: 1 C2510 1 C2511 1 C2512 1UF 1UF 10UF A 10% 10V 2 X5R 10% 10V 2 X5R 20% 25V 2 X5R-CERM 10uF caps are shared between DRAM. Distribute evenly. SYNC_MASTER=J41_MLB SYNC_DATE=02/06/2013 A 402 402 0603 PAGE TITLE LPDDR3 DRAM Channel B (0-31) DRAWING NUMBER SIZE 62 57 23 22 21 20 PP1V8_S3 Apple Inc. <SCH_NUM> D REVISION R 1 C2530 1 C2531 1 C2532 <E4LABEL> 1UF 1UF 10UF NOTICE OF PROPRIETARY PROPERTY: BRANCH 10% 10% 20% 10V 10V 25V 2 X5R 2 X5R 2 X5R-CERM THE INFORMATION CONTAINED HEREIN IS THE <BRANCH> 402 402 0603 PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 25 OF 121 II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 22 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 D LPDDR3 CHANNEL B (32-63) D U2600 U2600 LPDDR3-16GB LPDDR3-16GB FBGA FBGA MEM_B_CAB<0> R2 (1 OF 2) P9 =MEM_B_DQ<32> PP1V8_S3 A3 (2 OF 2) B2 EDFA232A1MA-GD-F 70 63 24 IN CA0 DQ0 BI 63 62 57 23 22 21 20 EDFA232A1MA-GD-F 70 63 24 MEM_B_CAB<1> P2 CA1 DQ1 N9 =MEM_B_DQ<33> 63 A4 B5 IN BI 70 63 24 MEM_B_CAB<2> N2 CA2 DQ2 N10 =MEM_B_DQ<34> 63 A5 C5 IN BI 70 63 24 MEM_B_CAB<3> N3 CA3 DQ3 N11 =MEM_B_DQ<35> 63 A6 E4 IN BI 70 63 24 MEM_B_CAB<4> M3 CA4 DQ4 M8 =MEM_B_DQ<36> 63 A10 E5 IN BI 70 63 24 MEM_B_CAB<5> F3 CA5 DQ5 M9 =MEM_B_DQ<37> 63 U3 VDD1 F5 IN BI 70 63 24 7 MEM_B_CAB<6> E3 CA6 DQ6 M10 =MEM_B_DQ<38> 63 U4 J12 IN BI 70 63 24 MEM_B_CAB<7> E2 CA7 DQ7 M11 =MEM_B_DQ<39> 63 U5 K2 IN BI 70 63 24 MEM_B_CAB<8> D2 CA8 DQ8 F11 =MEM_B_DQ<40> 63 U6 L6 IN BI 70 63 24 MEM_B_CAB<9> C2 CA9 DQ9 F10 MEM_B_DQ<33> 7 63 70 U10 M5 IN BI DQ10 F9 =MEM_B_DQ<42> 63 VSS N4 MEM_B_CKE<2> K3 CKE0 BI PP1V2_S3 A8 70 24 7 IN OMIT_TABLE F8 =MEM_B_DQ<43> 70 62 53 42 23 22 21 20 19 17 OMIT_TABLE N5 K4 CKE1 DQ11 BI 63 A9 70 24 7 IN MEM_B_CKE<3> E11 R4 CRITICAL DQ12 =MEM_B_DQ<44> BI 63 D4 CRITICAL 70 24 7 MEM_B_CLK_P<1> J3 CK_T DQ13 E10 =MEM_B_DQ<45> 63 R5 IN BI D5 70 24 7 MEM_B_CLK_N<1> J2 CK_C DQ14 E9 =MEM_B_DQ<46> 63 T2 IN BI D6 D9 =MEM_B_DQ<47> T3 C 70 24 22 7 70 24 22 7 IN MEM_B_CS_L<0> MEM_B_CS_L<1> L3 CS0* L4 CS1* DQ15 DQ16 T8 =MEM_B_DQ<48> BI BI 63 63 G5 H5 T4 C IN T9 =MEM_B_DQ<49> T5 DQ17 BI 63 H6 L8 DM0 DQ18 T10 =MEM_B_DQ<50> 63 H2 BI H12 G8 DM1 DQ19 T11 =MEM_B_DQ<51> 63 BI J5 C3 P8 DM2 DQ20 R8 =MEM_B_DQ<52> 63 BI J6 VDD2 D3 D8 DM3 DQ21 R9 =MEM_B_DQ<53> 63 BI K5 F4 DQ22 R10 =MEM_B_DQ<54> 70 63 24 22 7 MEM_B_ODT<0> J8 ODT BI 63 K6 G3 IN R11 =MEM_B_DQ<55> DQ23 BI 63 K12 VSSCA G4 DQ24 C11 =MEM_B_DQ<56> 63 BI L5 P3 MEM_B_ZQ<2> B3 ZQ0 DQ25 C10 =MEM_B_DQ<57> 63 BI P4 M4 MEM_B_ZQ<3> B4 ZQ1 DQ26 C9 =MEM_B_DQ<58> 63 BI P5 J4 DQ27 C8 =MEM_B_DQ<59> 63 PP0V6_S3_MEM_VREFCA_B H4 VREFCA BI P6 R26001 R26011 70 22 19 18 J11 VREFDQ DQ28 B11 =MEM_B_DQ<60> BI 63 U8 B6 243 243 70 22 19 18 PP0V6_S3_MEM_VREFDQ_B B10 B12 1% 1% DQ29 =MEM_B_DQ<61> BI 63 U9 1/20W 1/20W A1 B9 C6 MF MF NC DQ30 =MEM_B_DQ<62> BI 63 201 2 201 2 C2640 1 1 C2641 NC A2 DQ31 B8 =MEM_B_DQ<63> BI 63 70 62 53 42 23 22 21 20 19 17 PP1V2_S3 F2 D12 0.047UF 0.047UF A12 G2 E6 10% 10% NC DQS0_C L11 =MEM_B_DQS_N<4> 63 6.3V 6.3V A13 BI H3 VDDCA F6 X5R 2 2 X5R NC G11 =MEM_B_DQS_N<5> 201 201 B1 DQS1_C BI 63 L2 F12 NC DQS2_C P11 =MEM_B_DQS_N<6> B13 BI 63 M2 G6 NC NU DQS3_C D11 MEM_B_DQS_N<6> 7 63 70 T1 BI G9 NC 70 62 53 42 23 22 21 20 19 17 PP1V2_S3 A11 T13 DQS0_T L10 =MEM_B_DQS_P<4> H10 NC BI 63 C12 U1 DQS1_T G10 =MEM_B_DQS_P<5> VSSQ K10 NC BI 63 E8 U2 DQS2_T P10 =MEM_B_DQS_P<6> 63 L9 NC BI E12 U12 DQS3_T D10 MEM_B_DQS_P<6> M6 NC BI 7 63 70 G12 U13 M12 NC H8 B NC C4 H9 N6 P12 B K9 NC H11 NC R6 R3 J9 NC T6 J10 VDDQ T12 K8 K11 70 62 53 42 23 22 21 20 19 17 PP1V2_S3 L12 N8 1 C2600 1 C2601 1 C2602 1 C2603 1 C2604 1 C2605 1 C2606 N12 0.1UF 0.1UF 1UF 1UF 1UF 1UF 10UF R12 10% 10% 10% 10% 10% 10% 20% 16V 16V 10V 10V 10V 10V 25V 2 X5R-CERM 2 X5R-CERM 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R-CERM U11 0201 0201 402 402 402 402 0603 70 62 53 42 23 22 21 20 19 17 PP1V2_S3 1 C2620 1 C2621 1 C2622 1 C2623 1UF 1UF 1UF 10UF 10% 10% 10% 20% 10V 10V 10V 25V 2 X5R 2 X5R 2 X5R 2 X5R-CERM 402 402 402 0603 70 62 53 42 23 22 21 20 19 17 PP1V2_S3 PLACEMENT_NOTE: 1 C2610 1 C2611 1UF 1UF A 10% 10V 2 X5R 10% 10V 2 X5R 10uF caps are shared between DRAM. Distribute evenly. SYNC_MASTER=J41_MLB SYNC_DATE=02/06/2013 A 402 402 PAGE TITLE LPDDR3 DRAM Channel B (32-63) DRAWING NUMBER SIZE 62 57 23 22 21 20 PP1V8_S3 Apple Inc. <SCH_NUM> D REVISION R 1 C2630 1 C2631 1 C2632 <E4LABEL> 1UF 1UF 10UF NOTICE OF PROPRIETARY PROPERTY: BRANCH 10% 10% 20% 10V 10V 25V 2 X5R 2 X5R 2 X5R-CERM THE INFORMATION CONTAINED HEREIN IS THE <BRANCH> 402 402 0603 PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 26 OF 121 II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 23 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 D Intel reccomends 55 Ohm for CMD/ADDR, 80 Ohm for CTRL/CKE, 38 Ohm for CLK D 62 53 24 PP0V6_S0_DDRVTT 62 53 24 PP0V6_S0_DDRVTT MEM_A_CAA<9> RP2701 56 4 5 MEM_B_CAA<9> RP2712 56 4 5 70 63 20 IN MEM_A_CAA<8> RP2701 56 3 6 5% 1/32W 4X0201-HF 1 C2700 70 63 22 IN MEM_B_CAA<8> RP2712 56 3 6 5% 1/32W 4X0201-HF 1 C2710 70 63 20 IN 5% 1/32W 0.47UF 70 63 22 IN 5% 1/32W 0.47UF 70 63 20 7 IN MEM_A_CAA<6> RP2701 56 2 7 4X0201-HF 20% 4V 70 63 22 IN MEM_B_CAA<7> RP2712 56 2 7 4X0201-HF 20% RP2701 56 5% 1/32W 4X0201-HF 2 CERM-X5R-1 RP2712 56 5% 1/32W 4X0201-HF 2 4V CERM-X5R-1 70 63 20 IN MEM_A_CAA<7> 1 8 201 70 63 22 7 IN MEM_B_CAA<6> 1 8 201 5% 1/32W 5% 1/32W 70 63 20 IN MEM_A_CAA<5> R2700 56 1 2 4X0201-HF 70 63 22 IN MEM_B_CAA<5> R2710 56 1 2 4X0201-HF R2701 39 5% 1/20W 201 MF R2711 39 5% 1/20W 201 MF 70 20 7 IN MEM_A_CLK_P<0> 1 2 70 22 7 IN MEM_B_CLK_P<0> 1 2 R2702 5% 1/20W 201 MF R2712 5% 1/20W 201 MF 70 20 7 IN MEM_A_CLK_N<0> 39 1 2 5% 1/20W 201 MF 1 C2701 1 C2702 70 22 7 IN MEM_B_CLK_N<0> 39 1 2 5% 1/20W 201 MF 1 C2711 1 C2712 70 20 7 IN MEM_A_CKE<1> R2703 82 1 2 0.47UF 20% 0.47UF 20% 70 22 7 IN MEM_B_CKE<1> R2713 82 1 2 0.47UF 20% 0.47UF 20% R2704 5% 1/20W 201 MF 4V 4V R2714 5% 1/20W 201 MF 70 20 7 IN MEM_A_CKE<0> 82 1 2 2 CERM-X5R-1 2 CERM-X5R-1 70 22 7 IN MEM_B_CKE<0> 82 1 2 2 4V CERM-X5R-1 4V 2 CERM-X5R-1 R2705 56 5% 1/20W 201 MF 201 201 R2715 56 5% 1/20W 201 MF 201 201 70 63 20 IN MEM_A_CAA<4> 1 2 70 63 22 IN MEM_B_CAA<4> 1 2 R2706 56 5% 1/20W 201 MF R2716 56 5% 1/20W 201 MF 70 63 20 IN MEM_A_CAA<3> 1 2 70 63 22 IN MEM_B_CAA<2> 1 2 5% 1/20W 201 MF 5% 1/20W 201 MF 70 63 20 IN MEM_A_CAA<2> RP2703 56 4 5 70 63 22 IN MEM_B_CAA<3> RP2713 56 4 5 5% 1/32W 5% 1/32W 70 63 20 IN MEM_A_CAA<1> RP2703 56 3 6 4X0201-HF 1 C2703 1 C2704 70 63 22 IN MEM_B_CAA<1> RP2713 56 3 6 4X0201-HF 1 C2713 1 C2714 5% 1/32W 5% 1/32W 70 63 20 IN MEM_A_CAA<0> RP2703 56 2 7 4X0201-HF 0.47UF 20% 0.47UF 20% 70 63 22 IN MEM_B_CAA<0> RP2713 56 2 7 4X0201-HF 0.47UF 20% 0.47UF 20% R2725 5% 1/32W 4X0201-HF 4V 4V R2735 5% 1/32W 4X0201-HF 70 63 21 IN MEM_A_CAB<9> 56 1 2 2 CERM-X5R-1 2 CERM-X5R-1 70 63 23 IN MEM_B_CAB<9> 56 1 2 2 4V CERM-X5R-1 4V 2 CERM-X5R-1 RP2707 56 5% 1/20W 201 MF 201 201 RP2717 56 5% 1/20W 201 MF 201 201 70 63 21 IN MEM_A_CAB<8> 4 5 70 63 23 IN MEM_B_CAB<8> 4 5 RP2707 56 5% 1/32W 4X0201-HF RP2717 56 5% 1/32W 4X0201-HF 70 63 21 7 IN MEM_A_CAB<6> 3 6 70 63 23 IN MEM_B_CAB<7> 3 6 RP2707 56 5% 1/32W 4X0201-HF RP2717 56 5% 1/32W 4X0201-HF 70 63 21 IN MEM_A_CAB<7> 2 7 70 63 23 7 IN MEM_B_CAB<6> 2 7 RP2707 56 5% 1/32W 4X0201-HF RP2717 56 5% 1/32W 4X0201-HF 70 63 21 IN MEM_A_CAB<5> 1 8 5% 1/32W 1 C2705 1 C2706 70 63 23 IN MEM_B_CAB<5> 1 8 5% 1/32W 1 C2715 1 C2716 70 21 7 IN MEM_A_CLK_P<1> R2707 39 1 2 4X0201-HF 0.47UF 20% 0.47UF 20% 70 23 7 IN MEM_B_CLK_N<1> R2717 39 1 2 4X0201-HF 0.47UF 20% 0.47UF 20% R2708 5% 1/20W 201 MF 4V 4V R2718 5% 1/20W 201 MF 70 21 7 IN MEM_A_CLK_N<1> 39 1 2 2 CERM-X5R-1 2 CERM-X5R-1 70 23 7 IN MEM_B_CLK_P<1> 39 1 2 2 4V CERM-X5R-1 4V 2 CERM-X5R-1 5% 1/20W 201 MF 5% 1/20W 201 MF 70 21 7 IN MEM_A_CKE<2> R2709 82 1 2 201 201 70 23 7 IN MEM_B_CKE<2> R2719 82 1 2 201 201 5% 1/20W 201 MF 5% 1/20W 201 MF 70 21 7 IN MEM_A_CKE<3> R2720 82 1 2 70 23 7 IN MEM_B_CKE<3> R2730 82 1 2 5% 1/20W 201 MF 5% 1/20W 201 MF MEM_A_CAB<4> R2721 56 MEM_B_CAB<4> R2731 56 C 70 63 21 70 63 21 IN IN MEM_A_CAB<2> RP2704 56 1 4 2 5 5% 5% 1/20W 1/32W 201 MF 1 C2707 1 C2708 70 63 23 70 63 23 IN IN MEM_B_CAB<2> RP2714 56 1 4 2 5 5% 5% 1/20W 1/32W 201 MF 1 C2717 1 C2718 C 70 63 21 IN MEM_A_CAB<3> RP2704 56 3 6 4X0201-HF 0.47UF 20% 0.47UF 20% 70 63 23 IN MEM_B_CAB<3> RP2714 56 3 6 4X0201-HF 0.47UF 20% 0.47UF 20% RP2704 56 5% 1/32W 4X0201-HF 4V 4V RP2714 56 5% 1/32W 4X0201-HF 70 63 21 IN MEM_A_CAB<1> 2 7 2 CERM-X5R-1 2 CERM-X5R-1 70 63 23 IN MEM_B_CAB<1> 2 7 2 4V CERM-X5R-1 4V 2 CERM-X5R-1 RP2704 56 5% 1/32W 4X0201-HF 201 201 RP2714 56 5% 1/32W 4X0201-HF 201 201 70 63 21 IN MEM_A_CAB<0> 1 8 70 63 23 IN MEM_B_CAB<0> 1 8 5% 1/32W 5% 1/32W 70 21 20 7 IN MEM_A_CS_L<0> R2722 82 1 2 4X0201-HF 70 23 22 7 IN MEM_B_CS_L<0> R2732 82 1 2 4X0201-HF 5% 1/20W 201 MF 5% 1/20W 201 MF 70 21 20 7 IN MEM_A_CS_L<1> R2723 82 1 2 70 23 22 7 IN MEM_B_CS_L<1> R2733 82 1 2 5% 1/20W 201 MF 5% 1/20W 201 MF 70 63 21 20 7 IN MEM_A_ODT<0> R2724 82 1 2 1 C2709 70 63 23 22 7 IN MEM_B_ODT<0> R2734 82 1 2 1 C2719 5% 1/20W 201 MF 0.47UF 5% 1/20W 201 MF 0.47UF 20% 20% 4V 2 CERM-X5R-1 2 4V Spare Spare CERM-X5R-1 201 201 RP2703 RP2713 56 56 1 8 CRITICAL 1 8 CRITICAL NC NC NC NC 5% 1/32W PLACE_NEAR=RP2701.5:4mm 1 C2720 5% 1/32W PLACE_NEAR=RP2714.8:4mm 1 C2740 4X0201-HF 22UF 4X0201-HF 22UF 20% 20% 2 6.3V X5R-CERM-1 2 6.3V X5R-CERM-1 603 603 B B A SYNC_MASTER=J41_MLB SYNC_DATE=02/06/2013 A PAGE TITLE LPDDR3 DRAM Termination DRAWING NUMBER SIZE Apple Inc. <SCH_NUM> D REVISION R <E4LABEL> NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. <BRANCH> THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 27 OF 121 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 24 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 CRITICAL 69 14 IN PCIE_TBT_R2D_C_P<0> C2800 1 2 16V PCIE_TBT_R2D_P<0> AB9 OMIT_TABLE AD5 PCIE_TBT_D2R_C_P<0> C2840 1 2 PCIE_TBT_D2R_P<0> OUT 14 69 10% X5R-CERM 0201 69 PERP_0 PETP_0 69 10% 16V X5R-CERM 0201 0.1UF AA10 U2800 AD7 0.1UF 69 PCIE_TBT_R2D_N<0> PERN_0 PETN_0 69 PCIE_TBT_D2R_C_N<0> 69 14 IN PCIE_TBT_R2D_C_N<0> C2801 1 2 10% 16V X5R-CERM 0201 CACTUSRIDGE4C C2841 1 2 10% PCIE_TBT_D2R_N<0> 16V X5R-CERM 0201 OUT 14 69 0.1UF FCBGA 0.1UF (SYM 1 OF 2) 69 14 IN PCIE_TBT_R2D_C_P<1> C2802 1 2 16V AA12 AD9 C2842 1 2 PCIE_TBT_D2R_P<1> OUT 14 69 PCIE GEN2 10% X5R-CERM 0201 69 PCIE_TBT_R2D_P<1> PERP_1 PETP_1 69 PCIE_TBT_D2R_C_P<1> 10% 16V X5R-CERM 0201 0.1UF AB13 AD11 0.1UF 69 PCIE_TBT_R2D_N<1> PERN_1 PETN_1 69 PCIE_TBT_D2R_C_N<1> C2803 C2843 RECEIVE TRANSMIT 69 14 IN PCIE_TBT_R2D_C_N<1> 1 2 16V 1 2 PCIE_TBT_D2R_N<1> OUT 14 69 10% X5R-CERM 0201 10% 16V X5R-CERM 0201 0.1UF 0.1UF 69 14 PCIE_TBT_R2D_C_P<2> C2804 1 2 16V C2844 1 2 PCIE_TBT_D2R_P<2> 14 69 D IN 0.1UF 10% X5R-CERM 0201 69 PCIE_TBT_R2D_P<2> PCIE_TBT_R2D_N<2> AB15 AA16 PERP_2 PERN_2 PETP_2 PETN_2 AD13 AD15 69 PCIE_TBT_D2R_C_P<2> PCIE_TBT_D2R_C_N<2> 0.1UF 10% 16V X5R-CERM 0201 OUT D 69 14 IN PCIE_TBT_R2D_C_N<2> C2805 1 2 16V 69 69 C2845 1 2 PCIE_TBT_D2R_N<2> OUT 14 69 10% X5R-CERM 0201 10% 16V X5R-CERM 0201 0.1UF 0.1UF 62 28 27 26 25 PP3V3_S4_TBTAPWR 69 14 IN PCIE_TBT_R2D_C_P<3> C2806 1 2 10% 16V X5R-CERM 0201 69 PCIE_TBT_R2D_P<3> AA18 PERP_3 PETP_3 AD17 69 PCIE_TBT_D2R_C_P<3> C2846 1 2 10% PCIE_TBT_D2R_P<3> 16V X5R-CERM 0201 OUT 14 69 R28101 0.1UF AB19 AD19 0.1UF PCIE_TBT_R2D_N<3> PERN_3 PETN_3 PCIE_TBT_D2R_C_N<3> 47K 5% 69 14 IN PCIE_TBT_R2D_C_N<3> C2807 1 2 10% 16V X5R-CERM 0201 69 69 C2847 1 2 10% PCIE_TBT_D2R_N<3> 16V X5R-CERM 0201 OUT 14 69 1/20W 0.1UF 0.1UF MF R6 U20 201 2 27 IN TBT_PCIE_RESET_L PERST_N RSENSE TBT_RSENSE 27 TBT_PWR_ON_POC_RST_L J2 PWR_ON_POC_RSTN IN W20 TBT_RBIAS 1 NO STUFF RBIAS R2855 NOTE: The following pins require testpoints: 1K PP3V3_TBTLC 15 17 25 26 27 62 64 C2810 1 TP_TBT_MONDC0 AD23 MONDC0 NC U4 1% 1/20W 0 - GPIO_13 8 - GPIO_15 0.1UF OMIT TP_TBT_MONDC1 AC24 MONDC1 NC MF 1 - GPIO_1 9 - GPIO_11 10% 16V 2 201 BYPASS=U2890.8:2mm X5R-CERM 2 R28151 DEBUG: For monitoring current/voltage 2 - GPIO_2 10 - GPIO_14 C2890 1 R28921 1 R2893 0201 NOSTUFF TBT_MONOBSP W18 MONOBS_P 3 - GPIO_3 11 - GPIO_0 R28901 1 R2891 1UF 10% 3.3K 3.3K NONE NONE TBT_MONOBSN W16 MONOBS_N 4 - GPIO_5 12 - GPIO_12 3.3K 3.3K 6.3V 2 5% 5% NONE Not used in host mode. PCIE RESET 5% 5% 1/20W 1/20W 0201 2 DEBUG: For monitoring clock 5 - PCIE_RST_1_N 13 - GPIO_10 MISC 1/20W 1/20W CERM CRITICAL MF MF PCIE_RST_0_N N6 TP_TBT_PCIE_RESET0_L MF MF 402 201 2 TP_TBT_THERM_DP Y7 6 - PCIE_RST_2_N 14 - PB_LSTX 201 2 OMIT_TABLE 2 201 THERMDA T1 TP_TBT_PCIE_RESET1_L 2 201 8 Use AA8 GND ball for THERM_DN PCIE_RST_1_N 7 - PCIE_RST_3_N 15 - PB_LSRX VCC PCIE_RST_2_N Y5 TP_TBT_PCIE_RESET2_L 71 TBT_SPI_MOSI R4 EE_DI U2 TP_TBT_PCIE_RESET3_L EEPROM P5 PCIE_RST_3_N (TBT_SPI_MOSI) 5 D U2890 Q 2 (TBT_SPI_MISO) 71 TBT_SPI_MISO EE_DO M95256-RMC6XG 71 TBT_SPI_CS_L AD3 EE_CS_N (TBT_SPI_CLK) 6 C MLP PCIE_CLKREQ_OD_N W6 TBT_CLKREQ_ISOL_L 27 71 TBT_SPI_CLK W4 EE_CLK OUT PP3V3_TBTLC 15 17 25 26 27 62 64 (TBT_SPI_CS_L) 1 S* K5 TBT_EN_LC_PWR JTAG/TEST PORT V1 EN_LC_PWR OUT 27 18 16 15 IN XDP_JTAG_ISP_TDI TDI 1 R2898 TBTROM_WP_L 3 W* AB3 18 15 IN JTAG_TBT_TMS TMS 10K AA6 REFCLK_100_IN_P AB21 PCIE_CLK100M_TBT_P IN 12 69 5% TBTROM_HOLD_L 7 HOLD* XDP_JTAG_ISP_TCK C VSS THM PAD 18 16 15 18 15 IN OUT JTAG_ISP_TDO R2 TCK TDO REFCLK_100_IN_N AD21 PCIE_CLK100M_TBT_N IN 12 69 1/20W MF 2 201 R2895 C TBT_TEST_EN N4 806 CLOCKS TEST_EN AA24 4 9 AB5 XTAL_25_IN 69 SYSCLK_CLK25M_TBT_R 1 2 SYSCLK_CLK25M_TBT IN 17 69 TBT_TEST_PWR_GOOD TEST_PWR_GOOD AB23 XTAL_25_OUT TP_TBT_XTAL25OUT 1% 1/20W MF Divides 3.3V to 1.8V R28251 1 R2829 67 25 DP_TBTSNK0_ML_P<3> E14 DPSNK0_3_P TMU_CLK_OUT AA4 TBT_TMU_CLK_OUT 201 0 0 DP_TBTSNK0_ML_N<3> D13 Y3 TBT_TMU_CLK_IN PP3V3_TBTLC 5% 5% 67 25 DPSNK0_3_N TMU_CLK_IN 64 62 27 26 25 17 15 1/20W 1/20W MF MF DP_TBTSNK0_ML_P<2> E16 NO STUFF 0201 2 2 0201 67 25 DPSNK0_2_P 1 1 1 1 67 25 DP_TBTSNK0_ML_N<2> D15 DPSNK0_2_N DPSRC_3_P A14 TP_DP_TBTSRC_ML_CP<3> 64 R2897 R2899 R2896 R2880 DISPLAYPORT 100K 10K 1K 10K SINK PORT 0 DPSRC_3_N B15 TP_DP_TBTSRC_ML_CN<3> 5% 5% 5% 5% 67 25 DP_TBTSNK0_ML_P<1> E18 DPSNK0_1_P 64 1/20W 1/20W 1/20W 1/20W D17 A12 MF MF MF MF 67 25 DP_TBTSNK0_ML_N<1> DPSNK0_1_N DPSRC_2_P TP_DP_TBTSRC_ML_CP<2> 64 2 201 201 2 2 201 2 201 DPSRC_2_N B13 TP_DP_TBTSRC_ML_CN<2> 64 DP_TBTSNK0_ML_P<0> E20 TBT_DDC_XBAR_EN_L SOURCE PORT 0 67 25 DPSNK0_0_P 25 67 25 DP_TBTSNK0_ML_N<0> D19 DPSNK0_0_N DPSRC_1_P A10 NC_DP_TBTSRC_ML_CP<1> 64 TBT_GO2SX_BIDIR 25 18 15 DPSRC_1_N B11 NC_DP_TBTSRC_ML_CN<1> R2881 for CYA, 67 25 DP_TBTSNK0_AUXCH_P A6 DPSNK0_AUX_P 64 allows separation 1 DP_TBTSNK0_AUXCH_N B5 DPSNK0_AUX_N DPSRC_0_P A8 TP_DP_TBTSRC_ML_CP<0> R2881 SNK0 AC Coupling 67 25 DPSRC_0_N B9 TP_DP_TBTSRC_ML_CN<0> 64 64 of GPIO_2/GPIO_9 5% 0 DP_TBTSNK0_HPD U6 DPSNK0_HPD if necessary. 67 5 IN DP_TBTSNK0_ML_C_P<0> C2820 1 2 DP_TBTSNK0_ML_P<0> 25 67 13 OUT C2 1/20W MF 10% 16V 0201 DPSRC_AUX_P NC_DP_TBTSRC_AUXCH_CP 64 Stuff one of R2881/2. 2 0201 0.1UF X5R-CERM E6 D3 R28301 DP_TBTSNK1_ML_P<3> DPSNK1_3_P DPSRC_AUX_N NC_DP_TBTSRC_AUXCH_CN 67 5 IN DP_TBTSNK0_ML_C_N<0> C2821 1 2 DP_TBTSNK0_ML_N<0> 25 67 100K 67 25 DP_TBTSNK1_ML_N<3> D5 64 25 TBT_GPIO_9 10% 16V 0201 67 25 DPSNK1_3_N V3 0.1UF X5R-CERM 5% DPSRC_HPD_OD DP_TBTSRC_HPD 25 TBT_GPIO_14 1/20W E8 DP_TBTSNK1_ML_P<2> DPSNK1_2_P NO STUFF 67 5 IN DP_TBTSNK0_ML_C_P<1> C2822 1 2 DP_TBTSNK0_ML_P<1> 25 67 MF 201 2 67 25 DP_TBTSNK1_ML_N<2> D7 1 0.1UF 10% 16V 0201 67 25 DPSNK1_2_N Y1 TBT_GO2SX_BIDIR R2832 R28831 1 R2882 SINK PORT 1 X5R-CERM GPIO_2/GO2SX BI 15 18 25 DP_TBTSNK0_ML_C_N<1> C2823 E10 W2 100K 10K 10K 67 5 IN 1 2 DP_TBTSNK0_ML_N<1> 25 67 67 25 DP_TBTSNK1_ML_P<1> DPSNK1_1_P (FORCE_PWR) GPIO_3 TBT_PWR_EN IN 15 5% 5% 5% 10% 16V 0201 D9 J4 1/20W 1/20W 1/20W 0.1UF X5R-CERM 67 25 DP_TBTSNK1_ML_N<1> DPSNK1_1_N GPIO_4/WAKE_N_OD SMC_PME_S4_DARK_L 33 37 38 MF MF MF B 67 5 IN DP_TBTSNK0_ML_C_P<2> C2824 1 2 DP_TBTSNK0_ML_P<2> 25 67 67 25 DP_TBTSNK1_ML_P<0> E12 DPSNK1_0_P GPIO_5/CIO_PLUG_EVENT AA2 AB1 TBT_CIO_PLUG_EVENT OUT OUT 15 18 2 201 201 2 2 201 B 10% 16V 0201 D11 GPIO_6/CIO_SDA_OD SMBUS_PCH_DATA BI 14 16 19 40 56 69 0.1UF X5R-CERM 67 25 DP_TBTSNK1_ML_N<0> DPSNK1_0_N AC2 GPIO_7/CIO_SCL_OD SMBUS_PCH_CLK 67 5 IN DP_TBTSNK0_ML_C_N<2> C2825 1 2 10% 16V DP_TBTSNK0_ML_N<2> 0201 25 67 67 25 DP_TBTSNK1_AUXCH_P A4 DPSNK1_AUX_P GPIO_8/EN_CIO_PWR_OD* P3 (TBT_EN_CIO_PWR_L) IN 14 16 19 40 56 69 TBT_EN_CIO_PWR_L 13 25 27 0.1UF OUT X5R-CERM B3 M5 67 25 DP_TBTSNK1_AUXCH_N DPSNK1_AUX_N GPIO_9/OK2GO2SX_OD* TBT_GPIO_9 25 TBT_EN_CIO_PWR_L OUT 13 25 27 MAKE_BASE=TRUE PP3V3_S4_TBTAPWR 67 5 IN DP_TBTSNK0_ML_C_P<3> C2826 1 2 10% 16V DP_TBTSNK0_ML_P<3> 0201 25 67 18 13 DP_TBTSNK1_HPD T5 DPSNK1_HPD GPIO_14 T3 TBT_GPIO_14 25 62 28 27 26 25 0.1UF OUT V5 TBT_DDC_XBAR_EN_L X5R-CERM GPIO_15 OUT 25 67 5 IN DP_TBTSNK0_ML_C_N<3> C2827 1 2 DP_TBTSNK0_ML_N<3> 25 67 0.1UF 10% 16V X5R-CERM 0201 R28311 71 28 OUT TBT_A_R2D_C_P<0> G24 PA_CIO0_TX_P/DP_SRC_0_P PB_CIO2_TX_P/DP_SRC_0_P R24 NC_TBT_B_R2D_CP<0> OUT 64 R28851 1 R2886 100K E24 N24 10K 10K 5% 71 28 OUT TBT_A_R2D_C_N<0> PA_CIO0_TX_N/DP_SRC_0_N PB_CIO2_TX_N/DP_SRC_0_N NC_TBT_B_R2D_CN<0> OUT 64 5% 5% 1/20W 1/20W 1/20W DP_TBTSNK0_AUXCH_C_P C2828 1 2 DP_TBTSNK0_AUXCH_P MF MF MF PORT0 PORT2 67 13 BI 25 67 G22 R22 10% 16V 0201 201 2 71 28 IN TBT_A_D2R_P<0> PA_CIO0_RX_P PB_CIO2_RX_P NC_TBT_B_D2RP<0> IN 64 201 2 2 201 0.1UF X5R-CERM E22 N22 TBT_A_D2R_N<0> PA_CIO0_RX_N PB_CIO2_RX_N NC_TBT_B_D2RN<0> 67 13 BI DP_TBTSNK0_AUXCH_C_N C2829 1 2 10% 16V DP_TBTSNK0_AUXCH_N 0201 25 67 71 28 IN IN 64 28 25 TBT_A_DP_PWRDN 0.1UF X5R-CERM 28 TBT_A_CONFIG1_BUF K1 PA_CONFIG1/CIO_0_LSEO PB_CONFIG1/CIO_2_LSEO P1 TBT_B_CONFIG1_BUF 18 25 TBT_B_DP_PWRDN IN IN 28 TBT_A_CONFIG2_RC G4 PA_CONFIG2/CIO_0_LSOE PB_CONFIG2/CIO_2_LSOE H5 TBT_B_CONFIG2_RC 18 28 27 25 TBT_A_HV_EN IN IN SNK1 AC Coupling 25 TBT_B_HV_EN TBT_A_R2D_C_P<1> L24 PA_CIO1_TX_P/DP_SRC_2_P PB_CIO3_TX_P/DP_SRC_2_P W24 NC_TBT_B_R2D_CP<1> 67 18 5 IN DP_TBTSNK1_ML_C_P<0> C2830 1 2 DP_TBTSNK1_ML_P<0> 25 67 71 28 OUT TBT_A_R2D_C_N<1> J24 U24 NC_TBT_B_R2D_CN<1> OUT 64 10% 16V 0.1UF X5R-CERM 0201 71 28 OUT PA_CIO1_TX_N/DP_SRC_2_N PB_CIO3_TX_N/DP_SRC_2_N OUT 64 R28881 1 R2887 10K 10K C2831 PORT1 PORT3 67 18 5 DP_TBTSNK1_ML_C_N<0> 1 2 DP_TBTSNK1_ML_N<0> 25 67 71 28 TBT_A_D2R_P<1> L22 PA_CIO1_RX_P PB_CIO3_RX_P W22 NC_TBT_B_D2RP<1> 64 5% 5% IN IN IN 10% 16V 0201 J22 U22 1/20W 1/20W 0.1UF X5R-CERM 71 28 IN TBT_A_D2R_N<1> PA_CIO1_RX_N PB_CIO3_RX_N NC_TBT_B_D2RN<1> IN 64 MF MF 201 2 2 201 67 18 5 IN DP_TBTSNK1_ML_C_P<1> C2832 1 2 10% 16V DP_TBTSNK1_ML_P<1> 0201 25 67 28 OUT TBT_A_LSTX N2 PA_LSTX/CIO_1_LSEO PB_LSTX/CIO_3_LSEO L6 NC_TBT_B_LSTX OUT 64 0.1UF X5R-CERM 28 TBT_A_LSRX J6 PA_LSRX/CIO_1_LSOE PB_LSRX/CIO_3_LSOE G6 TBT_B_LSRX 18 IN IN 67 18 5 IN DP_TBTSNK1_ML_C_N<1> C2833 1 2 10% 16V DP_TBTSNK1_ML_N<1> 0201 25 67 0.1UF DP_TBTPA_ML_C_P<1> A16 A20 DP_TBTPB_ML_C_P<1> PORTS X5R-CERM 71 28 OUT PA_DPSRC_1_P PB_DPSRC_1_P OUT DP_TBTPA_ML_C_N<1> B17 B21 DP_TBTPB_ML_C_N<1> A 67 18 5 IN DP_TBTSNK1_ML_C_P<2> C2834 0.1UF 1 2 10% 16V X5R-CERM DP_TBTSNK1_ML_P<2> 0201 25 67 71 28 71 28 OUT DP_TBTPA_ML_C_P<3> A18 PA_DPSRC_1_N PA_DPSRC_3_P PB_DPSRC_1_N PB_DPSRC_3_P A22 DP_TBTPB_ML_C_P<3> OUT SYNC_MASTER=J41_MLB SYNC_DATE=02/06/2013 A OUT OUT PAGE TITLE 67 18 5 IN DP_TBTSNK1_ML_C_N<2> C2835 1 2 10% 16V DP_TBTSNK1_ML_N<2> 0201 25 67 71 28 OUT DP_TBTPA_ML_C_N<3> B19 PA_DPSRC_3_N PB_DPSRC_3_N B23 DP_TBTPB_ML_C_N<3> OUT Thunderbolt Host (1 of 2) 0.1UF X5R-CERM F3 D1 DRAWING NUMBER SIZE DP_TBTPA_AUXCH_C_P PA_AUX_P PB_AUX_P NC_DP_TBTPB_AUXCH_CP 67 18 5 IN DP_TBTSNK1_ML_C_P<3> C2836 1 2 10% 16V DP_TBTSNK1_ML_P<3> 0201 25 67 71 28 71 28 BI DP_TBTPA_AUXCH_C_N F1 PA_AUX_N PB_AUX_N E2 NC_DP_TBTPB_AUXCH_CN BI 64 71 64 71 Apple Inc. <SCH_NUM> D 0.1UF BI BI X5R-CERM REVISION 67 18 5 IN DP_TBTSNK1_ML_C_N<3> C2837 1 2 10% 16V DP_TBTSNK1_ML_N<3> 0201 25 67 28 IN DP_TBTPA_HPD H1 PA_DPSRC_HPD PB_DPSRC_HPD K3 DP_TBTPB_HPD IN 18 R <E4LABEL> 0.1UF X5R-CERM G2 M1 NOTICE OF PROPRIETARY PROPERTY: BRANCH TBT_A_HV_EN GPIO_0/PA_HV_EN/BYP0 GPIO_1/PB_HV_EN/BYP0 TBT_B_HV_EN 28 27 25 OUT TBT_A_CIO_SEL M3 GPIO_10/PA_CIO_SEL/BYP1 GPIO_11/PB_CIO_SEL/BYP1 L2 TBT_B_CIO_SEL OUT 25 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. <BRANCH> 67 18 13 BI DP_TBTSNK1_AUXCH_C_P C2838 1 2 10% 16V DP_TBTSNK1_AUXCH_P 0201 25 67 28 OUT TBT_A_DP_PWRDN H3 GPIO_12/PA_DP_PWRDN/BYP2 GPIO_13/PB_DP_PWRDN/BYP2 L4 TBT_B_DP_PWRDN OUT 18 THE POSESSOR AGREES TO THE FOLLOWING: PAGE 0.1UF X5R-CERM 28 25 OUT OUT 25 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 28 OF 121 67 18 13 BI DP_TBTSNK1_AUXCH_C_N C2839 1 2 10% 16V DP_TBTSNK1_AUXCH_N 0201 25 67 For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC. II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 0.1UF X5R-CERM IV ALL RIGHTS RESERVED 25 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 PP1V05_TBTCIO 27 62 64 CRITICAL D PP1V05_TBTLC 64 62 27 J10 OMIT_TABLE K11 ???? mW (Single-Port) 2700 mW (Dual-Port) D ??? mW (Single Port) VCC1P0_ON VCC1P0 250 mW (Dual Port) J12 VCC1P0_ON U2800 VCC1P0 K15 EDP: 1100 mA EDP: 1600 mA C2900 1 1 C2910 1 C2911 1 C2912 1 C2913 J14 VCC1P0_ON CACTUSRIDGE4C VCC1P0 L10 C2940 1 C2941 1 C2942 1 C2943 1 C2944 1 C2945 1 1 C2905 10UF 1.0UF 1.0UF 1.0UF 1.0UF J16 FCBGA L14 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 10UF 20% 20% 20% 20% 20% VCC1P0_ON (SYM 2 OF 2) VCC1P0 20% 20% 20% 20% 20% 20% 20% 6.3V 2 6.3V 6.3V 2 6.3V 2 6.3V J8 M11 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 2 6.3V CERM-X5R 2 X5R 2 X5R X5R X5R VCC1P0_ON VCC1P0 X5R X5R X5R X5R X5R X5R CERM-X5R 0402-1 0201-1 0201-1 0201-1 0201-1 K17 VCC1P0_ON VCC1P0 M15 0201-1 0201-1 0201-1 0201-1 0201-1 0201-1 0402-1 T15 VCC1P0_ON VCC1P0 N10 U14 VCC1P0_ON VCC1P0 N14 V7 VCC1P0_ON VCC1P0 P11 C2901 1 1 C2914 1 C2915 1 C2916 1 C2917 W8 VCC1P0_ON VCC1P0 P15 10UF 1.0UF 1.0UF 1.0UF 1.0UF G10 VCC1P0 R10 20% 20% 20% 20% 20% VCC1P0_PE VCC 6.3V 2 6.3V 6.3V 2 6.3V 2 6.3V R14 CERM-X5R 2 X5R 2 X5R X5R X5R G12 VCC1P0_PE VCC1P0 0402-1 0201-1 0201-1 0201-1 0201-1 VCC1P0 T11 G14 VCC1P0_PE VCC1P0 U10 G16 VCC1P0_PE VCC1P0 V11 G18 VCC1P0_PE PP3V3_TBTLC VCC1P0 W10 15 17 25 27 62 64 H19 VCC1P0_PE ??? mW (Single-Port) K19 VCC1P0_PE 250 mW (Dual-Port) VCC3P3 M7 M19 VCC1P0_PE EDP: 50 mA VCC3P3 P7 P19 VCC1P0_PE T19 VCC1P0_PE VCC3P3 T7 C2970 1 C2971 1 C2972 1 C2973 1 C2974 1 1 C2960 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 10UF V15 VCC1P0_PE VCC3P3_CIO L18 20% 20% 20% 20% 20% 20% 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 2 6.3V V19 VCC1P0_PE VCC3P3_CIO N18 X5R X5R X5R X5R X5R CERM-X5R 0201-1 0201-1 0201-1 0201-1 0201-1 0402-1 W12 VCC1P0_PE VCC3P3_CIO R18 W14 VCC1P0_PE VCC3P3_DP H11 H13 C G8 H9 VCC1P0_DPAUX VCC1P0_DPAUX VCC3P3_DP VCC3P3_DP H15 C VCC3P3_DP H17 AD1 VSS VCC3P3_DPAUX H7 K13 VSS K9 VSS L12 VSS PP3V3_S4_TBTAPWR 25 27 28 62 L16 VSS VCC3P3_POC K7 EDP: 10 mA L8 VSS M13 VSS VSSPE C22 C2990 1 M17 VSS VSSPE C24 1.0UF 20% M9 VSS VSSPE C4 6.3V 2 X5R N12 VSS VSSPE C6 0201-1 N16 VSS VSSPE C8 N8 VSS VSSPE D21 P13 VSS VSSPE D23 P17 VSS VSSPE E4 P9 VSS VSSPE F11 R12 VSS VSSPE F13 R16 VSS VSSPE F15 R8 VSS VSSPE F17 T13 VSS VSSPE F19 T17 VSS VSSPE F21 T9 VSS VSSPE F23 U12 VSS VSSPE F5 GND U16 VSS VSSPE F7 U8 F9 B V9 VSS VSS VSSPE VSSPE G20 B VSSPE H21 A2 VSSPE VSSPE H23 A24 VSSPE VSSPE J18 AA14 VSSPE VSSPE J20 AA20 VSSPE VSSPE K21 AA22 VSSPE VSSPE K23 AA8 VSSPE VSSPE L20 AB11 VSSPE VSSPE M21 AB17 VSSPE VSSPE M23 AB7 VSSPE VSSPE N20 AC10 VSSPE VSSPE P21 AC12 VSSPE VSSPE P23 AC14 VSSPE VSSPE R20 AC16 VSSPE VSSPE T21 AC18 VSSPE VSSPE T23 AC20 VSSPE VSSPE U18 AC22 VSSPE VSSPE V13 AC4 VSSPE VSSPE V17 AC6 VSSPE VSSPE V21 AC8 VSSPE VSSPE V23 B1 VSSPE VSSPE Y11 B7 VSSPE VSSPE Y13 C10 VSSPE VSSPE Y15 C12 VSSPE VSSPE Y17 A C14 C16 VSSPE VSSPE VSSPE VSSPE Y19 Y21 SYNC_MASTER=J41_MLB SYNC_DATE=02/06/2013 A PAGE TITLE C18 Y23 C20 VSSPE VSSPE VSSPE VSSPE Y9 Thunderbolt Host (2 of 2) DRAWING NUMBER SIZE Apple Inc. <SCH_NUM> D REVISION R <E4LABEL> NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. <BRANCH> THE POSESSOR AGREES TO THE FOLLOWING: PAGE EDP numbers are from 12/22/2011 email from Haim Lustig (Intel) to Paul Baker (Apple) I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 29 OF 121 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET Power consumption figures from CR DG v0.57, IBL doc #472455. IV ALL RIGHTS RESERVED 26 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 Page Notes SI8409DB: Vds(max): -30V Power aliases required by this page: CRITICAL Vgs(max): +/-12V TBT 15V Boost Regulator - =PPVIN_SW_TBTBST (8-13V Boost Input) Vgs(th): -1.4V Q3080 CRITICAL - =PP15V_TBT_REG (15V Boost Output) Rds(on): 46mOhm @ 4.5V Vgs L3095 CRITICAL SI8409DB - =PP3V3_TBT_P3V3TBTFET (3.3V FET Input) 64 62 56 50 49 42 41 PPBUS_G3H BGA Id(max): 3.7A @ 70C 6.8UH-4.0A D3095 POWERDI-123 PP15V_TBT 28 62 64 - =PP3V3_TBT_FET (3.3V FET Output) 8-13V Input 2 3 64 62 PPVIN_S4SW_TBTBST_FET 1 2 TBTBST_BOOST A K - =PP3V3_S0_TBTPWRCTL Changes required MIN_LINE_WIDTH=0.5 mm MIN_LINE_WIDTH=0.5 mm Vout = 15.1V S D 4 MIN_NECK_WIDTH=0.25 mm PIMB062D-SM MIN_NECK_WIDTH=0.25 mm - =PP1V05_TBT_P1V05TBTFET (1.05V FET Input) for 2S. SWITCH_NODE=TRUE R3089 DFLS230L - =PP1V05_TBT_FET (1.05V FET Output) Voltage not specified here, add property on another page. C3090 1 C3091 1 DIDT=TRUE 0 Max Current = 1.0A R30801 10UF 10UF TBTBST_SNS1 1 2 C3080 Freq = 300KHz G 1 20% 20% MIN_LINE_WIDTH=0.2 mm 470K 25V 25V Signal aliases required by this page: 0.1UF X5R-CERM 2 X5R-CERM 2 MIN_NECK_WIDTH=0.2 mm 5% 1/20W 5% - =TBT_CLKREQ_L 10% 0603 0603 MF D 1 1/20W D - =TBT_RESET_L MF 201 2 25V 2 X5R 402 R30911 200K TBTBST_SNS2 0201 XW3095 27 8 9 20 21 38 1% MIN_LINE_WIDTH=0.2 mm SM BOM options provided by this page: TBTBST_PWREN_DIV_L 1/20W VIN MIN_NECK_WIDTH=0.2 mm MF SW TBTBST_VSNS 2 1 PLACE_NEAR=C3095.1:2 mm (NONE) 201 2 MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm R30811 <R1> TBTBST_EN_UVLO 25 EN/UVLO CRITICAL 6 2 150K U3090 SNS1 R3090 5% 3 49.9K 1/20W LT3957 SNS2 1% MF 201 2 TBTBST_INTVCC 28 INTVCC QFN 1/16W MF-LF 1 C3095 1 C3097 MIN_LINE_WIDTH=0.2 mm 402 1 10UF 10UF MIN_NECK_WIDTH=0.2 mm 20% 20% TBTBST_PWREN_L 25V 25V 2 X5R-CERM 2 X5R-CERM 30 VC 1 TBTBST_VSNS_RC 0603 0603 TBTBST_VC 2 MIN_LINE_WIDTH=0.2 mm Q3005 D 3 MIN_NECK_WIDTH=0.2 mm NC 10 NC R30951 C3096 1 C3098 1 DMN32D2LFB4 C3081 1 C3092 1 1 C3087 R3093 1 TBTBST_RT 33 RT 35 1 C3088 133K 10UF 10UF DFN1006H4-3 2.2UF 2.2UF 47PF 10K 22PF 1% 20% 25V 20% 25V SYM_VER_2 20% 20% 5% 1% 36 5% 1/16W 10V 10V 25V 2 50V X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 2 NP0-C0G-CERM 1/20W CERM MF-LF 0603 0603 402 402 0201 MF 32 SS 0402 402 2 201 2 TBTBST_SS 1 G S 2 <Ra> TBTBST_VC_RC FBX 31 TBTBST_FBX 28 25 IN TBT_A_HV_EN 34 SYNC SGND shorted to MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm GND inside package, 1 R3092 1 C3082 1 C3093 R30941 1 C3094 no XW necessary. NO STUFF R30961 1 C3084 1 C309A 1 C3099 73.2K 41.2K 1 C3089 15.8K 10UF 10UF 0.001UF 1% 2.2UF 3300PF 1% 0.33UF SGND GND 1% 20% 20% 10% 1/20W 20% 10V 10% 1/20W 10% 100PF 1/16W 2 25V 2 25V 50V 2 X7R-CERM 10V 6.3V 5% X5R-CERM X5R-CERM 23 24 37 12 13 14 15 16 17 MF 2 X5R-CERM 2 X7R-CERM MF 2 CERM-X5R 50V MF-LF 0603 0603 0402 4 2 201 402 0201 201 2 402 2 CERM 402 2 <R2> GND_TBTBST_SGND 402 <Rb> C3085 1 C309B 1 MIN_LINE_WIDTH=0.5 mm 10UF 10UF UVLO(falling) = 1.22 * (R1 + R2) / R2 MIN_NECK_WIDTH=0.25 mm 20% 20% VOLTAGE=0V 25V 25V UVLO(rising) = UVLO(falling) + (2uA * R1) X5R-CERM 2 X5R-CERM 2 UVLO = 4.55V (falling), 4.95 (rising) Vout = 1.6V * (1 + Ra / Rb) 0603 0603 C Supervisor & CLKREQ# Isolation C 74 65 64 62 61 59 56 30 27 18 17 15 13 12 11 8 PP3V3_S0 D 45 44 43 42 41 40 39 38 36 PP3V3_TBTLC 15 17 25 26 27 62 64 6 Q3088 DMN5L06VK-7 1 R3088 SOT-563 1 1 330K R3040 CRITICAL R3007 1 5% 1/20W 10K VDD 100K MF 5% 5% 1 S G 2 Max Vgs: 10V 2 201 Q3040 1/20W MF U3000 1/20W MF TBTBST_SHDN_DIV G 1 DMN32D2LFB4 2 201 SLG4AP016V 2 201 DFN1006H4-3 SYM_VER_3 TDFN PP1V05_TBTLC 26 27 62 64 1 + SENSE 2 R3087 D C3000 1 - 0.7V 3 Q3088 D S 25 IN TBT_EN_LC_PWR 0.1UF 330K DMN5L06VK-7 5% 3 2 10% 1/20W SOT-563 16V X5R-CERM 2 DLY MF 0201 2 201 RESET* 4 TBT_PCIE_RESET_L OUT 25 18 15 IN PCH_TBT_PCIE_RESET_L 3 MR* 4 S G 5 DLY = 60 ms +/- 20% Platform (PCIe) Reset SMC_DELAYED_PWRGD IN 17 37 38 6 EN TBT_CLKREQ_ISOL_L IN 25 27 12 OUT TBT_CLKREQ_L 8 OUT (OD) IN 7 TBT_CLKREQ_ISOL_L 25 27 MAKE_BASE=TRUE Pull-up provided by SB page. GND THRM PAD 5 9 TBT_EN_LC_ISOL TBT "POC" Power-up Reset R3011 62 28 26 25 PP3V3_S4_TBTAPWR 36.5K1 B 2 TBT_EN_LC_RC3V3 B 1% 1/20W 3.3V TBT "LC" Switch CRITICAL 1 MF 201 U3010 VDD Pull-up: R2810 PP3V3_S0 62 64 65 74 65 64 62 61 59 56 45 44 27 18 17 15 13 12 11 8 PP3V3_S0 TPS22924 PP3V3_TBTLC 15 17 25 26 27 62 64 8 11 12 13 15 17 18 27 30 36 38 39 40 41 42 43 44 45 56 59 61 43 42 41 40 39 38 36 30 A2 CSP A1 2 SENSE U3030RESET* 6 TBT_PWR_ON_POC_RST_L OUT 25 74 Max Current = 2A (85C) 1 B2 VIN VOUT B1 TPS3808 (IPU) 4 R3030 U3010 TBTPOCRST_CT 3 CT QFN MR* TBTPOCRST_MR_L Q3025 100K G 5 CRITICAL THRM DMN5L06VK-7 5% GND 1/20W C3010 1 C2 ON Part TPS22924C 1 C3031 C3030 1 PAD SOT-563 MF 1.0UF GND 2 201 5 7 20% 0.0047UF 0.1UF TPS3808G25 D S 6.3V 2 TBT_POC_RESET_L C1 Type Load Switch 10% 10% 15 X5R 25V 16V IN 2 CERM X5R-CERM 2 Vt = 2.33V +/- 2% 3 4 0201-1 R(on) 18.5 mOhm Typ 0402 0201 Delay = 27.3ms @ 2.5V 25.8 mOhm Max C3025 1 330PF C3011 1 10% 16V 1.0UF X7R-CERM 2 20% 0201 6.3V X5R 2 0201-1 R3016 0 1 2 TBT_EN_LC_RC1V05 5% 1/20W MF 1.05V TBT "LC" Switch 51 42 38 27 17 16 15 11 8 6 64 62 59 58 55 PP1V05_S0 1.05V TBT "CIO" Switch 0201 PP3V3_TBTLC U3015 64 62 27 26 25 17 15 U3020 51 42 38 27 17 16 15 11 8 6 PP1V05_S0 TPS22920 PP1V05_TBTLC 26 27 62 64 TPS22920 PP1V05_TBTCIO 26 62 64 64 62 59 58 55 A2 CSP A1 Max Current = 4A (85C) R30201 A2 CSP A1 Max Current = 4A (85C) B2 B1 100K B2 B1 VIN VOUT 5% VIN VOUT A C2 C1 U3015 1/20W MF 201 2 C2 C1 U3020 SYNC_MASTER=J41_MLB SYNC_DATE=02/06/2013 A CRITICAL CRITICAL PAGE TITLE Part TPS22920 Part TPS22920 C3015 1 D2 ON TBT_EN_CIO_PWR D2 ON TBT Power Support 1.0UF GND Type Load Switch GND Type Load Switch 20% DRAWING NUMBER SIZE C3020 D1 D1 6.3V 2 1 X5R 0201-1 R(on) 6.1 mOhm Typ Q3025 D 6 1.0UF R(on) 6.1 mOhm Typ Apple Inc. <SCH_NUM> D @ 1.05V 10.4 mOhm Max DMN5L06VK-7 20% 6.3V 2 @ 1.05V 10.4 mOhm Max REVISION SOT-563 R NO STUFF X5R 0201-1 <E4LABEL> C3016 1 NOTICE OF PROPRIETARY PROPERTY: BRANCH 1.0UF 2 G S 1 THE INFORMATION CONTAINED HEREIN IS THE <BRANCH> 20% PROPRIETARY PROPERTY OF APPLE INC. 6.3V X5R 2 TBT_EN_CIO_PWR_L THE POSESSOR AGREES TO THE FOLLOWING: PAGE 0201-1 25 13 IN I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 30 OF 121 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 27 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 3.3V/HV Power MUX V3P3 must be S4 to support wake from Thunderbolt device attach. 62 28 27 26 25 PP3V3_S4_TBTAPWR 34 29 18 17 16 15 13 11 8 PP3V3_S5 74 64 62 60 59 58 57 42 Nominal Min Max IV3P3 1100mA 1030mA 1200mA CRITICAL C3280 1 C3281 IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum) C3220 1 C3287 1 1 0.1UF 3 100UF 22UF 0.1UF IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W) 10% SIGNAL_MODEL=TBT_MUX 20% 20% 10% 16V 6.3V 6.3V 16V X5R-CERM 2 VDD POLY-TANT 2 X5R-CERM-1 2 2 X5R-CERM PP3V3_S4_TBTAPWR 25 26 27 28 62 GND_VOID=TRUE 0201 CRITICAL D CASE-B2-SM 603 0201 19 V3P3OUT 18 MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V (Both C’s) U3220 CBTL05024 D PP15V_TBT 20 V3P3 12 PP3V3RHV_S4_TBTAPWR TBT_A_D2R_N<1> C3277 1 2 HVQFN24-COMBO 64 62 27 71 25 OUT 20% 4V 201 7 TB- 15 OUT MIN_LINE_WIDTH=0.38 MM 0.47UF CERM-X5R-1 71 TBT_A_D2R_C_N<1> TB_ENA TBT_A_CIO_SEL IN 25 18.9V Max 6 14 MIN_NECK_WIDTH=0.20 MM TBT_A_D2R_P<1> 7 VHV VOLTAGE=15V 71 25 OUT C3276 1 2 20% 4V 201 71 TBT_A_D2R_C_P<1> 8 TB+ AUXIO_EN 24 DP_AUXCH_ISOL_L IN 13 C3215 1 1 C3210 CRITICAL C3285 1 1 C3286 1 C3211 0.47UF CERM-X5R-1 DP_PD 6 TBT_A_DP_PWRDN IN 25 4.7UF 0.1UF U3210 0.1UF 10% 10UF 20% 0.1UF 10% 71 25 DP_TBTPA_AUXCH_C_N C3230 1 2 10% 16V 71 DP_TBTPA_AUXCH_N 1 AUX- 16V BI 10% 25V 10% CD3211A0RGPR X5R-CERM 2 2 6.3V 2 25V 0.1UF X5R-CERM 71 DP_TBTPA_AUXCH_P 2 AUX+ (IPU) AUXIO- 23 TBT_A_D2R1_AUXDDC_N 28 71 X5R-CERM 2 2 25V CERM-X5R X5R DP_TBTPA_AUXCH_C_P 0201 0603 X5R 402 QFN 0201 0402-1 402 71 25 BI C3231 1 2 10% 16V (IPD) AUXIO+ 22 TBT_A_D2R1_AUXDDC_P 28 71 16 ENHVU FAULTZ 4 0.1UF X5R-CERM 18 13 DP_TBTSNK0_DDC_DATA 4 DDC_DAT TBT: RX_1 BI 0201 5 18 13 IN DP_TBTSNK0_DDC_CLK DDC_CLK 59 58 18 IN S4_PWR_EN 5 EN ISET_V3P3 8 TBTAPWRSW_ISET_V3P3 27 25 TBT_A_HV_EN 11 HV_EN ISET_S0 10 TBTAPWRSW_ISET_S0 25 TBT_A_CONFIG1_BUF 16 CA_DETOUT CA_DET 18 TBT_A_CONFIG1_RC 28 IN OUT 59 57 IN PM_SLP_S3_BUF_L 17 S0 ISET_S3 9 TBTAPWRSW_ISET_S3 71 25 DP_TBTPA_ML_C_P<1> C3232 1 2 20% 6.3V 71 DP_TBTPA_ML_P<1> 11 DP+ IN 0.22UF GND THRM TBTHV:P15V TBTHV:P15V DP_TBTPA_ML_C_N<1> X5R 0201 DP_TBTPA_ML_N<1> 10 DP- PAD 12V: See R3210 1 1 R3211 1 R3212 71 25 IN C3233 1 2 20% 6.3V 71 DPMLO+ 19 DP_A_LSX_ML_P<1> 28 71 0.22UF DPMLO- 20 DP_A_LSX_ML_N<1> 1 2 3 13 15 21 22.6K 22.6K 36.5K X5R 0201 TBT_A_LSTX 14 LSTX (IPU) 28 71 below 1% 1% 1% 25 IN 1/20W 1/20W 1/20W TBT_A_LSRX 13 LSRX (IPD) TBT: LSX_A_R2P/P2R (P/N) MF MF MF 25 OUT 201 2 2 201 2 201 TBTAPWRSW_ISET_S3_R <RV3P3> 25 DP_TBTPA_HPD 12 HPDOUT HPD 17 TBT_A_HPD 28 TBTAPWRSW_ISET_S0_R OUT TBTHV:P15V TBTHV:P15V GND THMPAD Single-fault protection R32131 1 R3214 9 21 25 requires two R’s per HV 22.6K 22.6K 1% 1% ISET_Sx with CD3210. 1/20W 1/20W MF MF Single R on ISET_V3P3 OK. 201 2 2 201 <RHVS3> <RHVS0> ILIM = 40000 / RISET C For 12V systems: C PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 118S0145 2 RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF R3210,R3213 TBTHV:P12V 118S0145 2 RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF R3211,R3214 TBTHV:P12V Nominal Min Max CRITICAL L3200 Thunderbolt Connector A IHVS0/S3 1120mA 1090mA 1170mA (12W minimum) FERR-120-OHM-3A 1 2 PP3V3RHV_S4_TBTAPWR_F 0603 MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=15V TBTACONN_1_C C3200 1 R3201 MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM GND_VOID=TRUE 0.01UF 12 VOLTAGE=18.9V 10% 50V TBTACONN_20_RC 1 2 (0-18.9V) C3205 1 X7R-CERM 2 MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM 5% 0.01UF 0402 VOLTAGE=18V 1/20W 10% 1 C3201 MF 201 25V X5R-CERM 2 GND_VOID=TRUE 0.01UF 0201 GND_VOID=TRUE 10% (Both C’s) 50V 2 X7R-CERM (Both C’s) 0402 TBT Dir DP Dir DP Dir TBT Dir C3270 1 2 20% 6.3V TBT_A_R2D_C_P<0> TBT_A_D2R_P<0> C3274 1 2 TBT_A_D2R_C_P<0> 71 TBT_A_R2D_P<0> 0.22UF X5R 0201 TBT_A_R2D_C_N<0> IN 25 71 71 25 OUT TBT_A_D2R_N<0> 0.47UF 20% 4V 201 CERM-X5R-1 71 TBT_A_D2R_C_N<0> J3200 71 TBT_A_R2D_N<0> C3271 1 2 IN 25 71 71 25 OUT C3275 1 2 71 MDP-J11 TBT: TX_0 0.22UF 20% X5R 6.3V 0201 20% 4V 201 GND_VOID=TRUE GND_VOID=TRUE F-RT-TH 0.47UF CERM-X5R-1 1 1 TBT: RX_0 TBTACONN_7_C R3294 R3295 CRITICAL MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM GND_VOID=TRUE 1 GND_VOID=TRUE 1 GND_VOID=TRUE 1K 1K VOLTAGE=18.9V R3270 R3271 5% 1/20W 5% 1/20W 514-0818 (0-18.9V) C3206 1 470K 470K MF MF 2 1 0.01UF 5% 5% 201 2 HOT_PLUG_DETECT GND 10% 2 201 4 3 25V 1/20W 1/20W NO_XNET_CONNECTION=TRUE NO_XNET_CONNECTION=TRUE CONFIG1 ML_LANE0P X5R-CERM 2 MF MF 6 5 0201 2 201 2 201 CONFIG2 B C3278 1 2 13 GND ML_LANE0N GND 7 B 71 25 IN DP_TBTPA_ML_C_P<3> 20% 6.3V 71 DP_TBTPA_ML_P<3> 10 ML_LANE3P ML_LANE1P 9 DP_A_LSX_ML_P<1> 28 71 0.22UF X5R 0201 DP_TBTPA_ML_C_N<3> DP_TBTPA_ML_N<3> 12 11 DP_A_LSX_ML_N<1> 71 25 IN C3279 1 2 20% 6.3V 71 14 ML_LANE3N ML_LANE1N 8 28 71 0.22UF X5R 0201 TBT: Unused GND GND TBT: LSX_R2P/P2R (P/N) 16 AUX_CHP 15 ML_LANE2P R32791 1 R3278 18 20 AUX_CHN ML_LANE2N 17 19 470K 470K DP_PWR RETURN 5% 5% 1/20W 1/20W GND_VOID=TRUE MF MF 201 2 2 201 SHIELD PINS (Both C’s) C3272 1 2 20% 6.3V TBT_A_R2D_C_P<1> 28 27 26 25 24 23 22 21 IN 25 71 0.22UF X5R 0201 71 TBT_A_R2D_P<1> TBT_A_R2D_C_N<1> 71 TBT_A_R2D_N<1> C3273 1 2 20% 6.3V IN 25 71 0.22UF X5R 0201 TBT_A_D2R1_AUXDDC_P TBT: TX_1 71 28 GND_VOID=TRUE GND_VOID=TRUE TBT_A_D2R1_AUXDDC_N 1 1 71 28 R3272 R3273 470K 470K TBT: RX_1 5% 5% 1/20W 1/20W 28 TBT_A_HPD MF MF 2 201 2 201 TBT_A_CONFIG1_RC DP Source must pull 28 1 C3202 down HPD input with 25 OUT TBT_A_CONFIG2_RC 0.01UF 10% greater than or equal 470k R’s for ESD protection 16V 2 X5R-CERM 0201 to 100K (DPv1.1a). on AC-coupled signals. R32521 1 R3251 C3294 1 1 C3295 1 R3241 1M 1M 330PF 330PF 100K 5% 5% 10% 10% 5% Sink HPD range: 1/20W 1/20W 16V 16V 1/20W MF MF X7R-CERM 2 2 X7R-CERM MF High: 2.0 - 5.0V A 201 2 2 201 0201 0201 2 201 Low: 0 - 0.8V SYNC_MASTER=J41_MLB SYNC_DATE=02/07/2013 A PAGE TITLE Thunderbolt Connector A DRAWING NUMBER SIZE Apple Inc. <SCH_NUM> D REVISION R <E4LABEL> NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. <BRANCH> THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 32 OF 121 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 28 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 3.3V WLAN Switch Part TPS22924C D Type Load Switch D R(on) 18.5 mOhm Typ @ 2.5V 25.8 mOhm Max Sense resistor on sensor page U3550 TPS22924 PP3V3_S5 8 11 13 15 16 17 18 28 29 34 42 CSP 57 58 59 60 62 64 74 PP3V3_WLAN 37 38 39 41 64 41 PP3V3_WLAN_R A1 A2 MIN_LINE_WIDTH=0.5 mm MIN_LINE_WIDTH=0.5 mm B1 VOUT VIN B2 MIN_NECK_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V VOLTAGE=3.3V 1 C3521 CRITICAL 0.1UF Max Current = 2A (85C) ON C2 SMC_WIFI_PWR_EN IN 29 37 39 10% 2 6.3V CERM-X5R GND 514S0335 0201 C3550 C1 1 CRITICAL BYPASS=J3501:5mm 1.0UF J3501 20% 6.3V SSD-K99 2 X5R F-RT-SM1 1 AIRPORT 0201-1 2 WIFI_EVENT_L 37 38 64 OUT 3 4 69 64 PCIE_AP_R2D_N C3531 1 2 10% 16V PCIE_AP_R2D_C_N IN 14 69 5 0.1UF X5R-CERM 0201 6 69 64 PCIE_AP_R2D_P C3530 1 2 10% 16V PCIE_AP_R2D_C_P IN 14 69 7 0.1UF X5R-CERM 0201 PCIE_CLK100M_AP_N IN 12 64 69 8 PCIE_CLK100M_AP_P 12 64 69 IN 9 10 PCIE_AP_D2R_P 14 64 69 OUT C 11 12 PCIE_AP_D2R_N OUT 14 64 69 C Supervisor & CLKREQ# Isolation 13 14 Delay = 130 ms +/- 20% 15 PP3V3_S5 8 11 13 15 16 17 18 28 29 34 42 57 58 59 60 62 64 74 16 17 PP3V3_S4 29 33 36 38 39 58 62 64 APCLKRQ:ISOL 18 1 C3540 1 R35531 1 R3554 VDD 0.1UF 10% 100K 232K 19 1 C3532 5% 1/20W 1% 1/20W U3540 2 6.3V CERM-X5R 20 0.1UF MF MF 0201 21 10% 6.3V 201 2 2 201 SLG4AP041V 2 CERM-X5R TDFN 0201 CRITICAL P3V3WLAN_VMON 2 SENSE + BYPASS=J3501:1.5mm VREF - R3558 DLY AP_RESET_CONN_L 1 0 2 AP_RESET_CONN_R_L 4 RESET* 64 MR* 3 AP_RESET_L IN 15 5% 1/20W MF 0201 EN 6 SMC_WIFI_PWR_EN IN 29 37 39 OUT 8 AP_CLKREQ_R_L 64 AP_CLKREQ_Q_L 7 IN (OD) THRM PAD GND APCLKRQ:ISOL 1 1 R3555 R3556 9 5 100K 0 1% 5% B PCIe Wake Muxing 1/20W MF 2 201 APCLKRQ:BIDIR 1/20W MF 2 0201 B 60 29 13 59 28 11 58 18 8 PP3V3_S5 R3557 17 16 15 0 57 74 42 64 34 62 SEL OUTPUT 2 1 AP_CLKREQ_L BI 12 5% L PCIE_WAKE_L (B0) 1/20W 1 R3561 C3560 1 5 H AP_S0IX_WAKE_L (B1) MF 0201 100K 0.1UF VCC 5% 10% 6.3V 1/20W MF CERM-X5R 2 CRITICAL NOSTUFF 2 201 0201 U3560 S 6 AP_S0IX_WAKE_SEL IN 15 R3559 NC7SB3157P6XG 0 SC70 2 1 VER-3 B0 3 PCIE_WAKE_L OUT 13 31 64 5% AP_PCIE_WAKE_L 4 A B1 1 AP_S0IX_WAKE_L OUT 15 1/20W MF GND 0201 2 NOSTUFF R3560 0 BLUETOOTH 1 2 58 39 38 36 33 29 PP3V3_S4 64 62 5% 1/20W MF 0201 1 C3510 5 0.1UF SMC_PME_S4_WAKE_L OUT 36 37 39 VDD 10% NO_XNET_CONNECTION=TRUE U3510 2 6.3V CERM-X5R USB3740 0201 Q3510 D 3 DFN USB_BT_P DMN32D2LFB4 DP_2 6 BI 14 68 DFN1006H4-3 CRITICAL SYM_VER_2 DM_2 7 USB_BT_N A 68 64 USB_BT_CONN_P 10 DP DP_1 2 BI 14 68 1 G S 2 SYNC_MASTER=J41_MLB SYNC_DATE=02/06/2013 A 68 64 USB_BT_CONN_N 9 DM NC PAGE TITLE DM_1 1 BT_WAKE Wireless Connector 3 DRAWING NUMBER SIZE OE* 1 R3512 Apple Inc. <SCH_NUM> D S 4 PM_SLP_S4_L IN 13 18 36 37 59 15K REVISION SIGNAL_MODEL=BT_MUX 1% R GND SEL OUTPUT 1/20W MF <E4LABEL> 8 2 201 NOTICE OF PROPRIETARY PROPERTY: BRANCH L BT_WAKE (1) THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. <BRANCH> H USB_BT (2) THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 35 OF 121 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 29 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 D OOB Isolation D 64 62 41 30 PP3V3_S0SW_SSD BYPASS=U3710:5 mm 1 C3718 0.1UF 10% 10V 2 X5R-CERM PLACE_NEAR=J3700.1:3mm 0201 CRITICAL CRITICAL L3700 74LVC1G08 6 FERR-26-OHM-6A SOT891 2 SMC_OOB1_R2D_L 37 IN PP3V3_S0SW_SSD 1 2 PP3V3_S0SW_SSD_FLT 4 64 62 41 30 64 MIN_LINE_WIDTH=0.6mm U3710 0603 MIN_NECK_WIDTH=0.15mm 08 1 VOLTAGE=3.3V 74 65 64 62 61 PP3V3_S0 NC 1 C3701 1 C3702 36 30 27 18 17 15 13 12 11 8 59 56 45 44 43 42 41 40 39 38 3 5 0.1UF 0.1UF 10% 10% 10V 2 X5R-CERM 10V 2 X5R-CERM 514S0449 R37101 R37001 NC 0201 0201 100K 100K CRITICAL 5% 1% PLACE_NEAR=L3700.1:1mm PLACE_NEAR=L3700.1:1mm 1/20W 1/20W J3700 MF 201 2 MF 201 2 61 59 56 45 44 43 42 18 17 15 13 12 11 8 PP3V3_S0 SSD-GS3 41 40 39 38 36 30 27 74 65 64 62 GND_VOID F-RT-SM GND_VOID 1 53 BYPASS=U3711:5 mm 2 52 64 SMC_OOB1_R2D_CONN_L C3719 1 0.1UF 3 51 64 SMC_OOB1_D2R_CONN_L 10% 10V 4 X5R-CERM 2 0201 5 50 SSD_PCIE_SEL_L CRITICAL OUT 16 64 6 49 SSD_DEVSLP IN 15 64 6 74LVC1G08 74 65 64 62 61 PP3V3_S0 7 48 SMC_PWRFAIL_WARN_L 2 SOT891 C 36 30 27 18 17 15 13 12 11 8 59 56 45 44 43 42 41 40 39 38 64 SSD_RESET_CONN_L 8 47 SSD_PWR_EN IN 37 IN 15 30 58 59 64 U3711 4 SMC_OOB1_D2R_L OUT 37 C NC_SSD_MFG_RSVD 9 1 08 SMC_PWRFAIL_WARN_L Signal has PU on SSD module 67 12 IN PCIE_SSD_R2D_C_N<3> C3710 1 2 GND_VOID=TRUE 10% 16V X5R-CERM 0201 10 46 NC 5 3 0.1UF 67 64 PCIE_SSD_R2D_N<3> TRUE 11 45 TRUE PCIE_SSD_D2R_N<3> OUT 12 64 67 67 12 IN PCIE_SSD_R2D_C_P<3> C3711 1 2 GND_VOID=TRUE 10% 16V X5R-CERM 0201 67 64 PCIE_SSD_R2D_P<3> TRUE 12 44 TRUE PCIE_SSD_D2R_P<3> OUT 12 64 67 NC 0.1UF 13 43 67 12 IN PCIE_SSD_R2D_C_N<2> C3712 1 2 GND_VOID=TRUE 10% 16V X5R-CERM 0201 67 64 PCIE_SSD_R2D_N<2> TRUE 14 42 TRUE PCIE_SSD_D2R_N<2> OUT 12 64 67 0.1UF 67 64 PCIE_SSD_R2D_P<2> TRUE 15 41 TRUE PCIE_SSD_D2R_P<2> OUT 12 64 67 67 12 IN PCIE_SSD_R2D_C_P<2> C3713 1 2 GND_VOID=TRUE 10% 16V X5R-CERM 0201 16 40 0.1UF 67 12 IN PCIE_SSD_R2D_C_N<1> C3714 1 2 GND_VOID=TRUE 10% 16V X5R-CERM 0201 17 39 0.1UF 67 64 PCIE_SSD_R2D_N<1> TRUE 18 38 TRUE PCIE_SSD_D2R_N<1> 12 64 67 OUT 67 12 IN PCIE_SSD_R2D_C_P<1> C3715 1 2 GND_VOID=TRUE 10% 16V X5R-CERM 0201 67 64 PCIE_SSD_R2D_P<1> TRUE 19 37 TRUE PCIE_SSD_D2R_P<1> OUT 12 64 67 0.1UF 20 36 67 12 IN PCIE_SSD_R2D_C_N<0> C3716 1 2 GND_VOID=TRUE 10% 16V X5R-CERM 0201 67 64 PCIE_SSD_R2D_N<0> TRUE 21 35 TRUE PCIE_SSD_D2R_N<0> OUT 12 64 67 0.1UF 67 64 PCIE_SSD_R2D_P<0> TRUE 22 34 TRUE PCIE_SSD_D2R_P<0> 12 64 67 OUT 67 12 IN PCIE_SSD_R2D_C_P<0> C3717 1 2 GND_VOID=TRUE 23 33 10% 16V X5R-CERM 0201 24 0.1UF 64 SSD_CLKREQ_CONN_L 25 32 26 31 PCIE_CLK100M_SSD_N 12 64 67 IN Per Intel PDG, use PCIe style decoupling, when muxing PCIe & SATA 27 30 PCIE_CLK100M_SSD_P 12 64 67 IN 28 29 54 59 55 60 PCIe polarity inversion and lane reversal B Supervisor & CLKREQ# Isolation 56 57 61 are only permitted on the device side, provided the device PHY supports it. B 62 Delay = ~55ms 58 63 PP3V42_G3H 17 35 36 37 38 40 46 49 50 59 PP3V3_S0SW_SSD 30 41 62 64 61 62 64 65 CRITICAL 1 C3740 1 R37401 1 R3741 VDD 0.1UF 100K 5% 1/20W 232K 1% 1/20W U3740 10% 2 6.3V CERM-X5R 0201 Gumstick3 Connector MF MF SLG4AP016V 201 2 2 201 TDFN P3V3SSD_VMON 2 SENSE + 0.7V - DLY 4 RESET* MR* 3 SSD_RESET_L IN 15 EN 6 SSD_PWR_EN IN 15 30 58 59 64 7 IN OUT 8 SSD_CLKREQ_L OUT 12 (OD) THRM 1 PAD GND R3742 9 5 100K 1% 1/20W MF 2 201 A SYNC_MASTER=J41_MLB SYNC_DATE=04/09/2013 A PAGE TITLE SSD Connector DRAWING NUMBER SIZE Apple Inc. <SCH_NUM> D REVISION R <E4LABEL> NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. <BRANCH> THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 37 OF 121 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 30 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 PP1V8_CAM 31 32 L3902 NOSTUFF NOSTUFF 1.0UH-1.6A-55MOHM 1 1NOSTUFF 1 BYPASS=U3900.K13:2.54MM R3930 R3932 R3934 72 32 31 PP1V35_CAM 1 2 P1V35_CAM_SRVLXD_PHASE 31 100K 100K 100K MIN_LINE_WIDTH=0.6MM 1008 5% 5% 5% MIN_NECK_WIDTH=0.2MM 1/20W 1/20W 1/20W VOLTAGE=1.35V L3906 1 C3921 1 C3922 1 C3923 1 C3924 1 C3912 1 C3913 PLACE_NEAR=U3900.K13:4MM MF MF MF 1.0UF 0.1UF 1.0UF 0.1UF 4.7UF 4.7UF 2 201 2 201 2 201 22NH 20% 10% 20% 10% 20% 20% 6.3V 2 X5R 2 6.3V 2 6.3V 2 6.3V 6.3V 2 X5R 6.3V 2 X5R CAM_RAMCFG2 31 PP1V35_DDR_CLK 1 2 CERM-X5R X5R CERM-X5R 32 31 PP1V8_CAM MIN_LINE_WIDTH=0.6MM 0201-1 0201 0201-1 0201 402 402 CAM_RAMCFG1 31 MIN_NECK_WIDTH=0.2MM 0402 VOLTAGE=1.35V CAM_RAMCFG0 U3900 1 C3900 1 R3920 1R3921 31 BCM15700 0.1UF 31 GND_CAM_PVSSD 100K 100K 10% 1 1 1 5% 5% R3931 R3933 R3935 D N7 FBGA SYM 3 OF 3 2 6.3V CERM-X5R 0201 1/20W MF 2 201 1/20W MF 2 201 5% 330K 330K 5% 330K 5% D N8 CRITICAL A4 L3903 1/20W MF 1/20W MF 1/20W MF MIPI_AGND 220-OHM-1.4A N6 D4 I2C_CAM_SMBDBG_CLK 31 2 201 2 201 2 201 OMIT_TABLE 1 2 PP1V2_CAM_XTALPCIEVDD DDR_VDDIO G4 PP0V675_CAM_VREF MIN_LINE_WIDTH=0.6MM 32 72 0603 17 31 I2C_CAM_SMBDBG_DAT 31 L3901 C10 K4 MIN_NECK_WIDTH=0.2MM 1 C3930 1 C3931 1.0UH-1.6A-55MOHM VOLTAGE=0.675V 1.0UF 10UF C7 PCIE_GND N4 1 C3927 20% 20% 31 PP1V2_CAM 1 2 P1V2_CAM_SRVLXC_PHASE 31 0.1UF 6.3V 2 X5R 6.3V 2 CERM-X5R 1008 G14 DDR_VDDIO_CK G5 10% 2 6.3V 0201-1 0402-1 1 C3970 1 C3971 1 C3972 1 C3973 1 C3974 1 C3975 1 C3914 1 C3915 PLACE_NEAR=U3900.M13:4MM CERM-X5R 0.1UF 1000PF 0.1UF 1000PF 0.1UF 0.1UF 4.7UF 4.7UF M12 PMU_AVSS 0201 L3904 10% 2 6.3V 10% 16V 2 X7R-CERM 10% 2 6.3V 10% 2 16V 10% 2 6.3V 10% 2 6.3V 20% 6.3V 20% 6.3V DDR_VREF_O N5 220-OHM-1.4A CERM-X5R CERM-X5R X7R-CERM CERM-X5R CERM-X5R 2 X5R 2 X5R 0201 0201 0201 0201 0201 0201 402 402 31 GND_CAM_PVSSC N13 1 2 PLACE_NEAR=U3900.M13:2.54MM P14 PCIE_VDD1P2 C8 PP1V2_CAM_PCIE_VDD_FLT 0603 P15 SR_PVSSC MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM 1 C3932 1 C3933 BYPASS=U3900.F6:2.54MM BYPASS=U3900.F9:2.54MM BYPASS=U3900.F6:2.54MM BYPASS=U3900.L9:2.54MM 31 GND_CAM_PVSSC VOLTAGE=1.2V 1.0UF 10UF BYPASS=U3900.F9:2.54MM BYPASS=U3900.L9:2.54MM R15 PCIE_PVDD1P2 D9 20% 20% 6.3V 2 X5R 6.3V 2 CERM-X5R PP1V2_CAM_PCIE_PVDD_FLT 0201-1 0402-1 GND_CAM_PVSSD K15 DDR_AVDD1P8 J1 MIN_LINE_WIDTH=0.6MM 31 L12 MIN_NECK_WIDTH=0.2MM VOLTAGE=1.2V U3900 L13 MIPI_AVDD1P8 L7 BCM15700 SR_PVSSD FBGA L14 PP1V8_CAM SYM 1 OF 3 L15 MIN_LINE_WIDTH=0.6MM 72 32 IN MIPI_CLK_P P7 MIPI_CP_CLK DEBUG_00 B11 TP_CAM_TEST_MODE0 PLL_VDD1P8 D6 MIN_NECK_WIDTH=0.2MM CRITICAL VOLTAGE=1.8V 1 C3919 1 C3918 1 C3916 1 C3917 1 C3910 1 C3951 72 32 IN MIPI_CLK_N R7 MIPI_CM_CLK OMIT_TABLE DEBUG_01 C14 TP_CAM_TEST_MODE1 (=PP3V3_S3RS0_CAMERA) BYPASS=U3900.D7:2.54MM 0.1UF 1000PF 0.1UF 1000PF 0.1UF 0.1UF DEBUG_02 B14 TP_CAM_TEST_MODE2 A1 OTP_VDD3P3 D7 10% 10% 10% 10% 10% 10% 6.3V 2 CERM-X5R 16V 2 X7R-CERM 2 6.3V 2 16V 2 6.3V 2 6.3V MIPI_DATA_P P8 MIPI_DP0 DEBUG_03 A15 TP_CAM_LV_JTAG_TCK A6 CERM-X5R X7R-CERM CERM-X5R CERM-X5R 72 32 IN B6 M14 1 C3938 0201 0201 0201 0201 0201 0201 72 32 IN MIPI_DATA_N R8 MIPI_DM0 DEBUG_04 E11 TP_CAM_LV_JTAG_TDI 1000PF DEBUG_05 E10 TP_CAM_LV_JTAG_TDO D1 M15 10% SR_VDD_3P3C 1 C3928 2 16V BYPASS=U3900.J1:2.54MM BYPASS=U3900.L7:2.54MM P6 MIPI_DP1 DEBUG_06 F11 TP_CAM_LV_JTAG_TMS D5 N15 X7R-CERM BYPASS=U3900.J1:2.54MM BYPASS=U3900.D6:2.54MM NC 4.7UF 0201 BYPASS=U3900.L7:2.54MM BYPASS=U3900.D6:2.54MM R6 MIPI_DM1 F10 TP_CAM_LV_JTAG_TRSTN C E5 G1 H14 20% 6.3V 2 X5R XW3900 NC DEBUG_07 DEBUG_08 G11 NC C 402 SM 69 32 PCIE_CAMERA_R2D_P B7 PCIE_RDP0 DEBUG_09 G10 G6 H15 IN NC G7 J13 GND_CAM_PVSSC 1 2 69 32 IN PCIE_CAMERA_R2D_N A7 PCIE_RDN0 DEBUG_10 H11 NC SR_VDD_3P3D MIN_LINE_WIDTH=0.6MM H10 G8 J14 MIN_NECK_WIDTH=0.2MM DEBUG_11 NC VOLTAGE=0V G9 J15 69 32 IN PCIE_CLK100M_CAMERA_C_P B10 PCIE_REFCLKP DEBUG_12 J10 NC H5 (=PP3V3_S3RS0_CAMERA) 69 32 IN PCIE_CLK100M_CAMERA_C_N A10 PCIE_REFCLKN DEBUG_13 K11 NC VSSC DEBUG_14 K10 H6 M13 P1V2_CAM_SRVLXC_PHASE 31 NC MIN_LINE_WIDTH=0.6MM PLACE_NEAR=U3900.M14:2.54MM PCIE_CAMERA_D2R_C_P A8 PCIE_TDP0 DEBUG_15 L11 PP1V8_CAM H7 SR_VLXC_O N14 MIN_NECK_WIDTH=0.2MM 1 C3926 69 32 OUT NC 32 31 DIDT=TRUE 4.7UF 69 32 OUT PCIE_CAMERA_D2R_C_N B8 PCIE_TDN0 DEBUG_16 L10 NC NOSTUFF H8 20% 32 31 PP1V8_CAM 1 H9 K13 P1V35_CAM_SRVLXD_PHASE 6.3V 2 X5R R3936 J5 SR_VLXD_O K14 MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM 31 402 XW3901 SM NC B9 PCIE_TESTP 5% 100K DIDT=TRUE C9 PCIE_TESTN 1/20W J6 GND_CAM_PVSSD 1 2 NC MF R12 CAM_RAMCFG0 J7 VDD_1P35A F14 PP1V35_CAM 31 32 72 MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM PP3V3_S3RS0_CAMERA 15 41 R39131 R39141 GPIO_00 31 201 2 J8 VOLTAGE=0V 1K 1K 69 32 OUT CLK25M_CAM_CLKP A13 XTAL_P GPIO_01 P12 CAM_RAMCFG1 31 5% 5% J9 1/20W 1/20W 69 32 IN CLK25M_CAM_CLKN A12 XTAL_N GPIO_02 P11 CAM_RAMCFG2 31 VDD_3P3A J11 MF MF P10 CAM_GPIO3 K1 201 2 201 2 GPIO_03 I2C_CAM_SMBDBG_CLK D15 I2C_CLK_DBG GPIO_04 P9 TP_CAM_PLL_BYPASS K5 VDD1P2_O F15 PP1V2_CAM_XTALPCIEVDD 1 C3942 1 C3940 1 C3934 1 C3935 1 C3936 1 C3937 31 I2C_CAM_SCK R10 I2C_CLK_SENSOR GPIO_05 N11 K6 4.7UF 0.1UF 1000PF 0.1UF 1000PF 0.1UF 64 32 OUT NC NOSTUFF 20% 10% 10% 10% 10% 10% I2C_CAM_SMBDBG_DAT C15 I2C_DATA_DBG GPIO_06 N10 K7 VDD1P8_O G15 PP1V8_CAM 6.3V 6.3V 16V 2 6.3V 2 16V 2 6.3V 31 NC 1 2 X5R 402 2 CERM-X5R 0201 2 X7R-CERM 0201 CERM-X5R 0201 X7R-CERM 0201 CERM-X5R 0201 64 32 BI I2C_CAM_SDA R9 I2C_DATA_SENSOR GPIO_07 N9 NC R3937 K8 100K K9 F6 1 C3941 BYPASS=U3900:7mm BYPASS=U3900:3mm BYPASS=U3900:3mm 5% 1/20W 2.2UF BYPASS=U3900:5mm BYPASS=U3900:5mm BYPASS=U3900:5mm NOSTUFF TP_CAM_JTAG_TCK F13 JTAG_TCK UARTCTS D13 CAM_UARTCTS 31 MF A14 F7 20% 201 2 6.3V TP_CAM_JTAG_TDI E12 TP_CAM_UARTRTS M9 F8 2 CERM R3991 JTAG_TDI UARTRTS D14 402-LF 0 TP_CAM_JTAG_TDO F12 JTAG_TDO N1 F9 1 C3939 64 29 13 OUT PCIE_WAKE_L 1 2 TP_CAM_JTAG_TMS D12 JTAG_TMS UARTRXD E13 CAM_UARTRXD P5 VDDC L6 1UF BYPASS=U3900.F15:2.54MM 5% 31 10% 1/20W TP_CAM_JTAG_TRST_L D11 JTAG_TRST* UARTTXD E14 TP_CAM_UARTTXD 2 10V B R1 R5 L5 L8 X5R 402 32 31 PP1V8_CAM MF 0201 31 CAM_JTAG_SRST_L C11 JTAG_SRST* B E9 BYPASS=U3900.G15:2.54MM TEST_OUT J12 CAM_TEST_OUT 31 L9 PP1V2_CAM 31 MIN_LINE_WIDTH=0.6MM 1 R3990 12 OUT CAMERA_CLKREQ_L P13 PCIE_CLKREQ* TEST_MODE M10 CAM_TEST_MODE 31 MIN_NECK_WIDTH=0.2MM B12 XTAL_AVSS VOLTAGE=1.2V 100K 18 IN CAM_PCIE_RESET_L R14 PCIE_RST* B15 5% STRAP_XTAL_FREQ C13 CAM_XTAL_FREQ U3900 1/20W MF CAM_PCIE_WAKE_L N12 PCIE_WAKE* 31 VDDO18 BCM15700 STRAP_XTAL_SEL C12 CAM_XTAL_SEL R11 2 201 31 FBGA CAM_PWR_SEL G12 DDR_PWR_SEL SYM 2 OF 3 72 32 OUT MEM_CAM_A<0> L3 DDR_AD00 DDR_DQ00 C2 MEM_CAM_DQ<0> BI 32 72 CAM_DEBUG_RESET_L E15 RESET* L3901:1 VSENSE_C M11 PP1V2_CAM 31 72 32 OUT MEM_CAM_A<1> M4 DDR_AD01 CRITICAL DDR_DQ01 E3 MEM_CAM_DQ<1> BI 32 72 R13 SENSOR_WAKE* L3902:1 VSENSE_D K12 PP1V35_CAM 31 32 72 NOSTUFF MEM_CAM_A<2> N3 DDR_AD02 OMIT_TABLE DDR_DQ02 E4 MEM_CAM_DQ<2> 1 R3901 H12 SHUTDOWN* 72 32 OUT MEM_CAM_A<3> M3 DDR_AD03 DDR_DQ03 D3 MEM_CAM_DQ<3> BI 32 72 1 C3990 100K XTAL_AVDD1P2 B13 PP1V2_CAM_XTALPCIEVDD 17 31 72 32 OUT BI 32 72 0.1UF 5% PD = 1.35V MIN_LINE_WIDTH=0.6MM 72 32 MEM_CAM_A<4> M1 DDR_AD04 DDR_DQ04 F3 MEM_CAM_DQ<4> 32 72 10% 1/20W MIN_NECK_WIDTH=0.2MM OUT BI 6.3V 2 CERM-X5R MF VOLTAGE=1.2V 72 32 OUT MEM_CAM_A<5> M2 DDR_AD05 DDR_DQ05 F1 MEM_CAM_DQ<5> BI 32 72 0201 2 201 MAKE_BASE=TRUE 32 31 PP1V8_CAM 72 32 OUT MEM_CAM_A<6> P4 DDR_AD06 DDR_DQ06 F4 MEM_CAM_DQ<6> BI 32 72 PP1V2_CAM_XTALPCIEVDD 17 31 CAM_A1 31 CAM_TEST_MODE 72 32 OUT MEM_CAM_A<7> N2 DDR_AD07 DDR_DQ07 F2 MEM_CAM_DQ<7> BI 32 72 1 72 32 OUT MEM_CAM_A<8> P3 DDR_AD08 DDR_DQ08 B5 MEM_CAM_DQ<8> BI 32 72 R3915 31 CAM_TEST_OUT 100K MEM_CAM_A<9> P2 DDR_AD09 DDR_DQ09 C3 MEM_CAM_DQ<9> 5% 1 C3960 72 32 OUT MEM_CAM_A<10> J4 DDR_AD10 DDR_DQ10 B1 MEM_CAM_DQ<10> BI 32 72 CAM_SENSOR_WAKE_L 1/20W MF NO STUFF 0.1UF 72 32 OUT BI 32 72 32 IN 1 1 10% 72 32 OUT MEM_CAM_A<11> R2 DDR_AD11 DDR_DQ11 B4 MEM_CAM_DQ<11> BI 32 72 18 IN CAMERA_PWR_EN 2 201 R3910 R3911 2 6.3V CERM-X5R 100K 100K 0201 72 32 OUT MEM_CAM_A<12> L1 DDR_AD12 DDR_DQ12 A5 MEM_CAM_DQ<12> BI 32 72 CAM_JTAG_SRST_L 31 5% 5% MEM_CAM_A<13> P1 C5 MEM_CAM_DQ<13> PU on PCH page 1/20W 1/20W 72 32 OUT DDR_AD13 DDR_DQ13 BI 32 72 MF MF PP1V8_CAM 31 32 A1 SILICON BUG 2 201 2 201 72 32 OUT MEM_CAM_A<14> R4 DDR_AD14 DDR_DQ14 B2 MEM_CAM_DQ<14> BI 32 72 DDR_DQ15 B3 MEM_CAM_DQ<15> BI 32 72 MEM_CAM_BA<0> K3 DDR_BA0 CAM_XTAL:YES 72 32 OUT 1 1 31 CAM_UARTCTS 72 32 OUT MEM_CAM_BA<1> L2 DDR_BA1 DDR_DQS_P0 E2 MEM_CAM_DQS_P<0> BI 32 72 R3904 R3906 MEM_CAM_BA<2> K2 DDR_BA2 MEM_CAM_DQS_N<0> 100K 100K DDR_DQS_N0 D2 A 31 CAM_UARTRXD 72 32 OUT BI 32 72 5% 1/20W MF 5% 1/20W MF SYNC_MASTER=J41_MLB SYNC_DATE=04/02/2013 A MEM_CAM_CLK_P H2 DDR_CK_P0 DDR_DQS_P1 A2 MEM_CAM_DQS_P<1> 2 201 2 201 PAGE TITLE 1 R3975 51K 5% 1 R3976 51K 5% 72 32 72 32 OUT OUT MEM_CAM_CLK_N G2 DDR_CK_N0 DDR_DQS_N1 A3 MEM_CAM_DQS_N<1> BI BI 32 72 32 72 31 CAM_XTAL_FREQ PU = 25MHz CAM_XTAL_SEL CAM_XTAL:NO 31 Camera 1 of 2 DRAWING NUMBER SIZE 1/20W 1/20W MF MF 72 32 OUT MEM_CAM_DM<0> C1 DDR_DM0 DDR_RAS* H3 MEM_CAM_RAS_L OUT 32 72 1 R3907 Apple Inc. <SCH_NUM> D 2 201 2 201 72 32 MEM_CAM_DM<1> C4 DDR_DM1 DDR_WE* J2 MEM_CAM_WE_L 32 72 100K REVISION OUT OUT R3912 DDR_CAS* H4 MEM_CAM_CAS_L OUT 32 72 5% 1/20W R <E4LABEL> 240 MEM_CAM_ZQ_S2 G3 DDR_ZQ R3 MEM_CAM_RESET_L MF 1 2 DDR_RESET* OUT 32 2 201 NOTICE OF PROPRIETARY PROPERTY: BRANCH 1% 1/20W 72 32 OUT MEM_CAM_CKE J3 DDR_CKE THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. <BRANCH> MF 72 32 OUT MEM_CAM_CS_L L4 DDR_CS* THE POSESSOR AGREES TO THE FOLLOWING: PAGE 201 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 39 OF 121 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 31 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 PP1V35_CAM 72 31 BYPASS=U4000.A1:4mm BYPASS=U4000.B2:4mm BYPASS=U4000.D2:4mm BYPASS=U4000.K2:4mm 69 14 IN PCIE_CAMERA_R2D_C_P C4033 1 2 PCIE_CAMERA_R2D_P OUT 10% 16V X5R-CERM 0201 31 69 0.1UF 1 C4002 1 C4003 1 C4004 1 C4005 1 C4006 1C4007 1 C4008 1C4009 PCIE_CAMERA_R2D_C_N C4032 1 2 PCIE_CAMERA_R2D_N OUT 10UF 10UF 0.47UF 0.1UF 2.2UF 0.1UF 2.2UF 0.1UF 69 14 IN 10% 16V X5R-CERM 0201 31 69 20% 20% 20% 10% 20% 10% 20% 10% 0.1UF 6.3V 2 CERM-X5R 6.3V 2 CERM-X5R 4V 6.3V 2 CERM-X5R-1 2 CERM-X5R 10V 2 X5R-CERM 2 6.3V 10V 2 X5R-CERM 2 6.3V CERM-X5R CERM-X5R 0402-1 0402-1 201 0201 402 0201 402 0201 69 31 IN PCIE_CAMERA_D2R_C_P C4031 1 2 PCIE_CAMERA_D2R_P OUT 14 69 R4000 BYPASS=U4000.H9:4mm BYPASS=U4000.R9:4mm 10% 16V X5R-CERM 0201 D 72 31 PP0V675_CAM_VREF 1 0 2 72 PP0V675_MEM_CAM_VREFDQ 69 31 IN PCIE_CAMERA_D2R_C_N C4030 0.1UF 1 2 PCIE_CAMERA_D2R_N OUT 14 69 D MIN_LINE_WIDTH=0.5 mm 10% 16V X5R-CERM 0201 0201 5% MF MIN_NECK_WIDTH=0.2 mm 0.1UF 1/20W VOLTAGE=0.675V R40221 72 PP0V675_MEM_CAM_VREFCA MIN_LINE_WIDTH=0.5 mm 69 12 IN PCIE_CLK100M_CAMERA_P C4061 1 2 PCIE_CLK100M_CAMERA_C_P 10% 16V X5R-CERM 0201 OUT 31 69 1K MIN_NECK_WIDTH=0.2 mm 0.1UF 1% VOLTAGE=0.675V 1/20W MF 69 12 IN PCIE_CLK100M_CAMERA_N C4062 1 2 PCIE_CLK100M_CAMERA_C_N 10% 16V X5R-CERM 0201 OUT 31 69 201 2 C4010 1 1 C4011 0.1UF 0.1UF 0.1UF 10% 6.3V 10% R4008 CERM-X5R 2 2 6.3V CERM-X5R CAM_XTAL:NO 0 R40231 SYSCLK_CLK25M_CAMERA 1 2 CLK25M_CAM_CLKP A1 A8 C1 C9 D2 E9 F1 H2 H9 B2 D9 G7 K2 K8 N1 N9 R1 R9 VREFCA M8 VREFDQ H1 0201 0201 69 17 IN IN 31 69 1K 0201 5% MF 1% 1/20W 1/20W MF R40021 VDDQ VDD C4015 CAM_XTAL:YES 201 2 1K R4007 R4009 5% MEM_CAM_A<0> N3 J1 12PF 1/20W 72 31 IN A0 U4000 NC CAM_XTAL:YES 1 2 CLK25M_CAM_XTALP 1 0 2 CLK25M_CAM_XTALP_R 1 0 2 MF 69 69 201 2 72 31 IN MEM_CAM_A<1> P7 A1 4GB-DDR3-256MX16 J9 NC MEM_CAM_A<2> P3 L1 5% 0201 5% NOSTUFF 5% CAM_XTAL:YES 72 31 IN A2 FBGA NC NC 25V CRITICAL 1/20W MF 1 1/20W MF 1 H5TC4G63AFR R4012 MEM_CAM_A<3> NC Y4000 N2 A3 L9 NP0-C0G-CERM 0201 NOSTUFF 72 31 IN NC 0201 1M 4 2 1 72 31 IN MEM_CAM_A<4> P8 A4 M7 NC NC SM-3.2X2.5MM 1% R4003 MEM_CAM_A<5> P2 A5 CRITICAL C4014 25.000MHZ-12PF-20PPM 1/20W MF 3 72 31 IN 1K MEM_CAM_A<6> 2 201 R4010 5% 72 31 IN R8 A6 DQL0 E3 MEM_CAM_DQ<0> BI 31 72 12PF CAM_XTAL:YES 1/20W MEM_CAM_A<7> MEM_CAM_DQ<1> 0 MF 72 31 IN R2 A7 DQL1 F7 BI 31 72 1 2 69 CLK25M_CAM_XTALN 1 2 CLK25M_CAM_CLKN OUT 31 69 201 2 72 31 IN MEM_CAM_A<8> T8 A8 DQL2 F2 MEM_CAM_DQ<2> BI 31 72 5% CAM_XTAL:YES 5% CAM_XTAL:YES MEM_CAM_A<9> R3 F8 MEM_CAM_DQ<3> 25V NOTE: TBD PPM crystal required 1/20W 72 31 IN A9 DQL3 BI 31 72 NP0-C0G-CERM MF 0201 CAM_XTAL:NO 72 31 IN MEM_CAM_A<10> L7 A10/AP DQL4 H3 MEM_CAM_DQ<4> BI 31 72 0201 1 C4016 72 31 IN MEM_CAM_A<11> R7 A11 DQL5 H8 MEM_CAM_DQ<5> BI 31 72 100PF 5% 72 31 IN MEM_CAM_A<12> N7 A12/BC* DQL6 G2 MEM_CAM_DQ<6> BI 31 72 2 25V NP0-CERM MEM_CAM_A<13> T3 H7 MEM_CAM_DQ<7> 0201 72 31 IN A13 DQL7 BI 31 72 C 72 31 IN MEM_CAM_A<14> T7 A14 DQSL F3 MEM_CAM_DQS_P<0> 31 72 C BI 72 31 IN MEM_CAM_BA<0> M2 BA0 DQSL* G3 MEM_CAM_DQS_N<0> BI 31 72 72 31 IN MEM_CAM_BA<1> N8 BA1 72 31 IN MEM_CAM_BA<2> M3 BA2 DQSU C7 MEM_CAM_DQS_P<1> BI 31 72 PP1V8_CAM 31 72 31 IN DQSU* B7 MEM_CAM_DQS_N<1> BI 31 72 1 72 31 IN MEM_CAM_RAS_L J3 RAS* 1 R4005 R4020 72 31 IN MEM_CAM_CAS_L K3 CAS* DQU0 D7 MEM_CAM_DQ<8> BI 31 72 100K 84.5 5% 1% 72 31 IN MEM_CAM_WE_L L3 WE* DQU1 C3 MEM_CAM_DQ<9> BI 31 72 1/20W 1/20W C8 MEM_CAM_DQ<10> CAM_WAKE:YES MF MF DQU2 BI 31 72 2 201 2 201 MEM_CAM_CLK_P J7 CK DQU3 C2 MEM_CAM_DQ<11> BI 31 72 R4030 MEM_CAM_CLK_N K7 CK* A7 MEM_CAM_DQ<12> CAM_SENSOR_WAKE_L_CONN 1 0 2 CAM_SENSOR_WAKE_L 72 31 IN DQU4 BI 31 72 64 32 31 DQU5 A2 MEM_CAM_DQ<13> BI 31 72 0201 5% 1/20W 72 31 IN MEM_CAM_CKE K9 CKE DQU6 B8 MEM_CAM_DQ<14> BI 31 72 CAM_WAKE:NO MF NO STUFF 72 31 IN MEM_CAM_CS_L L2 CS* DQU7 A3 MEM_CAM_DQ<15> BI 31 72 R40311 1 0 R4021 5% 82 72 MEM_CAM_ODT K1 ODT DML E7 MEM_CAM_DM<0> IN 31 72 1/20W 1% MF 1/20W DMU D3 MEM_CAM_DM<1> IN 31 72 0201 2 MF 2 201 MEM_CAM_ZQ_DDR L8 ZQ MEM_CAM_CKE_R 31 IN MEM_CAM_RESET_L T2 RESET* NO STUFF 1 R4006 VSSQ VSS 100PF B1 B9 D1 D8 E2 E8 F9 G1 G9 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 5% 25V 2 NP0-CERM 0201 1 R4004 B 1% 240 B 1/20W MF 2 201 CAMERA SENSOR L4009 90-OHM-50MA TCM0605-1 SYM_VER-1 CRITICAL 1 4 MIPI_CLK_N IN 31 72 J4002 CCR20-AK7100-1 F-RT-SM 2 3 MIPI_CLK_P IN 31 72 14 PLACE_NEAR=J4002.2:2.54MM 1 CRITICAL 2 MIPI_CLK_CONN_N 3 72 64 72 64 MIPI_CLK_CONN_P L4007 90-OHM-50MA TCM0605-1 4 CAM_SENSOR_WAKE_L_CONN 32 64 SYM_VER-1 5 72 64 MIPI_DATA_CONN_N 1 4 MIPI_DATA_N BI 31 72 6 72 64 MIPI_DATA_CONN_P 7 2 3 MIPI_DATA_P BI 31 72 8 SMBUS_SMC_1_S0_SDA A ALS 9 10 I2C_CAM_SCK BI SMBUS_SMC_1_S0_SCL IN 14 37 14 37 IN 31 64 40 43 44 64 69 73 40 43 44 64 69 73 L4010 PLACE_NEAR=J4002.5:2.54MM CRITICAL SYNC_MASTER=J41_MLB PAGE TITLE SYNC_DATE=03/20/2013 A 11 12 64 I2C_CAM_SDA BI PP5V_S3RS0_ALSCAM_F 31 64 MIN_LINE_WIDTH=0.5 mm FERR-120-OHM-1.5A 2 1 PP5V_S0 16 17 45 46 51 52 56 58 59 61 62 64 Camera 2 of 2 DRAWING NUMBER SIZE MIN_NECK_WIDTH=0.2 mm 0402-LF 13 VOLTAGE=5V NOSTUFF Apple Inc. <SCH_NUM> D C4013 1 L4011 REVISION 0.1uF FERR-120-OHM-1.5A R <E4LABEL> 20% 10V NOTICE OF PROPRIETARY PROPERTY: 518S0892 CERM 2 2 1 PP5V_S4RS3 BRANCH 402 0402-LF 35 47 49 54 55 58 62 64 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. <BRANCH> 77.2 mA nominal max THE POSESSOR AGREES TO THE FOLLOWING: PAGE 96.2 mA peak I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 40 OF 121 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 32 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 64 62 58 39 38 36 33 29 PP3V3_S4 1 R4410 470K 5% Q4410 1/20W MF 1 DMN5L06VK-7 R4411 SOT-563 2 201 470K D G 2 5% D 1/20W MF 201 2 Q4410 D S SMC_PME_SDCONN G 5 To SMC SMC_PME_S4_DARK_L DMN5L06VK-7 6 1 25 38 37 33 SOT-563 SDCONN_STATE_CHANGE Isolation D S 38 37 33 25 SMC_PME_S4_DARK_L 3 4 64 62 58 41 40 36 19 18 15 PP3V3_S3 CRITICAL U4410 74AUP1G09 6 SOT891 VCC 16 15 OUT XDP_SDCONN_STATE_CHANGE_L 4 Y A 2 BYPASS=U4410.5:5mm To PCH B 1 C4410 1 0.1UF NC 5 10% NC 6.3V GND CERM-X5R 2 3 0201 64 62 58 39 38 36 33 29 PP3V3_S4 BYPASS=U4430.1:5mm C4430 1 C C 0.1UF 10% CRITICAL 1 16V X5R-CERM 2 0201 VDD U4430 SLG4AP014V TDFN 2 LOW_PWR RST RST_OUT* 4 LOGIC NC 3 RST_IN* 6 DET_IN DLY (OD) 8 SDCONN_STATE_CHANGE_SAK_L XOR (IPU) FROM SD CONN -> DET_CHNGD* (IPU) DLY block is 20ms nominal (OD) 7 SDCONN_DETECT_L OUT 34 75 DET_OUT THRM GND PAD 5 9 SD CARD CONNECTOR CRITICAL 516-0253 J4400 SD-CARD-K16 CRITICAL F-RT-TH-1 L4400 R4480 R4481 B 47NH-1.3OHM 0402 0 402 0 402 3 6 VSS VSS B 5% MF-LF 1/16W 5% MF-LF 1/16W 75 34 IN SDCONN_CLK R4479 33 1 2 5% 1/20W MF 201 SDCONN_CLK_L 1 2 SDCONN_CLK_R1 1 2 SDCONN_CLK_R2 1 2 SD_CONN_CLK 5 CLK 75 34 OUT SDCONN_CMD R4461 0 1 2 5% 1/20W MF 0201 SDCONN_CMD_R 2 CMD 75 34 BI SDCONN_DATA<0> R4471 0 1 2 5% 1/20W MF 0201 SDCONN_R_DATA<0> 7 DAT0 75 34 BI SDCONN_DATA<1> R4472 0 1 2 5% 1/20W MF 0201 SDCONN_R_DATA<1> 8 DAT1 75 34 BI SDCONN_DATA<2> R4473 0 1 2 5% 1/20W MF 0201 SDCONN_R_DATA<2> 9 DAT2 75 34 BI SDCONN_DATA<3> R4474 0 1 2 5% 1/20W MF 0201 SDCONN_R_DATA<3> 1 CD/DAT3 10 NC DAT4 11 NC DAT5 12 NC DAT6 13 NC DAT7 SD_CD_L 14 CARD_DETECT_SW (CARD INSERTED = GROUND) 15 NOSTUFF NOSTUFF NOSTUFF CARD_DETECT_GND SDCONN_WP 16 WRITE_PROTECT_SW NOSTUFF 1 C4470 1 C4473 1 C4475 75 34 OUT 34 PP3V3_S0_SD_CONN 4 1 C4471 15PF 10PF 10PF NOSTUFF VDD 5% 5% 5% 22PF 50V 2 CERM 50V 50V 1 17 5% 2 CERM 2 CERM R4482 SHLD_PIN 2 50V CERM 402 402 402 0 18 SHLD_PIN 402 NOSTUFF 5% 19 1/16W SHLD_PIN NOSTUFF 1 C4474 MF-LF NOSTUFF 20 1 C4472 10PF 2 402 SHLD_PIN 10PF 5% 2 50V 1 C4476 5% 50V CERM 402 10PF 2 CERM 5% 402 2 50V CERM 402 SD CARD A SYNC_MASTER=MASTER SYNC_DATE=07/01/2011 A PAGE TITLE SD READER CONNECTOR DRAWING NUMBER SIZE Apple Inc. <SCH_NUM> D REVISION R <E4LABEL> NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. <BRANCH> THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 44 OF 121 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 33 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 3.3V S3 SD Card Switch 42 29 28 18 17 16 15 13 11 8 PP3V3_S5 74 64 62 60 59 58 57 NOSTUFF 1 1 R4595 VDD 10K 5% 1/20W U4550 PP3V3_S0SW_SD MF 201 2 SLG5AP1443V 15 34 37 39 65 P3V3_SD_FET_RAMP 7 TDFN 3 CAP D SD_PWR_EN 2 CRITICAL 5 PP3V3_S0SW_SD 15 ON S 65 39 37 34 15 D IN BYPASS=U4550.A2:5mm GND MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V D MAKE_BASE=TRUE C4560 1 C4561 1 8 1.0UF 4700PF U4550 EDP: 1.05A 20% 10% 6.3V 2 10V X5R X7R 2 0201-1 201 Part SLG5AP1438V Type Load Switch R(on) 15 mOhm Typ 17 mOhm Max Current 2.5A CRITICAL CRITICAL L4500 L4501 FERR-1000-OHM-450MA FERR-1000-OHM-450MA 1 2 PP1V2_S0_SD_AVDD12 PP3V3_S0_SD_AVDD33 1 2 0402 MIN_LINE_WIDTH=0.5 MM MIN_LINE_WIDTH=0.5 MM 0402 MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.2V VOLTAGE=3.3V BYPASS=U4500.43:5mm BYPASS=U4500.46:5mm BYPASS=U4500.3:5mm C4523 1 C4524 1 C4525 1 C4526 1 C4527 1 C4528 1 0.1UF 0.1UF 1.0UF BYPASS=U4500.3:5mm 0.1UF 0.1UF 2.2UF BYPASS=U4500.43:5mm 10% 10% 10% BYPASS=U4500.9:5mm 10% 10% 20% 16V 16V 6.3V 16V 16V 6.3V X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 CERM 2 0201 0201 0201-1 0201 0201 402-LF C C PP1V2_S3_SD_DVDD12 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM BYPASS=U4500.42:5mm BYPASS=U4500.21:5mm VOLTAGE=1.2V PP1V2_S0_SD_VUHS1 BYPASS=U4500.38:5mm BYPASS=U4500.22:5mm MIN_LINE_WIDTH=0.5 MM C4519 1 C4520 1 PP3V3_S0_SD_CONN MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.8V C4521 1 C4522 1 C4518 1 BYPASS=U4500.31:5mm 0.1UF 2.2UF 34 33 MIN_LINE_WIDTH=0.5 MM VOLTAGE=3.3V BYPASS=U4500.30:5mm 4.7UF 1.0UF 0.1UF 10% 20% MIN_NECK_WIDTH=0.20MM MAKE_BASE=TRUE 20% 10% 10% 16V X5R-CERM 2 4V X5R-CERM 2 900mA max C4529 1 C4530 1 C4531 1 6.3V 2 X5R 6.3V X5R-CERM 2 16V X5R-CERM 2 0201 0201 PP3V3_S0_SD_CONN 34 33 47PF 100PF 1.0UF 402 0201-1 0201 5% BYPASS=U4500.30:5mm 25V 5% 10% 25V 6.3V BYPASS=U4500.39:5mm NP0-C0G-CERM 2 NP0-CERM 2 X5R-CERM 2 NO USB 2.0 INTERFACE PMOS33 39 AVDD12 46 AVDD33 43 DVDD12 21 DVDD12 42 DVDD33 31 DVDD33 38 DVDD33 40 V33IN 22 VUHSI 30 C4550 1 0201 0201 0201-1 AVDD12 3 AVDD33 9 4.7UF USB_SD_DM BYPASS=U4500.30:5mm 20% 6.3V 2 X5R 1 402 R4580 0 5% 1/20W 45 DM SD_D1 24 SDCONN_DATA<1> BI 33 75 MF 0201 2 44 DP U4500 SD_D0 25 SDCONN_DATA<0> BI 33 75 USB_SD_DP GL3219 SD_D2 29 SDCONN_DATA<2> BI 33 75 7 X1 LQFN SD_D3 28 SDCONN_DATA<3> BI 33 75 8 X2 PLACE_NEAR=U4500.4:5mm PLACE_NEAR=U4500.1:5mm 68 65 14 USB3_SD_R2D_C_N C4510 1 2 GND_VOID=TRUE 68 USB3_SD_R2D_N 4 RXN CRITICAL TXN 68 1 USB3_SD_D2R_C_N C4512 1 2 GND_VOID=TRUE USB3_SD_D2R_N 14 65 68 IN OUT 10% 16V X5R-CERM 0201 10% 16V X5R-CERM 0201 0.1UF 68 USB3_SD_R2D_P 5 RXP TXP 68 2 USB3_SD_D2R_C_P 0.1UF USB3_SD_R2D_C_P C4511 1 2 OMIT_TABLE C4513 1 2 USB3_SD_D2R_P 68 65 14 IN GND_VOID=TRUE GND_VOID=TRUE OUT 14 65 68 PLACE_NEAR=U4500.5:5mm 10% 16V X5R-CERM 0201 10% 16V X5R-CERM 0201 0.1UF SD_RTERM 10 RTERM SD_CLK 26 SDCONN_CLK OUT 33 75 0.1UF PLACE_NEAR=U4500.2:5mm R4570 (IPU) SD_WP 23 SDCONN_WP IN 33 75 3.3K 2 B 15 IN SD_RESET_L 1 5% SD_RESET_R_L 41 RSTZ* (IPU) SD_CMD (IPU) SD_CDZ 27 20 SDCONN_CMD SDCONN_DETECT_L BI 33 75 BYPASS=U4590.8:5mm B 1/20W MF 11 NC IN 33 75 C4590 1 201 NC SPI_CK 75 35 SD_SPI_CLK 1.0UF NOSTUFF 12 NC 10% NC SPI_CS 34 SD_SPI_CS_L 6.3V X5R-CERM 2 75 13 NC NC SPI_SI 75 36 SD_SPI_MOSI 0201-1 8 14 NC NOSTUFF NC SD_SPI_MISO C4570 1 R45001 NC 15 NC SPI_SO 75 37 VCC NOSTUFF 1 R4590 1 R4591 0.047UF 680 16 10% 1% NC NC LED 33 NC U4590 3.3K 3.3K 6.3V 2 1/20W 17 5% 5% X5R MF NC NC 512KB 1/20W 1/20W 201 201 2 USON MF MF 18 NC 201 2 NC W25X05CL 2 201 19 NC NC 47 THRM 32 5 DIO(IO0) CLK 6 6 GND PAD NC NC CRITICAL 2 DO(IO1) CS* 1 NOSTUFF WP* 3 SD_SPI_WP_L HOLD* 7 SD_SPI_HOLD_L THRM PAD GND 9 4 USING ON CHIP CLOCK SOURCE MODE (CRYSTAL AS BACK-UP) C4580 R4581 12PF 2 1 SDCLK_CLK25M_X2 1 0 2 SDCLK_CLK25M_X2_R 69 75 69 5% 5% 1/20W 25V 1 CRITICAL MF R4582 1 NP0-C0G-CERM 0201 0201 NC Y4580 1M 2 4 NC 5% 25.000MHZ-12PF-20PPM 1/20W C4581 MF 3 SM-3.2X2.5MM 2 201 12PF A 1 2 69 SDSCLK_CLK25M_X1 SYNC_MASTER=MASTER SYNC_DATE=10/11/2010 A 5% PAGE TITLE 25V NP0-C0G-CERM 0201 SD CONTROLLER (GL3219) DRAWING NUMBER SIZE Apple Inc. <SCH_NUM> D REVISION R <E4LABEL> NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE <BRANCH> PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 45 OF 121 II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 34 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 Right USB Port A D USB Port Power Switch D CRITICAL CRITICAL L4605 U4600 FERR-120-OHM-3A TPS2557DRB SON PP5V_S3_RTUSB_A_ILIM 1 2 PP5V_S3_RTUSB_A_F MIN_LINE_WIDTH=0.5 mm MIN_LINE_WIDTH=0.5 mm 64 62 58 55 54 49 47 32 PP5V_S4RS3 2 IN_0 OUT1 6 MIN_NECK_WIDTH=0.15 mm 0603 MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V VOLTAGE=5V 3 IN_1 OUT2 7 C4605 1 0.01UF 16 14 XDP_USB_EXTA_OC_L 8 FAULT* ILIM 5 USB_ILIM 10% CRITICAL OUT 16V 2 USB_PWR_EN 4 EN 1 X5R-CERM 0201 J4600 65 61 59 R4600 USB3.0-J11-J13 THRM 22.1K F-RT-TH CRITICAL 1% CRITICAL GND PAD 1/20W C4690 1 1 C4691 1 C4696 MF C4695 1 L4600 1 VBUS 1 9 201 2 90-OHM 10UF 0.1UF 220UF-35MOHM 10UF DLP0NS 2 20% 10% 20% USB_ILIM_R 20% SYM_VER-1 SSTX+ 6.3V 2 2 16V 2 6.3V 6.3V 2 3 CERM-X5R X5R-CERM POLY-TANT CERM-X5R 4 3 SSTX- 0402-1 0201 1 0402-1 4 CASE-B2-SM1 R4601 5 GND 22.1K 68 USB2_EXTA_MUXED_N 68 USB2_EXTA_MUXED_F_N D- 1% 6 1/20W 68 USB2_EXTA_MUXED_P 1 2 68 USB2_EXTA_MUXED_F_P D+ MF 7 2 201 GND CRITICAL CRITICAL 8 2 2 SXRX+ D4601 D4600 9 SSRX- ESD0P2RF-02LS ESD0P2RF-02LS 10 Current limit per port (R4600+R4601): 2.19A min / 2.76A max TSSLP-2-1 TSSLP-2-1 GND 1 1 11 C 12 13 C 14 15 Mojo SMC Debug Mux 16 17 18 59 50 49 46 40 38 37 36 30 17 PP3V42_G3H 65 64 62 61 BYPASS=U4650.9:3:5mm C4650 1 1 R4650 APN: 514-0819 0.1UF 100K 68 14 OUT USB3_EXTA_D2R_N 10% 5% 10V 9 X5R-CERM 2 1/20W MF 0201 VCC 2 201 68 14 USB3_EXTA_D2R_P OUT 68 38 37 SMC_DEBUGPRT_RX_L 5 M+ Y+ 1 IN SMC_DEBUGPRT_TX_L 4 M- Y- 2 68 38 37 OUT U4650 GND_VOID=TRUE GND_VOID=TRUE PI3USB102EZLE 7 D+ TQFN CRITICAL CRITICAL USB_EXTA_P 2 2 68 14 68 14 BI USB_EXTA_N 6 D- CRITICAL D4621 D4620 BI ESD0P2RF-02LS ESD0P2RF-02LS TSSLP-2-1 TSSLP-2-1 8 OE* SEL 10 SMC_DEBUGPRT_EN_L IN 37 1 1 GND SEL OUTPUT SIGNAL_MODEL=MOJO_MUX_SMSC 3 L SMC (M) H USB (D) B B GND_VOID=TRUE C4620 0.1UF USB3_EXTA_R2D_C_N 1 2 68 USB3_EXTA_R2D_N 68 14 IN C4621 10% 6.3V CERM-X5R 0201 0.1UF 68 14 IN USB3_EXTA_R2D_C_P 1 2 68 USB3_EXTA_R2D_P 10% 6.3V CERM-X5R 0201 GND_VOID=TRUE GND_VOID=TRUE GND_VOID=TRUE CRITICAL 2 2 CRITICAL D4611 D4610 ESD0P2RF-02LS ESD0P2RF-02LS TSSLP-2-1 TSSLP-2-1 1 1 A SYNC_MASTER=J41_MLB SYNC_DATE=02/07/2013 A PAGE TITLE External A USB3 Connector DRAWING NUMBER SIZE Apple Inc. <SCH_NUM> D REVISION R <E4LABEL> NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. <BRANCH> THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 46 OF 121 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 35 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 PLACE_NEAR=J4800.10:1.5MM R4830 0 64 62 58 39 38 36 33 29 PP3V3_S4 1 2 VOLTAGE=3.3V 5% 1/20W MF 0201 C4800 1 MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.5 mm IPD Flex Connector 0.1UF 10% 6.3V CERM-X5R 2 BYPASS=J4800.10:1.5MM 0201 CRITICAL PLACE_NEAR=J4800.14:1.5MM 518S0884 D L4820 J4800 D FERR-120-OHM-1.5A TF13BS-20S-0.4SH F-RT-SM-1 62 54 53 PP5V_S5 1 2 22 0402-LF MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V R4850 C4810 1 33 65 64 61 38 37 36 IN SMC_LID 1 0.1UF 15 OUT TPAD_SPI_MISO 1 2 64 TPAD_SPI_MISO_R 2 10% 68 5% 1/20W MF 201 16V 3 X5R-CERM 2 PLACE_NEAR=J4800.2:2.54mm 0201 50 49 46 40 38 37 35 30 17 PP3V42_G3H 68 64 14 USB_TPAD_P 4 65 64 62 61 59 BI PLACE_NEAR=J4800.14:1.5MM BYPASS=J4800.19:1.5MM 68 64 14 BI USB_TPAD_N 5 C4820 1 6 0.1UF 10% 15 IN TPAD_SPI_CLK 1 2 33 R4851 TPAD_SPI_CLK_R 64 7 6.3V 68 5% 1/20W MF 201 64 TPAD_WAKE_L 8 CERM-X5R 2 PLACE_NEAR=J4800.7:2.54mm 0201 15 IN TPAD_SPI_MOSI 1 2 33 R4852 64 TPAD_SPI_MOSI_R 9 68 5% 1/20W MF 201 PLACE_NEAR=J4800.9:2.54mm 64 PP3V3_S4_IPD 10 TPAD_INTWAKE:SPLIT 1 2 33 R4853 64 TPAD_SPI_CS_R_L 11 PLACE_NEAR=R4844.1:1.5MM R4841 5% 1/20W MF 201 PLACE_NEAR=J4800.12:2.54mm 64 TPAD_SPI_IF_EN_CONN 12 0 (TPAD_WAKE_L) 1 2 64 TPAD_SPI_INT_S4_WAKE_L_CONN 13 5% 64 PP5V_S4_IPD 14 1/20W MF 64 TPAD_USB_IF_EN_CONN 15 0201 73 64 44 40 37 36 BI SMBUS_SMC_3_SDA 16 TPAD_INTWAKE:SHARED SMBUS_SMC_3_SCL 17 73 64 44 40 37 36 BI R4843 64 38 36 OUT SMC_LSOC_RST_L 18 0 39 37 29 OUT SMC_PME_S4_WAKE_L 1 2 (TPAD_SPI_INT_S4_WAKE_L_CONN) (=PP3V42_G3H_IPD) 19 5% 64 38 37 36 OUT SMC_ONOFF_L 20 To SMC 1/20W MF PLACE_NEAR=R4841.1:1.5MM 0201 21 C TPAD_INTWAKE:SHARED C TPAD_INTWAKE:SHARED R48441 Q4800 0 5% PP3V3_S3 1 64 62 58 41 40 36 33 19 18 15 DMN32D2LFB4 1/20W DFN1006H4-3 MF G SYM_VER_3 0201 2 PLACE_NEAR=J4800.8:1.5MM S D 15 OUT TPAD_SPI_INT_L 3 2 To PCH PLACE_NEAR=R4842.2:5MM TPAD_INTWAKE:SPLIT R4842 1 0 2 5% 1/20W MF 0201 PLACE_NEAR=R4843.2:1.5MM 64 62 58 39 38 36 33 29 PP3V3_S4 C4841 1 0.1UF 10% BYPASS=U4810:3mm 6.3V CERM-X5R 2 0201 CRITICAL 8 74LVC2G08GT PM_SLP_S4_L 1 SOT833 59 37 36 29 18 13 IN A U4810Y 7 (TPAD_USB_IF_EN_CONN) B 15 IN TPAD_USB_IF_EN 2 B 08 B From PCH NOSTUFF 4 1 R4810 100K 5% 1/20W MF 2 201 CKPLUS_WAIVE=UNCONNECTED_PINS 8 74LVC2G08GT PM_SLP_S4_L 5 SOT833 59 37 36 29 18 13 IN A U4810Y 3 (TPAD_SPI_IF_EN_CONN) 15 IN TPAD_SPI_IF_EN 6 B 08 From PCH 4 CKPLUS_WAIVE=UNCONNECTED_PINS 64 62 58 41 40 36 33 19 18 15 PP3V3_S3 1 R4860 PP3V3_S0 Q4860 100K 1 74 65 64 62 38 30 27 18 17 15 13 12 11 8 61 59 56 45 44 43 42 41 40 39 DMN32D2LFB4 DFN1006H4-3 5% 1/20W G SYM_VER_3 MF 2 201 SMBUS_SMC_3_SDA 36 37 40 44 64 73 S D 15 IN TPAD_SPI_CS_L TPAD_SPI_CS_CONN_L SMBUS_SMC_3_SCL 36 37 40 44 64 73 A 3 A 2 SMC_ONOFF_L 36 37 38 64 SYNC_MASTER=J41_MLB SYNC_DATE=02/12/2013 SMC_LID 36 37 38 61 64 65 PAGE TITLE SMC_LSOC_RST_L 36 38 64 IPD Connector NOSTUFF NOSTUFF DRAWING NUMBER SIZE 1 C4832 1 C4833 1 C4834 1 C4835 1 C4836 Apple Inc. <SCH_NUM> D 100PF 100PF 100PF 100PF 100PF REVISION 5% 5% 5% 5% 5% R 2 25V NP0-CERM 25V 2 NP0-CERM 2 25V NP0-CERM 2 25V NP0-CERM 25V 2 NP0-CERM <E4LABEL> 0201 0201 0201 0201 0201 NOTICE OF PROPRIETARY PROPERTY: BRANCH BYPASS=J4800.6:1.5MM BYPASS=J4800.4:1.5MM BYPASS=J4800.1:1.5MM BYPASS=J4800.5:1.5mm BYPASS=J4800.3:8.5MM THE INFORMATION CONTAINED HEREIN IS THE <BRANCH> PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 48 OF 121 II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 36 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 D D U5000 LM4FSXAH5BB BGA 69 64 46 14 BI LPC_AD<0> B13 LPC0AD0 (1 OF 2) AIN00 E2 SMC_HS_COMPUTING_ISENSE IN 39 41 69 64 46 14 BI LPC_AD<1> A13 LPC0AD1 AIN01 E1 SMC_PBUS_VSENSE IN 39 42 69 64 46 14 BI LPC_AD<2> C12 LPC0AD2 OMIT_TABLE AIN02 F2 SMC_BMON_ISENSE IN 39 41 69 64 46 14 BI LPC_AD<3> D11 LPC0AD3 AIN03 F1 SMC_DCIN_ISENSE IN 39 41 69 17 IN LPC_CLK24M_SMC H12 LPC0CLK AIN04 B3 SMC_DCIN_VSENSE IN 39 42 69 64 46 14 IN LPC_FRAME_L D12 LPC0FRAME* AIN05 A3 SMC_BMON_DISCRETE_ISENSE IN 39 43 18 IN SMC_LRESET_L C13 LPC0RESET* AIN06 B4 SMC_CPU_ISENSE IN 39 42 PP3V42_G3H 17 30 35 36 38 40 46 49 50 59 61 62 64 65 64 46 15 BI LPC_SERIRQ (OD) H13 LPC0SERIRQ AIN07 A4 SMC_OTHER_HI_ISENSE IN 39 41 64 46 13 OUT PM_CLKRUN_L (OD) G11 LPC0CLKRUN* AIN08 B5 SMC_PANEL_ISENSE IN 39 43 L5001 64 46 13 LPC_PWRDWN_L F13 LPC0PD* AIN09 A5 SMC_1V2S3_ISENSE 39 41 30-OHM-1.7A IN IN 13 SMC_RUNTIME_SCI_L F12 LPC0SCI* AIN10 B6 SMC_LCDBKLT_ISENSE 39 41 1 2 PP3V3_S5_SMC_VDDA OUT IN MIN_LINE_WIDTH=0.25MM 15 OUT SMC_WAKE_SCI_L B12 PK5 AIN11 A6 SMC_P3V3S5_ISENSE IN 39 42 0402 MIN_NECK_WIDTH=0.1MM VOLTAGE=3.3V AIN12 C1 SMC_WLAN_ISENSE IN 39 41 1 C5002 1 C5003 1 C5004 1 C5005 1 C5006 1 R5002 1 C5001 SMBUS_SMC_0_S0_SCL (OD) E10 C2 SMC_SSD_ISENSE 1M 0.1UF 73 60 40 BI I2C0SCL AIN13 IN 39 41 1UF 0.1UF 0.1UF 0.1UF 0.1UF 5% U5000 10% 73 60 40 SMBUS_SMC_0_S0_SDA (OD) D13 I2C0SDA AIN14 B1 SMC_P3V3S0_ISENSE 39 41 20% 6.3V 10% 10% 10% 10% 1/20W LM4FSXAH5BB 2 10V BI IN 2 X5R 2 10V X5R-CERM 10V 2 X5R-CERM 2 10V X5R-CERM 10V 2 X5R-CERM MF X5R-CERM 0201 73 69 64 44 43 40 32 14 BI SMBUS_SMC_1_S0_SCL (OD) M4 I2C1SCL AIN15 B2 SMC_CAMERA_ISENSE IN 39 41 0201 0201 0201 0201 0201 2 201 BGA 73 69 64 44 43 40 32 14 BI SMBUS_SMC_1_S0_SDA (OD) N2 I2C1SDA AIN16 G2 PP3V3_S0SW_SD IN 15 34 39 65 (2 OF 2) 73 65 61 40 SMBUS_SMC_2_S3_SCL (OD) N8 I2C2SCL AIN17 G1 SMC_P1V05S0_VSENSE 39 42 50 46 38 SMC_RESET_L G10 RST* SWCLK/TCK C10 SMC_TCK 38 46 64 BI IN 64 IN 73 65 61 40 SMBUS_SMC_2_S3_SDA (OD) M8 I2C2SDA AIN18 H1 SMC_CPUDDR_ISENSE 39 42 SWDIO/TMS A10 SMC_TMS 38 46 64 BI IN 73 64 44 40 36 SMBUS_SMC_3_SCL (OD) L8 I2C3SCL AIN19 H2 SMC_P1V05S0_ISENSE 39 42 64 38 29 WIFI_EVENT_L (OD) B11 PK4/RTCCLK SWO/TDO A11 SMC_TDO 38 46 64 BI IN BI SMBUS_SMC_3_SDA K8 B7 SMC_CPU_VSENSE SMC_WAKE_L N13 B10 SMC_TDI C 73 64 44 40 36 64 BI BI NC_SMBUS_SMC_4_ASF_SCL (OD) (OD) N7 I2C3SDA I2C4SCL AIN20 AIN21 A7 SMC_CPUVR_ADJUST_ISENSE IN IN 39 42 39 43 1 C5007 0.1UF 1 C5008 0.1UF 1 C5009 0.1UF NC_SMC_HIB_L M12 WAKE* HIB* TDI 38 46 64 C 64 NC_SMBUS_SMC_4_ASF_SDA (OD) M7 I2C4SDA AIN22 B8 SMC_CPU_IMON_ISENSE 39 43 10% 10% 10% NC A2 BI IN 2 10V 10V 2 X5R-CERM 2 10V NC 73 64 50 48 40 SMBUS_SMC_5_G3_SCL (OD) N4 I2C5SCL AIN23 A8 PP3V3_WLAN 29 38 39 41 64 X5R-CERM X5R-CERM 69 38 SMC_CLK32K M10 XOSC0 BI IN 0201 0201 0201 IN 73 64 50 48 40 BI SMBUS_SMC_5_G3_SDA (OD) N3 I2C5SDA NC_SMC_XOSC1 N10 XOSC1 C0- K2 CPU_PROCHOT_L IN 6 38 51 67 VDDA D3 45 OUT SMC_FAN_0_CTL H11 PM6/FAN0PWM0 C0+ K1 SMC_VCCIO_CPU_DIV2 IN 38 38 SMC_EXTAL G12 OSC0 45 SMC_FAN_0_TACH L13 PM7/FAN0TACH0 C1- L2 SMC_S5_PWRGD_VIN 38 38 SMC_XTAL G13 OSC1 VREFA+ D2 PP3V3_S5_AVREF_SMC 38 IN IN NC_SMC_FAN_1_CTL C11 PK6/FAN0PWM1 PC5/C1+ L1 SPI_DESCRIPTOR_OVERRIDE_L VREFA- D1 64 64 OUT NC_SMC_FAN_1_TACH A12 PK7/FAN0TACH1 T3CCP1/PJ5/C2- C5 CPU_CATERR_L OUT 17 6 67 K12 VBAT XW5000 SM IN IN 43 42 39 SMC_TOPBLK_SWP_L G3 PN2/FAN0PWM2 T3CCP0/PJ4/C2+ D5 CPU_THRMTRIP_3V3 38 C3 41 38 GND_SMC_AVSS 2 1 OUT IN 58 42 39 SMC_SENSOR_PWR_EN D10 PN3/FAN0TACH2 D7 GNDA E3 OUT PLACE_NEAR=U5000.A1:4MM SSI0CLK/PA2 M2 SMC_PM_G2_EN 38 54 59 E6 OUT SMC_SYS_KBDLED L11 M3 PM_DSW_PWRGD E8 OMIT_TABLE A1 56 OUT PN4/FAN0PWM3 SSI0FSS/PA3 OUT 13 64 NC_SMC_T25_EN_L N12 PN5/FAN0TACH3 SSI0RX/PA4 L4 SMC_DELAYED_PWRGD 17 27 38 E9 C7 OUT OUT 39 TP_SMC_5VSW_PWR_EN N11 PN6/FAN0PWM4 SSI0TX/PA5 N1 SMC_PROCHOT 38 F10 VDD D9 OUT OUT 65 61 SYS_ONEWIRE M11 PN7/FAN0TACH4 J7 E5 IN NC_SMC_FAN_5_CTL J4 PH2/FAN0PWM5 U1RX/B0 F11 SMC_DEBUGPRT_RX_L J9 F9 64 OUT SMC_PCH_SUSACK_L (OD) J2 PH3/FAN0TACH5 U1TX/PB1 E11 SMC_DEBUGPRT_TX_L IN 35 38 68 J10 H5 1 C5020 1 C5021 39 OUT OUT 35 38 68 0.01UF 1UF T0CCP0/PB6 F4 NC_SMC_SYS_LED 64 H9 10% 20% OUT GND 10V 2 X5R-CERM 2 X5R 6.3V 38 CPU_PECI_R C4 PECI0RX T0CCP1/PB7 F3 NC_SMC_GFX_THROTTLE_L 64 PP1V2_S5_SMC_VDDC J1 J5 BI BI 0201 0201 MIN_LINE_WIDTH=0.25MM J6 J8 38 OUT SMC_PECI_L C6 PECI0TX MIN_NECK_WIDTH=0.1MM VOLTAGE=1.2V VDDC J11 SSI1RX/PF0 M9 SPI_SMC_MISO IN 46 69 K13 BYPASS=U5000.D2:D1:1MM BYPASS=U5000.D2:D1:1MM 38 IN SMC_BIL_BUTTON_L M13 PP0/IRQ116 SSI1TX/PF1 N9 SPI_SMC_MOSI OUT 46 69 D6 K11 64 NC_SMC_DP_HPD_L L12 PP1/IRQ117 SSI1CLK/PF2 L10 SPI_SMC_CLK 46 69 IN OUT 39 36 29 SMC_PME_S4_WAKE_L M5 PP2/IRQ118 SSI1FSS/PF3 K10 SPI_SMC_CS_L 46 69 IN OUT 38 33 25 SMC_PME_S4_DARK_L J12 PP3/IRQ119 PF4 L9 S5_PWRGD 54 59 B 59 38 IN OUT SMC_S4_WAKESRC_EN J13 PP4/IRQ120 PF5 K9 PM_PCH_SYS_PWROK IN IN 13 16 17 PLACE_NEAR=U5000.D6:5MM PLACE_NEAR=U5000.K13:5MM PLACE_NEAR=U5000.J6:5MM PLACE_NEAR=U5000.D6:5MM PLACE_NEAR=U5000.K13:5MM PLACE_NEAR=U5000.J6:5MM PLACE_NEAR=U5000.J1:5MM PLACE_NEAR=U5000.J1:5MM B 39 38 IN SMC_SENSOR_ALERT_L (OD) L5 PP5/IRQ121 NC D8 PP6/IRQ122 WT0CCP0/PG4 K7 SMC_DEBUGPRT_EN_L OUT 35 65 64 61 38 36 IN SMC_LID K6 PP7/IRQ123 WT0CCP1/PG5 L7 NC_SMC_GFX_OVERTEMP IN 64 1 C5010 1 C5017 1 C5015 1 C5016 1 C5014 1 C5012 1 C5013 1 C5011 1.0UF 1.0UF 0.1UF 0.1UF 1.0UF 0.1UF 0.1UF 0.1UF 20% 20% 10% 10% 20% 10% 10% 10% 39 SMC_PCH_SUSWARN_L D4 PQ0/IRQ124 WT2CCP0/PH0 K3 ALL_SYS_PWRGD 16 17 59 6.3V 2 X5R 6.3V 2 X5R 2 10V 10V 2 X5R-CERM 6.3V 2 X5R 10V 2 X5R-CERM 10V 2 X5R-CERM 10V 2 X5R-CERM IN IN X5R-CERM 38 SMS_INT_L E4 PQ1/IRQ125 WT2CCP1/PH1 K4 SMC_THRMTRIP 38 0201-1 0201-1 0201 0201 0201-1 0201 0201 0201 IN OUT 65 61 50 38 IN SMC_BC_ACOK F5 PQ2/IRQ126 18 13 IN PM_SLP_S0_L N5 PQ3/IRQ127 WT3CCP0/PH4 J3 PM_PWRBTN_L OUT 13 16 59 18 17 13 PM_SLP_S3_L N6 PQ4/IRQ128 WT3CCP1/PH5 H4 PM_SYSRST_L 13 17 64 IN OUT 59 36 29 18 13 PM_SLP_S4_L K5 PQ5/IRQ129 WT4CCP0/PH6 H3 MEM_EVENT_L (OD) 38 IN BI 59 13 PM_SLP_S5_L M6 PQ6/IRQ130 WT4CCP1/PH7 G4 SMC_ADAPTER_EN 13 38 IN OUT 64 38 36 SMC_ONOFF_L L6 PQ7/IRQ131 IN T1CCP0/PJ0 C9 SMC_OOB1_D2R_L IN 30 64 46 38 SMC_RX_L L3 U0RX T1CCP1/PJ1 B9 SMC_OOB1_R2D_L 30 IN OUT 64 46 38 SMC_TX_L M1 U0TX T2CCP0/PJ2 A9 SMC_CPU_DBGPWR_RD_L 43 OUT OUT T2CCP1/PJ3 C8 NC_BDV_BKL_PWM OUT 64 30 OUT SMC_PWRFAIL_WARN_L (OD) E13 USB0DM (PL7) 39 29 OUT SMC_WIFI_PWR_EN E12 USB0DP (PL6) WT5CCP1/PM3 H10 PM_BATLOW_L OUT 13 NOTE: SMS Interrupt can be active high or low, rename net accordingly. If SMS interrupt is not used, pull up to SMC rail. A NOTE: Unused pins have "SMC_Pxx" names. Unused SYNC_MASTER=J41_MLB SYNC_DATE=02/06/2013 A PAGE TITLE pins designed as outputs can be left floating, those designated as inputs require pull-ups. SMC DRAWING NUMBER SIZE Apple Inc. <SCH_NUM> D REVISION R <E4LABEL> NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. <BRANCH> THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 50 OF 121 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 37 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 SMC Reset "Button", Supervisor & AVREF Supply R5127 67 51 37 6 BI CPU_PROCHOT_L 65 49 64 46 62 40 PP3V42_G3H 1 0 2 PP3V42_G3H_SMC_SPVSR 35 30 17 38 37 36 MIN_LINE_WIDTH=0.4 mm D 61 59 50 5% 1/16W NOSTUFF MIN_NECK_WIDTH=0.1 mm VOLTAGE=3.42V 6 Q5159 1 C5127 C5131 1 DMN5L06VK-7 MF-LF 402 4.7UF 20% 47PF 5% SOT-563 SMC12 PECI Support 6.3V 25V 2 X5R NP0-C0G-CERM 2 55 58 59 62 64 402 0201 PP1V05_S0 6 8 11 15 16 S G 2 17 27 38 42 51 43 42 41 38 37 GND_SMC_AVSS PLACE_NEAR=Q5159.6:5MM 1 50 49 46 40 38 37 36 35 30 17 PP3V42_G3H CRITICAL 65 64 62 61 59 SMC_PROCHOT IN 37 Q5150 D 1 R5100 DMN32D2LFB4 D 3 D 1 3 Desktops: 5V Mobiles: 3.42V C5120 1 V+ VIN 100K 5% DFN1006H4-3 SYM_VER_2 0.47UF U5110 1/20W 67 38 15 OUT PM_THRMTRIP_L 10% MF 6.3V VREF-3.3V-VDET-3.0V CERM-X5R 2 2 201 402 DFN 1 G S 2 64 36 IN SMC_LSOC_RST_L 6 MR1* (IPU) SN0903049 RESET* 5 SMC_RESET_L OUT 37 46 50 64 3 D Q5159 R5152 DMN5L06VK-7 0 64 38 37 36 IN SMC_ONOFF_L 7 MR2* (IPU) 37 IN SMC_PECI_L 1 2 SMC_PECI_L_R PP3V3_S5_AVREF_SMC 37 SOT-563 MIN_LINE_WIDTH=0.4 mm 5% SMC_MANUAL_RST_L 4 DELAY REFOUT 8 MIN_NECK_WIDTH=0.1 mm From SMC 1/20W CRITICAL THRM VOLTAGE=3.3V MF 1NOSTUFF 1 OMIT GND PAD 0201 R5153 R5151 1 S G 5 R5101 C5101 1 4 1.6K 330 2 9 5% 5% 0 5% 0.01UF C5125 1 1 C5126 SMC_THRMTRIP 1/20W MF 1/20W MF 1/10W 10% 10UF 0.01UF IN 37 38 201 MF-LF 10V 20% 10% 2 2 201 X5R-CERM 2 10V 10V 2 603 0201 X5R-CERM 2 2 X5R-CERM SILK_PART=SMC_RST 0402-1 0201 PLACE_SIDE=BOTTOM GND_SMC_AVSS 37 38 41 42 43 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.1 mm 38 37 OUT CPU_THRMTRIP_3V3 MR1* and MR2* must both be low to cause manual reset. VOLTAGE=0V Used on mobiles to support SMC reset via keyboard. CRITICAL NOTE: Internal pull-ups are to VIN, not V+. 3 R5134 Q5158 1 1 43 2 37 CPU_PECI_R CPU_PECI 6 SMC_BC_ACOK SMC_BC_ACOK MMBT3904LP-7 OUT BI 67 65 61 50 38 37 37 38 50 61 65 NOSTUFF Debug Power "Buttons" MAKE_BASE=TRUE DFN1006-3 2 R5158 3.3K 2 To SMC 1 C5134 5% 1/20W MF From/To CPU/PCH PM_THRMTRIP_R_L 1 PM_THRMTRIP_L IN 201 SMC_ONOFF_L OUT 36 37 38 64 15 38 67 47PF 5% 5% OMIT OMIT 1/20W 2 25V NP0-C0G-CERM MF 0201 R51161 1 R5115 201 PLACE_NEAR=Q5150.2:5MM PLACE_SIDE=BOTTOM 0 0 PLACE_SIDE=TOP 5% 5% C 1/10W MF-LF 603 2 1/10W MF-LF 2 603 C SILK_PART=PWR_BTN SILK_PART=PWR_BTN 50 49 46 40 38 37 36 35 30 17 65 64 62 61 59 PP3V42_G3H SMC Crystal Circuit 64 62 58 39 36 33 29 PP3V3_S4 SMC USB Clock require these crystal 74 65 64 62 36 30 27 18 17 15 13 12 11 8 61 59 56 45 44 43 42 41 40 39 PP3V3_S0 values:5,6,8,10,12,16,18,20,24,25 MHz 38 37 33 25 SMC_PME_S4_DARK_L R5167 100K 1 2 5% 1/20W MF 201 R5110 SMC_XTAL 1 2.49K2 SMC_XTAL_R SMC_ONOFF_L R5170 10K 1 2 37 64 38 37 36 R5172 10K 5% 1/20W MF 201 1% CRITICAL 39 37 SMC_SENSOR_ALERT_L 1 2 1/20W 5% 1/20W MF 201 MF 201 Y5110 65 64 61 37 36 SMC_LID R5171 100K 1 2 R5173 10K 5% 1/20W MF 201 3.2X2.5MM-SM 64 46 37 SMC_TX_L 1 2 12.000MHZ-30PPM-10PF-85C 64 46 37 SMC_RX_L R5174 100K 1 2 5% 1/20W MF 201 SMC_EXTAL 1 3 5% 1/20W MF 201 37 68 37 35 SMC_DEBUGPRT_TX_L R5175 20K 1 2 R5176 20K 5% 1/20W MF 201 2 4 68 37 35 SMC_DEBUGPRT_RX_L 1 2 NCNC SMC_PME_S4_DARK_L SMC_PME_S4_DARK_L SMC_TMS R5177 10K 1 2 5% 1/20W MF 201 1 C5110 1 C5111 38 37 33 25 MAKE_BASE=TRUE IN 25 33 37 38 64 46 37 SMC_TDO R5178 10K 1 2 5% 1/20W MF 201 12PF 12PF 64 46 37 5% 1/20W MF 201 5% 5% 64 46 37 SMC_TDI R5179 10K 1 2 2 25V NP0-C0G-CERM 2 25V NP0-C0G-CERM 51 42 38 27 17 16 15 11 8 6 PP1V05_S0 R5180 10K 5% 1/20W MF 201 0201 0201 64 62 59 58 55 64 46 37 SMC_TCK 1 2 R5181 10K 5% 1/20W MF 201 1 37 SMC_BIL_BUTTON_L 1 2 R5112 R5197 R5187 100K 5% 1/20W MF 201 B 69 13 IN PM_CLK32K_SUSCLK_R 1 22 2 SMC_CLK32K OUT 37 69 100K 1% 65 61 50 38 37 37 SMC_BC_ACOK SMC_S5_PWRGD_VIN R5192 100K 1 1 2 2 5% 1/20W MF 201 B 1/20W 5% 1/20W MF 201 PLACE_NEAR=U0500.AE6:5.1mm 5% 1/20W MF 201 MF 37 SMS_INT_L R5193 10K 1 2 2 201 5% 1/20W MF 201 SMC_VCCIO_CPU_DIV2 10KNO1 STUFF 37 37 MEM_EVENT_L R5114 2 5% 1/20W MF 201 38 37 CPU_THRMTRIP_3V3 R5117 100K 1 2 1 5% 1/20W MF 201 R5196 64 46 SMC_ROMBOOT 100K 1% 1 1/20W MF R5188 2 201 1K 5% 1/20W MF 2 201 59 54 37 SMC_PM_G2_EN R5198 100K 1 2 37 13 SMC_ADAPTER_EN R5185 10K 1 2 5% 1/20W MF 201 5% 1/20W MF 201 38 37 SMC_THRMTRIP R5186 10K 1 2 5% 1/20W MF 201 37 27 17 SMC_DELAYED_PWRGD R5191 100K 1 2 5% 1/20W MF 201 59 37 SMC_S4_WAKESRC_EN R5190 100K 1 2 5% 1/20W MF 201 PP3V3_WLAN 64 41 39 37 29 Module has 3.3K PU NO STUFF 64 37 29 WIFI_EVENT_L R5189 10K 1 2 5% 1/20W MF 201 A SYNC_MASTER=J41_MLB SYNC_DATE=02/06/2013 A PAGE TITLE SMC Shared Support DRAWING NUMBER SIZE Apple Inc. <SCH_NUM> D REVISION R <E4LABEL> NOTICE OF PROPRIETARY PROPERTY: BRANCH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. <BRANCH> THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 51 OF 121 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 38 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 41 39 37 SMC_HS_COMPUTING_ISENSE SMC_HS_COMPUTING_ISENSE 37 39 41 MAKE_BASE=TRUE 42 39 37 SMC_PBUS_VSENSE SMC_PBUS_VSENSE 37 39 42 MAKE_BASE=TRUE 41 39 37 SMC_BMON_ISENSE SMC_BMON_ISENSE 37 39 41 MAKE_BASE=TRUE 41 39 37 SMC_DCIN_ISENSE SMC_DCIN_ISENSE 37 39 41 MAKE_BASE=TRUE 42 39 37 SMC_DCIN_VSENSE SMC_DCIN_VSENSE 37 39 42 MAKE_BASE=TRUE 43 39 37 SMC_BMON_DISCRETE_ISENSE SMC_BMON_DISCRETE_ISENSE 37 39 43 MAKE_BASE=TRUE 42 39 37 SMC_CPU_ISENSE SMC_CPU_ISENSE 37 39 42 MAKE_BASE=TRUE D 41 39 37 SMC_OTHER_HI_ISENSE SMC_OTHER_HI_ISENSE MAKE_BASE=TRUE 37 39 41 D 43 39 37 SMC_PANEL_ISENSE SMC_PANEL_ISENSE 37 39 43 MAKE_BASE=TRUE 41 39 37 SMC_1V2S3_ISENSE SMC_1V2S3_ISENSE 37 39 41 MAKE_BASE=TRUE 41 39 37 SMC_LCDBKLT_ISENSE SMC_LCDBKLT_ISENSE 37 39 41 MAKE_BASE=TRUE 42 39 37 SMC_P3V3S5_ISENSE SMC_P3V3S5_ISENSE 37 39 42 MAKE_BASE=TRUE 41 39 37 SMC_WLAN_ISENSE SMC_WLAN_ISENSE 37 39 41 MAKE_BASE=TRUE 41 39 37 SMC_SSD_ISENSE SMC_SSD_ISENSE 37 39 41 MAKE_BASE=TRUE 41 39 37 SMC_P3V3S0_ISENSE SMC_P3V3S0_ISENSE 37 39 41 MAKE_BASE=TRUE 41 39 37 SMC_CAMERA_ISENSE SMC_CAMERA_ISENSE 37 39 41 MAKE_BASE=TRUE PP3V3_S0SW_SD OUT 15 34 37 65 SD alias on page 103 42 39 37 SMC_P1V05S0_VSENSE SMC_P1V05S0_VSENSE 37 39 42 MAKE_BASE=TRUE 42 39 37 SMC_CPUDDR_ISENSE SMC_CPUDDR_ISENSE 37 39 42 MAKE_BASE=TRUE 42 39 37 SMC_P1V05S0_ISENSE SMC_P1V05S0_ISENSE 37 39 42 MAKE_BASE=TRUE 42 39 37 SMC_CPU_VSENSE SMC_CPU_VSENSE 37 39 42 MAKE_BASE=TRUE 43 39 37 SMC_CPUVR_ADJUST_ISENSE SMC_CPUVR_ADJUST_ISENSE 37 39 43 MAKE_BASE=TRUE 43 39 37 SMC_CPU_IMON_ISENSE SMC_CPU_IMON_ISENSE 37 39 43 MAKE_BASE=TRUE 64 41 39 38 37 29 PP3V3_WLAN PP3V3_WLAN 29 37 38 39 41 64 MAKE_BASE=TRUE C SMC_SENSOR_PWR_EN 37 39 42 58 C 58 42 39 37 SMC_SENSOR_PWR_EN SMC_SENSOR_PWR_EN 37 39 42 58 MAKE_BASE=TRUE 39 37 29 SMC_WIFI_PWR_EN SMC_WIFI_PWR_EN 29 37 39 MAKE_BASE=TRUE 39 37 TP_SMC_5VSW_PWR_EN TP_SMC_5VSW_PWR_EN 37 39 MAKE_BASE=TRUE R5230 0 37 IN SMC_PCH_SUSWARN_L 1 2 PCH_SUSWARN_L OUT 13 MAKE_BASE=TRUE 5% 1/20W MF Top-Block Swap 0201 R5231 0 PP3V3_S0 64 65 74 8 11 12 13 15 17 18 27 30 36 38 37 OUT SMC_PCH_SUSACK_L 1 2 PCH_SUSACK_L IN 13 40 41 42 43 44 45 56 59 61 62 MAKE_BASE=TRUE 5% 1/20W 1 R5296 MF 0201 1K 5% 1/20W MF 201 2 R5283 SMC_TOPBLK_SWP_L 1 1K 2 PCH_STRP_TOPBLK_SWP_L 37 IN OUT 15 5% 1/20W MF 201 B B R5216 100 64 62 58 39 38 36 33 29 PP3V3_S4 43 IN SMC_HS_COMP_ALERT_L 1 2 5% NOSTUFF 1/20W R5215 MF 201 PCH_SML1ALERT_L 1 100 2 14 IN 5% 1/20W MF 201 R5213 R5295 10K 100 39 37 29 SMC_WIFI_PWR_EN 1 2 NOSTUFF 43 IN SMC_BMON_COMP_ALERT_L 1 2 5% 1/20W MF 201 5% 1/20W 58 42 39 37 SMC_SENSOR_PWR_EN R5294 10K 1 2 NOSTUFF R5210 MF 201 5% 1/20W MF 201 100 65 61 IN FINSTACKSNS_ALERT_L 1 2 5% 1/20W MF 201 R5214 100 44 IN CPUTHMSNS_ALERT_L 1 2 A NOSTUFF 5% 1/20W SYNC_MASTER=J41_MLB SYNC_DATE=02/06/2013 A PP3V3_S4 29 33 36 38 39 58 62 64 R5211 MF 201 PAGE TITLE 100 1 44 IN CPUBMONSNS_ALERT_L 1 2 SMC Project Support R5282 5% 1/20W DRAWING NUMBER SIZE 100K 5% MF 201 R5212 Apple Inc. <SCH_NUM> D 1/20W 100 REVISION MF 44 TBTMLBSNS_ALERT_L 1 2 SMC_SENSOR_ALERT_L 37 38 R 37 36 29 SMC_PME_S4_WAKE_L 2 201 IN 5% OUT <E4LABEL> IN 39 SMC_PME_S4_WAKE_L SMC_PME_S4_WAKE_L 1/20W MF NOTICE OF PROPRIETARY PROPERTY: BRANCH 37 36 29 39 IN MAKE_BASE=TRUE OUT 29 36 37 39 201 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. <BRANCH> THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 52 OF 121 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 39 OF 76 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 LYNX POINT LP S0 SMBus "0" Connections SMC "0" SMBus S0 Connections SMC "5" SMBus G3H Connections 74 65 64 62 61 36 30 27 18 17 15 13 12 11 8 PP3V3_S0 59 50 49 46 38 37 36 35 30 17 PP3V42_G3H 59 56 45 44 43 42 41 40 39 38 65 64 62 61 Pullups are on eDP LYNX POINT LP R53001 1 R5301 LCD BACKLIGHT SMC connector page and Internal DP SMC R53801 1 R5381 Battery Charger 1K 1K gated by EDP_PANEL_PWR 2.0K 2.0K 5% 5% J8300 5% 5% U0500 1/20W 1/20W U7701 U5000 U5000 1/20W 1/20W ISL6259 - U7100 MF MF (See Table) MF MF (MASTER) 201 2 2 201 (Write: 0x58 Read: 0X59) (MASTER) (MASTER) 201 2 2 201 (Write: 0x12 Read: 0x13) 25 19 16 14 SMBUS_PCH_CLK SMBUS_PCH_CLK 69 14 16 19 73 60 40 37 SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SCL 37 40 60 50 48 40 37 SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SCL 37 40 48 D 69 56 40 MAKE_BASE=TRUE 25 19 16 14 SMBUS_PCH_DATA SMBUS_PCH_DATA 25 40 56 69 14 16 19 MAKE_BASE=TRUE 73 60 40 37 SMBUS_SMC_0_S0_SDA SMBUS_SMC_0_S0_SDA 73 37 40 60 73 64 MAKE_BASE=TRUE 50 48 40 37 SMBUS_SMC_5_G3_SDA SMBUS_SMC_5_G3_SDA 50 64 73 37 40 48 D 69 56 40 MAKE_BASE=TRUE 25 40 56 MAKE_BASE=TRUE 73 73 64 MAKE_BASE=TRUE 50 64 73 VRef DACs Battery U2200 J6950 Battery (Write: 0x98 Read: 0x99) (See Table) TBT 69 Battery Manager - (Write: 0x16 Read: 0x17) 19 16 14 SMBUS_PCH_CLK SMBUS_SMC_5_G3_SCL 37 40 48 56 40 25 50 64 73 U2800 69 19 16 14 SMBUS_PCH_DATA (Write: 0xFE Read: 0XFF) SMBUS_SMC_5_G3_SDA 37 40 48 56 40 25 50 64 73 69 SMBUS_PCH_CLK 14 16 19 25 40 56 69 SMBUS_PCH_DATA 14 16 19 25 40 56 Margin Control U2201 SMC "3" SMBus S0 Connections (Write: 0x30 Read: 0x31) 69 (* = Multiple options) 74 65 64 62 61 19 16 14 SMBUS_PCH_CLK 36 30 27 18 17 15 13 12 11 8 PP3V3_S0 56 40 25 59 56 45 44 43 42 41 40 39 38 69 Trackpad 19 16 14 SMBUS_PCH_DATA J43 J41 56 40 25 Internal DP Samsung LGD Samsung LGD AUO J4800 Analogix T-con - (Write: 0x7B/0x87 Read: 0x7C/0x88) N Y * Y * SMC R53901 1 R5391 (Write: 0x90 Read: 0x91) 2.0K 2.0K Parade T-con - (0x10-0x1F or 0x30-0x3F) Y N * N * 5% 5% U5000 1/20W 1/20W DVR - (Write: 0x4E Read: 0x4F) Y Y Y Y N MF MF SMBUS_SMC_3_SCL 36 37 40 (MASTER) 201 2 44 64 73 2 201 SMBUS_SMC_3_SDA 36 37 40 44 40 37 36 SMBUS_SMC_3_SCL 44 64 73 C XDP Connectors SMC "2" SMBus S3 Connections 73 64 MAKE_BASE=TRUE 44 40 37 36 SMBUS_SMC_3_SDA 73 64 MAKE_BASE=TRUE C J1800 (MASTER) TBT & MLBBOT, TBD Temp 64 62 58 41 36 33 19 18 15 PP3V3_S3 25 19 16 14 SMBUS_PCH_CLK EMC1414: U5810 69 56 40 (Write: 0x98 Read: 0x99) 25 19 16 14 SMBUS_PCH_DATA 69 56 40 SMC R53701 1 R5371 LIO Finstack Temp SMBUS_SMC_3_SCL 36 37 40 44 64 73 1K 1K 5% 5% J9500 SMBUS_SMC_3_SDA 36 37 40 44 64 73 U5000 1/20W 1/20W MF MF (Write: 0x92 Read 0x93) (MASTER) 201 2 2 201 65 61 40 37 SMBUS_SMC_2_S3_SCL SMBUS_SMC_2_S3_SCL 37 40 61 73 MAKE_BASE=TRUE 65 73 65 61 40 37 SMBUS_SMC_2_S3_SDA SMBUS_SMC_2_S3_SDA 37 40 61 73 MAKE_BASE=TRUE 65 73 B LYNX POINT LP S0 "SMLink 0" Connections B 74 65 64 62 61 36 30 27 18 17 15 13 12 11 8 PP3V3_S0 59 56 45 44 43 42 41 40 39 38 SMC S0 "1" SMBus Connections LYNX POINT LP R53101 1 R5311 74 65 64 62 61 36 30 27 18 17 15 13 12 11 8 PP3V3_S0 59 56 45 44 43 42 41 40 39 38 8.2K 8.2K 5% 5% U0500 1/20W 1/20W MF MF (MASTER) 201 2 2 201 SMC R53601 1 R5361 CPU Temp, Inlet, DDR, BMON THR 2.0K 2.0K 69 14 SML_PCH_0_CLK 5% 5% MAKE_BASE=TRUE U5000 1/20W 1/20W EMC1704-02: U5800 MF MF 69 14 SML_PCH_0_DATA 201 2 MAKE_BASE=TRUE (MASTER) 2 201 (Write: 0x98 Read: 0x99) 73 40 37 32 14 SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SCL 14 32 37 40 43 44 64 69 64 44 43 MAKE_BASE=TRUE 69 73 73 40 37 32 14 SMBUS_SMC_1_S0_SDA SMBUS_SMC_1_S0_SDA 14 32 37 40 43 44 64 69 64 44 43 MAKE_BASE=TRUE 69 73 LYNX POINT LP S0 "SMLink 1" Connections Chipset current PAC1921: U5620 (Write: 0x30 Read: 0x31) 64 69 73 SMBUS_SMC_1_S0_SCL 14 32 37 40 43 44 64 69 73 LYNX POINT LP SMBUS_SMC_1_S0_SDA 14 32 37 40 43 44 A U0500 (Write: 0x88 Read: 0x89) SYNC_MASTER=J41_MLB SYNC_DATE=02/06/2013 A PAGE TITLE 73 69 40 37 32 14 SMBUS_SMC_1_S0_SCL 64 44 43 73 40 37 32 14 SMBUS_SMC_1_S0_SDA ALS SMBus Connections 69 64 44 43 J4002 DRAWING NUMBER SIZE (Write: 0x72 Read 0x73) Apple Inc. <SCH_NUM> D REVISION R SMBUS_SMC_1_S0_SCL 64 69 73 14 32 37 40 43 44 <E4LABEL> SMLink 1 is slave port to SMBUS_SMC_1_S0_SDA 64 69 73 NOTICE OF PROPRIETARY PROPERTY: BRANCH access PCH 14 32 37 40 43 44 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. <BRANCH> THE POSESSOR AGREES TO THE FOLLOWING: PAGE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT 53 OF 121 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET IV ALL RIGHTS RESERVED 40 OF 76 8 7 6 5 4 3 2 1
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