Internal Use Only North/Latin America http://aic.lgservice.com Europe/Africa http://eic.lgservice.com Asia/Oceania http://biz.lgservice.com LED LCD TV SERVICE MANUAL CHASSIS : LD2FF MODEL : 37LT760H 37LT760H-ZA CAUTION BEFORE SERVICING THE CHASSIS, READ THE SAFETY PRECAUTIONS IN THIS MANUAL. P/NO : MFL67659803 (1210-REV00) Printed in Korea CONTENTS CONTENTS . ............................................................................................. 2 SAFETY PRECAUTIONS ......................................................................... 3 SERVICING PRECAUTIONS..................................................................... 4 SPECIFICATION........................................................................................ 6 ADJUSTMENT INSTRUCTION................................................................. 9 TROUBLESHOOTING GUIDE.................................................................. 17 BLOCK DIAGRAM.................................................................................... 26 EXPLODED VIEW .................................................................................. 27 SCHEMATIC CIRCUIT DIAGRAM .............................................................. Copyright © LG Electronics. Inc. All rights reserved. -2- LGE Internal Use Only Only for training and service purposes SAFETY PRECAUTIONS IMPORTANT SAFETY NOTICE Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the Schematic Diagram and Exploded View. It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent Shock, Fire, or other Hazards. Do not modify the original design without permission of manufacturer. General Guidance Leakage Current Hot Check (See below Figure) Plug the AC cord directly into the AC outlet. An isolation Transformer should always be used during the servicing of a receiver whose chassis is not isolated from the AC Do not use a line Isolation Transformer during this check. power line. Use a transformer of adequate power rating as this Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor protects the technician from accidents resulting in personal injury between a known good earth ground (Water Pipe, Conduit, etc.) from electrical shocks. and the exposed metallic parts. Measure the AC voltage across the resistor using AC voltmeter It will also protect the receiver and it's components from being with 1000 ohms/volt or more sensitivity. damaged by accidental shorts of the circuitry that may be Reverse plug the AC cord into the AC outlet and repeat AC voltage inadvertently introduced during the service operation. measurements for each exposed metallic part. Any voltage measured must not exceed 0.75 volt RMS which is corresponds to If any fuse (or Fusible Resistor) in this TV receiver is blown, 0.5 mA. replace it with the specified. In case any measurement is out of the limits specified, there is possibility of shock hazard and the set must be checked and When replacing a high wattage resistor (Oxide Metal Film Resistor, repaired before it is returned to the customer. over 1 W), keep the resistor 10 mm away from PCB. Leakage Current Hot Check circuit Keep wires away from high voltage or high temperature parts. Before returning the receiver to the customer, always perform an AC leakage current check on the exposed metallic parts of the cabinet, such as antennas, terminals, etc., to be sure the set is safe to operate without damage of electrical shock. Leakage Current Cold Check(Antenna Cold Check) With the instrument AC plug removed from AC source, connect an electrical jumper across the two AC plug prongs. Place the AC switch in the on position, connect one lead of ohm-meter to the AC plug prongs tied together and touch other ohm-meter lead in turn to each exposed metallic parts such as antenna terminals, phone jacks, etc. If the exposed metallic part has a return path to the chassis, the measured resistance should be between 1 MΩ and 5.2 MΩ. When the exposed metal has no return path to the chassis the reading must be infinite. An other abnormality exists that must be corrected before the receiver is returned to the customer. Copyright © LG Electronics. Inc. All rights reserved. -3- LGE Internal Use Only Only for training and service purposes SERVICING PRECAUTIONS CAUTION: Before servicing receivers covered by this service 2. After removing an electrical assembly equipped with ES manual and its supplements and addenda, read and follow the devices, place the assembly on a conductive surface such as SAFETY PRECAUTIONS on page 3 of this publication. aluminum foil, to prevent electrostatic charge buildup or expo- NOTE: If unforeseen circumstances create conflict between the sure of the assembly. following servicing precautions and any of the safety precautions 3. Use only a grounded-tip soldering iron to solder or unsolder ES on page 3 of this publication, always follow the safety precau- devices. tions. Remember: Safety First. 4. Use only an anti-static type solder removal device. Some sol- der removal devices not classified as “anti-static” can generate General Servicing Precautions electrical charges sufficient to damage ES devices. 1. Always unplug the receiver AC power cord from the AC power 5. Do not use freon-propelled chemicals. These can generate source before; electrical charges sufficient to damage ES devices. a. Removing or reinstalling any component, circuit board mod- 6. Do not remove a replacement ES device from its protective ule or any other receiver assembly. package until immediately before you are ready to install it. b. Disconnecting or reconnecting any receiver electrical plug or (Most replacement ES devices are packaged with leads electri- other electrical connection. cally shorted together by conductive foam, aluminum foil or c. Connecting a test substitute in parallel with an electrolytic comparable conductive material). capacitor in the receiver. 7. Immediately before removing the protective material from the CAUTION: A wrong part substitution or incorrect polarity leads of a replacement ES device, touch the protective material installation of electrolytic capacitors may result in an explo- to the chassis or circuit assembly into which the device will be sion hazard. installed. 2. Test high voltage only by measuring it with an appropriate CAUTION: Be sure no power is applied to the chassis or circuit, high voltage meter or other voltage measuring device (DVM, and observe all other safety precautions. FETVOM, etc) equipped with a suitable high voltage probe. 8. Minimize bodily motions when handling unpackaged replace- Do not test high voltage by "drawing an arc". ment ES devices. (Otherwise harmless motion such as the 3. Do not spray chemicals on or near this receiver or any of its brushing together of your clothes fabric or the lifting of your assemblies. foot from a carpeted floor can generate static electricity suf- 4. Unless specified otherwise in this service manual, clean ficient to damage an ES device.) electrical contacts only by applying the following mixture to the contacts with a pipe cleaner, cotton-tipped stick or comparable General Soldering Guidelines non-abrasive applicator; 10 % (by volume) Acetone and 90 % 1. Use a grounded-tip, low-wattage soldering iron and appropriate (by volume) isopropyl alcohol (90 % - 99 % strength) tip size and shape that will maintain tip temperature within the CAUTION: This is a flammable mixture. range or 500 °F to 600 °F. Unless specified otherwise in this service manual, lubrication of 2. Use an appropriate gauge of RMA resin-core solder composed contacts in not required. of 60 parts tin/40 parts lead. 5. Do not defeat any plug/socket B+ voltage interlocks with which 3. Keep the soldering iron tip clean and well tinned. receivers covered by this service manual might be equipped. 4. Thoroughly clean the surfaces to be soldered. Use a mall wire- 6. Do not apply AC power to this instrument and/or any of its bristle (0.5 inch, or 1.25 cm) brush with a metal handle. electrical assemblies unless all solid-state device heat sinks Do not use freon-propelled spray-on cleaners. are correctly installed. 5. Use the following unsoldering technique 7. Always connect the test receiver ground lead to the receiver a. Allow the soldering iron tip to reach normal temperature. chassis ground before connecting the test receiver positive (500 °F to 600 °F) lead. b. Heat the component lead until the solder melts. Always remove the test receiver ground lead last. c. Quickly draw the melted solder with an anti-static, suction- 8. Use with this receiver only the test fixtures specified in this type solder removal device or with solder braid. service manual. CAUTION: Work quickly to avoid overheating the circuit CAUTION: Do not connect the test fixture ground strap to any board printed foil. heat sink in this receiver. 6. Use the following soldering technique. a. Allow the soldering iron tip to reach a normal temperature Electrostatically Sensitive (ES) Devices (500 °F to 600 °F) Some semiconductor (solid-state) devices can be damaged eas- b. First, hold the soldering iron tip and solder the strand ily by static electricity. Such components commonly are called against the component lead until the solder melts. Electrostatically Sensitive (ES) Devices. Examples of typical ES c. Quickly move the soldering iron tip to the junction of the devices are integrated circuits and some field-effect transistors component lead and the printed circuit foil, and hold it there and semiconductor “chip” components. The following techniques only until the solder flows onto and around both the compo- should be used to help reduce the incidence of component dam- nent lead and the foil. age caused by static by static electricity. CAUTION: Work quickly to avoid overheating the circuit 1. Immediately before handling any semiconductor component or board printed foil. semiconductor-equipped assembly, drain off any electrostatic d. Closely inspect the solder area and remove any excess or charge on your body by touching a known earth ground. Alter- splashed solder with a small wire-bristle brush. natively, obtain and wear a commercially available discharging wrist strap device, which should be removed to prevent poten- tial shock reasons prior to applying power to the unit under test. Copyright © LG Electronics. Inc. All rights reserved. -4- LGE Internal Use Only Only for training and service purposes IC Remove/Replacement 3. Solder the connections. Some chassis circuit boards have slotted holes (oblong) through CAUTION: Maintain original spacing between the replaced which the IC leads are inserted and then bent flat against the cir- component and adjacent components and the circuit board to cuit foil. When holes are the slotted type, the following technique prevent excessive component temperatures. should be used to remove and replace the IC. When working with boards using the familiar round hole, use the standard technique Circuit Board Foil Repair as outlined in paragraphs 5 and 6 above. Excessive heat applied to the copper foil of any printed circuit board will weaken the adhesive that bonds the foil to the circuit Removal board causing the foil to separate from or "lift-off" the board. The 1. Desolder and straighten each IC lead in one operation by following guidelines and procedures should be followed whenever gently prying up on the lead with the soldering iron tip as the this condition is encountered. solder melts. 2. Draw away the melted solder with an anti-static suction-type At IC Connections solder removal device (or with solder braid) before removing To repair a defective copper pattern at IC connections use the the IC. following procedure to install a jumper wire on the copper pattern Replacement side of the circuit board. (Use this technique only on IC connec- 1. Carefully insert the replacement IC in the circuit board. tions). 2. Carefully bend each IC lead against the circuit foil pad and solder it. 1. Carefully remove the damaged copper pattern with a sharp 3. Clean the soldered areas with a small wire-bristle brush. knife. (Remove only as much copper as absolutely necessary). (It is not necessary to reapply acrylic coating to the areas). 2. carefully scratch away the solder resist and acrylic coating (if used) from the end of the remaining copper pattern. "Small-Signal" Discrete Transistor 3. Bend a small "U" in one end of a small gauge jumper wire and Removal/Replacement carefully crimp it around the IC pin. Solder the IC connection. 1. Remove the defective transistor by clipping its leads as close 4. Route the jumper wire along the path of the out-away copper as possible to the component body. pattern and let it overlap the previously scraped end of the 2. Bend into a "U" shape the end of each of three leads remaining good copper pattern. Solder the overlapped area and clip off on the circuit board. any excess jumper wire. 3. Bend into a "U" shape the replacement transistor leads. 4. Connect the replacement transistor leads to the corresponding At Other Connections leads extending from the circuit board and crimp the "U" with Use the following technique to repair the defective copper pattern long nose pliers to insure metal to metal contact then solder at connections other than IC Pins. This technique involves the each connection. installation of a jumper wire on the component side of the circuit board. Power Output, Transistor Device Removal/Replacement 1. Remove the defective copper pattern with a sharp knife. 1. Heat and remove all solder from around the transistor leads. Remove at least 1/4 inch of copper, to ensure that a hazardous 2. Remove the heat sink mounting screw (if so equipped). condition will not exist if the jumper wire opens. 3. Carefully remove the transistor from the heat sink of the circuit 2. Trace along the copper pattern from both sides of the pattern board. break and locate the nearest component that is directly con- 4. Insert new transistor in the circuit board. nected to the affected copper pattern. 5. Solder each transistor lead, and clip off excess lead. 3. Connect insulated 20-gauge jumper wire from the lead of the 6. Replace heat sink. nearest component on one side of the pattern break to the lead of the nearest component on the other side. Diode Removal/Replacement Carefully crimp and solder the connections. 1. Remove defective diode by clipping its leads as close as pos- CAUTION: Be sure the insulated jumper wire is dressed so the sible to diode body. it does not touch components or sharp edges. 2. Bend the two remaining leads perpendicular y to the circuit board. 3. Observing diode polarity, wrap each lead of the new diode around the corresponding lead on the circuit board. 4. Securely crimp each connection and solder it. 5. Inspect (on the circuit board copper side) the solder joints of the two "original" leads. If they are not shiny, reheat them and if necessary, apply additional solder. Fuse and Conventional Resistor Removal/Replacement 1. Clip each fuse or resistor lead at top of the circuit board hollow stake. 2. Securely crimp the leads of replacement component around notch at stake top. Copyright © LG Electronics. Inc. All rights reserved. -5- LGE Internal Use Only Only for training and service purposes SPECIFICATION NOTE : Specifications and others are subject to change without notice for improvement. 1. Application range 3. Test method This specification is applied to the LCD TV used LD23E 1) Performance: LGE TV test method followed chassis. 2) Demanded other specification - Safety : CE, IEC specification - EMC : CE, IEC 2. Requirement for Test - Wireless : Wireless HD Specification (Option) Each part is tested as below without special appointment. 1) Temperature: 25 °C ± 5 °C(77 °F ± 9 °F), CST: 40 °C ± 5 °C 2) Relative Humidity: 65 % ± 10 % 3) Power Voltage : Standard input voltage (AC 100-240 V~, 50/60 Hz) * Standard Voltage of each products is marked by models. 4) Specification and performance of each parts are followed each drawing and specification by part number in accordance with BOM. 5) The receiver must be operated for about 20 minutes prior to the adjustment. 4. Model General Specification No. Item Specification Remarks 1 Market EU(PAL Market-33Countries) DTV & Analog (Total 33 countries) DTV (MPEG2/4, DVB-T) : 33 countries (Albania/Austria/Belarus/Belgium/Bosnia/Bulgaria/Croatia/ Czech/Estonia/France/Germany/Greece/Hungary/Ireland/ Italy/Kazakhstan/Latvia/Lithuania/Luxembourg/Morocco/ Netherlands/Poland/Portugal/Romania/Russia/Serbia/ Slovakia/Slovenia/Spain/Switzerland/Turkey/UK/Ukraine) DTV (MPEG2/4, DVB-C) : 33 countries (Albania/Austria/Belarus/Belgium/Bosnia/Bulgaria/Croatia/ Czech/Estonia/France/Germany/Greece/Hungary/Ireland/ Italy/Kazakhstan/Latvia/Lithuania/Luxembourg/Morocco/ Netherlands/Poland/Portugal/Romania/Russia/Serbia/ Slovakia/Slovenia/Spain/Switzerland/Turkey/UK/Ukraine) 2 Broadcasting system 1) PAL-BG Analogue 2) PAL-DK VHF : E2 to E12, UHF : E21 to E69, 3) PAL-I/I’ CATV : S1 to S20, HYPER : S21 to S47 4) SECAM L/L’, DK, BG, I 5) DVB-T Digital 6) DVB-C VHF UHF ► DVB-T - Guard Interval(Bitrate_Mbit/s) 1/4, 1/8, 1/16, 1/32 - Modulation : Code Rate QPSK : 1/2, 2/3, 3/4, 5/6, 7/8 Analog : Upper Heterodyne 16-QAM : 1/2, 2/3, 3/4, 5/6, 7/8 3 Receiving system Digital : COFDM, QAM 64-QAM : 1/2, 2/3, 3/4, 5/6, 7/8 ► DVB-C - Symbolrate : 4.0Msymbols/s to 7.2Msymbols/s - Modulation : 16QAM, 64-QAM, 128-QAM and 256-QAM Copyright © LG Electronics. Inc. All rights reserved. -6- LGE Internal Use Only Only for training and service purposes No. Item Specification Remarks Scart jack is Full scart and support 4 Scart Input (1EA) PAL, SECAM ATV/DTV-Out (not support MNT-Out) SVC, Control, Power outlet 5 RS-232C (Selectable 12V/1A or 5V/2A) 6 RGB Input (1EA) RGB-PC Analog (D-SUB 15PIN) HDMI1-DTV HDMI1 : ARC Support(HDMI Version 1.4) 7 HDMI Input (3EA) HDMI2-DTV Support HDCP HDMI3-DTV 8 Audio Input (1EA) RGB/DVI Audio L/R Input 9 SPDIF out (1EA) SPDIF out EMF, DivX HD, 10 USB (2EA) JPEG, MP3, DivX HD For SVC (download) 11 Ethernet Connect(2EA) Ethernet Connect WOL Support 12 CI Slot(1EA) CI EU PPV CH. Support 13 Clock LED Clock LED Clock Display Ext. Speaker out(1EA) Ext. Speaker out Stereo 1W / 8Ω, Variable 14 Ext. Volume control(1EA) Ext. volume control 5. RGB input (PC) No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remark 1 720*400 31.468 70.08 28.321 For only DOS mode Input 848*480 60Hz, 852*480 60Hz 2 640*480 31.469 59.94 25.17 VESA → 640*480 60Hz Display 3 800*600 37.879 60.31 40.00 VESA 4 1024*768 48.363 60.00 65.00 VESA(XGA) 5 1360*768 47.72 59.8 84.75 WXGA 6 1920*1080 66.587 59.93 138.625 WUXGA FHD model Copyright © LG Electronics. Inc. All rights reserved. -7- LGE Internal Use Only Only for training and service purposes 6. HDMI Input 6.1. DTV mode No. Resolution H-freq.(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Proposed 1. 720*480 31.469 / 31.5 59.94 / 60 27.00/27.03 SDTV 480P 2. 720*576 31.25 50 54 SDTV 576P 3. 1280*720 37.500 50 74.25 HDTV 720P 4. 1280*720 44.96 / 45 59.94 / 60 74.17/74.25 HDTV 720P 5. 1920*1080 33.72 / 33.75 59.94 / 60 74.17/74.25 HDTV 1080I 6. 1920*1080 28.125 50.00 74.25 HDTV 1080I 7. 1920*1080 26.97 / 27 231.97 / 24 74.17/74.25 HDTV 1080P FHD model 8. 1920*1080 33.716 / 33.75 29.976 / 30.00 74.25 HDTV 1080P FHD model 9. 1920*1080 56.250 50 148.5 HDTV 1080P FHD model 10. 1920*1080 67.43 / 67.5 59.94 / 60 148.35/148.50 HDTV 1080P FHD model 6.2. PC mode No. Resolution H-freq.(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Proposed 1. 720*400 31.468 70.08 28.321 HDCP 2. 640*480 31.469 59.94 25.17 VESA HDCP 3. 800*600 37.879 60.31 40.00 VESA HDCP 4. 1024*768 48.363 60.00 65.00 VESA(XGA) HDCP 5. 1360*768 47.72 59.8 84.75 WXGA HDCP 6. 1280*1024 63.595 60.0 108.875 SXGA HDCP / FHD model 7. 1920*1080 67.5 60.00 138.625 WUXGA HDCP / FHD model Copyright © LG Electronics. Inc. All rights reserved. -8- LGE Internal Use Only Only for training and service purposes ADJUSTMENT INSTRUCTION 1. Application Range 3.1.3. Adjustment method This spec. sheet applies to LD2FF Chassis applied LCD TV (1) Adjustment method all models manufactured in TV factory. - Don’t need to adjust ADC because there is data in OTP and adjusted initially. 2. Designation 3.2. MAC address D/L, CI+ D/L (1) Because this is not a hot chassis, it is not necessary to 3.2.1. Equipment & Condition use an isolation transformer. However, the use of isolation 1) Play file: keydownload.exe transformer will help protect test instrument. (2) Adjustment must be done in the correct order. 3.2.2. Communication Port connection (3) The adjustment must be performed in the circumstance of 1) Key Write: Com 1,2,3,4 and 115200 (Baudrate) 25 °C ± 5 °C of temperature and 65 % ± 10 % of relative 2) Barcode: Com 1,2,3,4 and 9600 (Baudrate) humidity if there is no specific designation. (4) The input voltage of the receiver must keep AC 100-240 3.2.3. Download process V~, 50/60 Hz. 1) Select the download items. (5) The receiver must be operated for about 5 minutes prior to 2) Mode check: Online Only the adjustment when module is in the circumstance of over 3) Check the test process 15. - DETECT -> MAC -> CI+ 4) Play: START In case of keeping module is in the circumstance of 0 °C, it 5) Check of result: Ready, Test, OK or NG should be placed in the circumstance of above 15 °C for 2 6) Printer Out (MAC Address Label) hours. 3.2.4. Communication Port connection In case of keeping module is in the circumstance of below Connect: PCBA Jig → RS-232C Port== PC → RS-232C Port -20 °C, it should be placed in the circumstance of above 15 °C for 3 hours. [Caution] When still image is displayed for a period of 20 minutes or longer (Especially where W/B scale is strong. Digital pattern 13ch and/or Cross hatch pattern 09ch), there can some afterimage in the black level area. 3. MAIN PCBA Adjustments 3.1. ADC Calibration 3.2.5. Download 3.1.1. Overview ADC adjustment is needed to find the optimum black level and gain in Analog-to-Digital device and to compensate RGB deviation. 3.1.2. Equipment & Condition (1) USB to RS-232C Jig (2) M SPG-925 Series Pattern Generator (MSPG-925FA, pattern - 65) - Resolution : 1080P Comp1 1920*1080 RGB - Pattern : Horizontal 100% Color Bar Pattern - Pattern level : 0.7 ± 0.1 Vp-p - Image Play: Start 3.2.6. Inspection - In INSTART menu, check these keys. Copyright © LG Electronics. Inc. All rights reserved. -9- LGE Internal Use Only Only for training and service purposes 3.3. LAN Inspection 3.5. Model name & Serial number Download 3.3.1. Equipment & Condition 3.5.1. Model name & Serial number D/L ▪ Each other connection to LAN Port of IP Hub and Jig ▪ Press "Power on" key of service remote control. (Baud rate : 115200 bps) ▪ Connect RS232 Signal Cable to RS-232 Jack. ▪ Write Serial number by use RS-232. ▪ Must check the serial number at Instart menu. 3.5.2. Method & notice (1) Serial number D/L is using of scan equipment. (2) Setting of scan equipment operated by Manufacturing Technology Group. 3.3.2. LAN inspection solution (3) Serial number D/L must be conformed when it is produced ▪ LAN Port connection with PCB in production line, because serial number D/L is mandatory by D-book 4.0. ▪ Network setting at MENU Mode of TV(Instart -> menu -> Network Setup) * Manual Download (Model Name and Serial Number) ▪ Setting automatic IP If the TV set is downloaded by OTA or service man, sometimes ▪ Setting state confirmation model name or serial number is initialized.(Not always) → If automatic setting is finished, you confirm IP and MAC It is impossible to download by bar code scan, so It need Address. Manual download. 1) Press the "Instart" key of Adjustment remote control. 2) Go to the menu "7.Model Number D/L" like below photo. 3) Input the Factory model name(ex 42LT760H-ZA) or Serial number like photo. 3.4. LAN PORT INSPECTION(PING TEST) 3.4.1. Equipment setting (1) Play the LAN Port Test PROGRAM. (2) Input IP set up for an inspection to Test Program. *IP Number : 12.12.2.2 Connect SET → LAN port == PC → LAN Port SET PC 4) Check the model name Instart menu. → Factory name displayed. (ex 42LT760H-ZA) 5) C heck the Diagnostics.(DTV country only) → Buyer 3.4.2. LAN PORT inspection(PING TEST) model displayed. (ex 42LT760H-ZA) (1) Play the LAN Port Test Program. (2) Connect each other LAN Port Jack. (3) Play Test (F9) button and confirm OK Message. 3.6. CI+ Key checking method (4) Remove LAN cable. - Check the Section 3.2 Check whether the key was downloaded or not at ‘In Start’ menu. (Refer to below). => Check the Download to CI+ Key value in LGset. Copyright © LG Electronics. Inc. All rights reserved. - 10 - LGE Internal Use Only Only for training and service purposes 3.6.1. Check the method of CI+ Key value 4. Manual Adjustment (1) Check the method on Instart menu * ADC adjustment is not needed because of OTP(Auto ADC (2) Check the method of RS232C Command adjustment) 1) Into the main ass’y mode(RS232: aa 00 00) CMD 1 CMD 2 Data 0 4.1. E DID(The Extended Display Identification A A 0 0 Data)/DDC(Display Data Channel) download 4.1.1. Overview 2) Check the key download for transmitted command It is a VESA regulation. A PC or a MNT will display an optimal (RS232: ci 00 10) resolution through information sharing without any necessity CMD 1 CMD 2 Data 0 of user input. It is a realization of "Plug and Play". C I 1 0 4.1.2. Equipment - Since embedded EDID data is used, EDID download JIG, 3) Result value HDMI cable and D-sub cable are not need. - Normally status for download : OKx - Adjustment remote control - Abnormally status for download : NGx 4.1.3. Download method 3.6.2. Check the method of CI+ key value(RS232) (1) Press "ADJ" key on the Adjustment remote control then 1) Into the main ass’y mode(RS232: aa 00 00) select "12.EDID D/L", By pressing "Enter" key, enter EDID CMD 1 CMD 2 Data 0 D/L menu. A A 0 0 (2) S elect "Start" button by pressing "Enter" key, HDMI1/ HDMI2/ HDMI3/ HDMI4/ RGB are writing and display OK or NG. 2) Check the mothed of CI+ key by command (RS232: ci 00 20) For Analog For HDMI EDID CMD 1 CMD 2 Data 0 D-sub to D-sub DVI-D to HDMI or HDMI to HDMI C I 2 0 3) Result value i 01 OK 1d1852d21c1ed5dcx CI+ Key Value 3.7. WIFI MAC ADDRESS CHECK 4.1.4. EDID DATA (1) Using RS232 Command ▪ HDMI_EDID DATA_2D 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F H-freq(kHz) V-freq.(Hz) 0x00 00 FF FF FF FF FF FF 00 1E 6D ⓐⓓ ⓑ Transmission [A][I][][Set ID][][20][Cr] [O][K][X] or [NG] 0x01 ⓒ 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 0x02 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 0x03 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C (2) Check the menu on in-start 0x04 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30 0x05 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 3A 0x06 3E 1F 53 10 00 0A 20 20 20 20 20 20 ⓓ 0x07 ⓓ 01 ⓔ1 0x00 02 03 26 F1 4E 10 9F 04 13 05 14 03 02 12 20 21 0x01 22 15 01 26 15 07 50 09 57 07 ⓕ 0x02 ⓕ E3 05 00 00 00 1D 80 18 71 1C 16 20 58 2C 0x03 25 00 A0 5A 00 00 00 9E 01 1D 00 80 51 D0 1A 20 0x04 6E 88 55 00 A0 5A 00 00 00 1A 02 3A 80 18 71 38 0x05 2D 40 58 2C 45 00 A0 5A 00 00 00 1E 66 21 50 B0 0x06 51 00 1B 30 40 70 36 00 A0 5A 00 00 00 1E 00 00 0x07 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ⓔ2 ▪ RGB_EDID 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x00 00 FF FF FF FF FF FF 00 1E 6D ⓐ ⓑ 0x01 ⓒ 01 03 68 A0 5A 78 0A EE 91 A3 54 4C 99 26 0x02 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 0x03 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C 0x04 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30 0x05 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 3A 0x06 3E 1E 53 10 00 0A 20 20 20 20 20 20 ⓓ 0x07 ⓓ 00 ⓔ3 Copyright © LG Electronics. Inc. All rights reserved. - 11 - LGE Internal Use Only Only for training and service purposes ▪ Reference 4.2.3. Equipment connection MAP - HDMI1 ~ HDMI3 / RGB - In the data of EDID, bellows may be different by S/W or Co lo r Analyzer Input mode. Probe RS -232C Co m p ut er ⓐ Product ID RS -232C RS -232C HEX EDID Table DDC Function Pat t ern Generat o r Signal Source 0001 01 00 Analog * If TV internal pattern is used, not needed 0001 01 00 Digital ⓑ Serial No: Controlled on production line. 4.2.4. Adj. Command (Protocol) ⓒ Month, Year: Controlled on production line: <Command Format> ex) Monthly : ‘01’ → ‘01’ START 6E A 50 A LEN A 03 A CMD A 00 A VAL A CS STOP Year : ‘2012’ → ‘16’ ⓓ Model Name(Hex): LGTV - LEN: Number of Data Byte to be sent MODEL NAME MODEL NAME(HEX) - CMD: Command LG TV 00 00 00 FC 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 (LG TV) - VAL: FOS Data value - CS: Checksum of sent data ⓔ Checksum(LG TV): Changeable by total EDID data. - A: Acknowledge ⓔ1 ⓔ2 ⓔ3 Ex) [Send: JA_00_DD] / [Ack: A_00_okDDX] HDMI1 43 15 X HDMI2 43 5 X ▪ RS-232C Command used during auto-adjustment. HDMI3 43 F5 X RS-232C COMMAND Explantion [CMD ID DATA] RGB X X 5C wb 00 00 Begin White Balance adjustment wb 00 10 Gain adjustment(internal white pattern) ⓕ Vendor Specific(HDMI) wb 00 1f Gain adjustment completed Input Model name(HEX) wb 00 20 Offset adjustment(internal white pattern) HDMI1 67 03 0C 00 10 00 80 2D wb 00 2f Offset adjustment completed HDMI2 67 03 0C 00 20 00 80 2D End White Balance adjustment wb 00 ff HDMI3 67 03 0C 00 30 00 80 2D (internal pattern disappears ) Ex) wb 00 00 -> Begin white balance auto-adj. 4.2. White Balance Adjustment wb 00 10 -> Gain adj. 4.2.1. Overview ja 00 ff -> Adj. data ▪ W/B adj. Objective & How-it-works jb 00 c0 (1) Objective: To reduce each Panel's W/B deviation ... (2) How-it-works : When R/G/B gain in the OSD is at 192, it ... means the panel is at its Full Dynamic Range. In order to wb 00 1f → Gain adj. completed prevent saturation of Full Dynamic range and data, one *(wb 00 20(Start), wb 00 2f(end)) → Off-set adj. of R/G/B is fixed at 192, and the other two is lowered to wb 00 ff → End white balance auto-adj. find the desired value. (3) Adjustment condition : normal temperature 1) Surrounding Temperature : 25 °C ± 5 °C 2) Warm-up time: About 5 Min 3) Surrounding Humidity : 20 % ~ 80 % 4.2.2. Equipment (1) Color Analyzer: CA-210 (LED Module : CH 14) (2) Adjustment Computer(During auto adj., RS-232C protocol is needed) (3) Adjustment Remote control (4) Video Signal Generator MSPG-925F 720p/216-Gray (Model: 217, Pattern: 78) → Only when internal pattern is not available ▪ Color Analyzer Matrix should be calibrated using CS-1000. Copyright © LG Electronics. Inc. All rights reserved. - 12 - LGE Internal Use Only Only for training and service purposes ▪ Adj. Map (2) O/S Module(AUO, CMI, Sharp,IPS…) Adj. item Command Data Range Default Coordinate (lower caseASCII) (Hex.) (Decimal) Mode Temp ∆uv x y CMD1 CMD2 MIN MAX R Gain j g 00 C0 Cool 0.271 ± 0.002 0.276 ± 0.002 13,000 K 0.0000 G Gain j h 00 C0 Medium 0.287 ± 0.002 0.296 ± 0.002 9,300 K 0.0000 B Gain j i 00 C0 Warm 0.315 ± 0.002 0.332 ± 0.002 6,500 K 0.0000 Cool R Cut G Cut ▪ Standard color coordinate and temperature using CA-210 B Cut (CH 14) - by aging time R Gain j a 00 C0 1) Edge LED models (applied only LGD Module) in LGERS G Gain j b 00 C0 B Gain j c 00 C0 Aging Cool Medium Warm Medium GP2 time X y x y x y R Cut (Min) 269 273 285 293 313 329 G Cut B Cut 1 0-2 279 288 295 308 319 338 R Gain j d 00 C0 2 3-5 278 286 294 306 318 336 G Gain j e 00 C0 3 6-9 277 285 293 305 317 335 Warm B Gain j f 00 C0 4 10-19 276 283 292 303 316 333 R Cut 5 20-35 274 280 290 300 314 330 G Cut 6 36-49 272 277 288 297 312 327 7 50-79 271 275 287 295 311 325 8 80-149 270 274 286 294 310 324 4.2.5. Adjustment method 9 Over 150 269 273 285 293 309 323 (1) Auto WB calibration 1) Set TV in ADJ mode using P-ONLY key(or POWER ON key) 2) Edge LED models (applied only LGD Module) in LGEKR 2) Place optical probe on the center of the display (GUMI) (wintertime) - It need to check probe condition of zero calibration Aging Cool Medium Warm before adjustment. GP2 time X y x y x y 3) Connect RS-232C Cable. (Min) 269 273 285 293 313 329 4) Select mode in ADJ Program and begin a adjustment. 1 281 293 297 313 321 343 338 5) When WB adjustment is complete with OK message, 2 280 290 296 310 320 340 336 adjustment status of pre-set mode(Cool, Medium, Warm) 6) Remove probe and RS-232C cable 3 279 289 295 309 319 339 335 ▪ W/B Adj. must begin as start command “wb 00 00” , and 4 277 286 293 306 317 333 333 finish as end command “wb 00 ff”, and Adj. offset if need. 5 275 282 291 302 315 332 330 6 273 278 289 298 313 328 327 4.2.6. Reference (White balance Adj. coordinate and 7 271 276 287 296 311 326 325 color temperature) 8 270 274 286 294 310 324 324 ▪ Luminance : 204 Gray, 80IRE 9 269 273 285 293 309 323 323 ▪ Standard color coordinate and temperature using CS-1000 (over 26 inch) Coordinate 4.3. Tool Option selection Mode Temp ∆uv ▪ Method : Press "ADJ" key on the Adjustment remote control, x y then select Tool option. Cool 0.269 0.273 13000 K 0.0000 Medium 0.285 0.293 9300 K 0.0000 Warm 0.313 0.329 6500 K 0.0000 ▪ Standard color coordinate and temperature using CA-210(CH 14) (1) LGD Coordinate Mode Temp ∆uv x y Cool 0.269 ± 0.002 0.273 ± 0.002 13,000 K 0.0000 Medium 0.285 ± 0.002 0.293 ± 0.002 9,300 K 0.0000 Warm 0.313 ± 0.002 0.329 ± 0.002 6,500K 0.0000 Copyright © LG Electronics. Inc. All rights reserved. - 13 - LGE Internal Use Only Only for training and service purposes 4.4. Wi-Fi Test (2) Check the sound from the TV Set Step 1) Turn on TV Step 2) Select Network Connection option in Network Menu. Instart menu -> Menu -> Network Setup (3) Check the Sound from the Speaker or using AV & Optic TEST program (It’s connected to MSHG-600) Step 3) Select Start Connection button in Network Connection. * Remark: Inspect in Power Only Mode and check SW version in a master equipment 5. Check Commercial features Mode info. Commercial Feature Step 4) If the system finds any AP like blow PIC, it is working IR DC Ext RJP well. Name inch Power SPK (HDMI Pro:Idiom Out Out(12V) Out interface) LT760H-ZA 32/37/42/47 O O O O O 5.1. External SPK Out 4.5. HDMI ARC Function Inspection 4.5.1. Test equipment - Optic Receiver Speaker - MSHG-600 (SW: 1220 ↑) 5.1.1. Equipment & Condition - HDMI Cable (for 1.4 version) ▪ Jig (Speaker out JIG) or Oscilloscope ▪ Power only mode 4.5.2. Test method (1) Insert the HDMI Cable to the HDMI ARC port from the 5.1.2. Check the speaker out master equipment (HDMI1) 1) Connect the External Speaker : check the sound Connect oscilloscope, you can see this waveform. Copyright © LG Electronics. Inc. All rights reserved. - 14 - LGE Internal Use Only Only for training and service purposes 5.2. IR Out and DC Power Outlet (12V) 6. AUDIO output check (1) Equipment & Condition ▪ Jig (commercial check JIG) 6.1. Audio input condition 1) RF input: Mono, 1 KHz sine wave signal, 100 % Modulation ▪ Special 232C Cable for commercial check Jig 2) CVBS, Component: 1 KHz sine wave signal 0.5 Vrms ▪ Power only mode 3) RGB PC: 1 KHz sine wave signal 0.7 Vrms ▪ PCB mode (instart menu -> menu -> Configuration Setup -> RS232 DC Power Outlet ) 6.2. Specification (2) Check the power out & IR out - commercial check jig Item Min Typ Max Unit Remark 1) Connect each other RS232c port on the Commercial Au dio practical max Output, 9.0 10.0 12.0 W (1) Measurement condition Check JIG L/R (Distortion=10% max 8.5 8.9 9.9 Vrms - EQ/AVL/Clear Voice: Off Output) (2) Speaker (8Ω Impedance) 2) P ress RED Color Button on SVC Remote-control in power only mode (or PCB mode) 3) Check the LED of jig board - +12V LED (OK condition: Turn On) - IR LED (OK condition: blinking) 7. GND and HI-POT Test 7.1. GND & HI-POT auto-check preparation (1) Check the POWER CABLE and SIGNAL CABE insertion condition 7.2. GND & HI-POT auto-check (1) Pallet moves in the station. (POWER CORD / AV CORD is tightly inserted) (2) Connect the AV JACK Tester. (3) Controller (GWS103-4) on. (4) GND Test (Auto) - If Test is failed, Buzzer operates. - If Test is passed, execute next process (Hi-pot test). (3) Check the power out & IR out - mini jig (Remove A/V CORD from A/V JACK BOX) 1) Connect mini jig on RS232c port (5) HI-POT test (Auto) 2) Press RED Color Button on SVC Remote control in - If Test is failed, Buzzer operates. power only mode (or PCB mode) - If Test is passed, GOOD Lamp on and move to next 3) Check the LED of mini jig process automatically. 7.3. Checkpoint (1) Test voltage - GND: 1.5KV/min at 100mA - SIGNAL: 3KV/min at 100mA (2) TEST time: 1 second (3) TEST POINT - GND Test = POWER CORD GND and SIGNAL CABLE GND. - H i-pot Test = POWER CORD GND and LIVE & NEUTRAL. (4) LEAKAGE CURRENT: At 0.5 mArms (4) Pro:Idiom Check 1) Connect the RF Cable 2) Turn to the Pro:Idiom channel (No. 333) 3) Check the video & sound ** Only displayed at “POWER ONLY” mode Copyright © LG Electronics. Inc. All rights reserved. - 15 - LGE Internal Use Only Only for training and service purposes 8. USB S/W Download(Service only) 4) Press the In-start Key on the ADJ remote after at least 1 min of signal reception. Then, select 7.External ADC. (1) Put the USB Stick to the USB socket. (2) Automatically detecting update file in USB Stick. And Press OK or Right Button for going to sub menu. - If your downloaded program version in USB Stick is Low, 5) Press OK in Comp 480i menu it didn't work. But your downloaded version is High, USB 6) Give a 1080p Mode, Horizontal 100% Color Bar Pattern data is automatically detecting.(Download Version High & to Comp1. (MSPG-925FA → Model: 225, Pattern: 65) Power only mode, Set is automatically Download) 7) Press OK in Comp 1080p menu (3) Show the message "Copying files from memory". 8) Perform (6) and (7) in RGB-PC 9) If ADC Comp is successful, “ADC Component Success” is displayed. If ADC calibration is failure, “ADC Component Fail” is displayed. 10) I f ADC calibration is failure, after rechecking ADC pattern or condition, retry calibration 11) I f ADC RGB calibration is successful, “ADC RGB Success” is displayed. If ADC calibration is failure, “ADC RGB Fail” is displayed. 12) If ADC calibration is failure, after recheck ADC pattern or condition, retry calibration 9.2. Manual White balance Adjustment (4) Updating is starting. 9.2.1. Adj. condition and cautionary items (1) Lighting condition in surrounding area surrounding lighting should be lower 10 lux. Try to isolate adj. area into dark surrounding. (2) Probe location: Color Analyzer (CA-210) probe should be within 10 cm and perpendicular of the module surface (80 °~ 100 °) (3) Aging time (5) Updating Completed, The TV will restart automatically. 1) After Aging Start, Keep the Power ON status during 5 (6) If your TV is turned on, check your updated version and Minutes. Tool option. (explain the Tool option, next stage) 2) In case of LCD, Back-light on should be checked using * If downloading version is more high than your TV have, TV no signal or Full-white pattern. can lost all channel data. In this case, you have to channel recover. if all channel data is cleared, you didn’t have a DTV/ 9.2.2. Equipment ATV test on production line. (1) Color Analyzer: CA-210(NCG: CH 9/ WCG: CH12/ LED: CH14) (2) Adj. Computer(During auto adj., RS-232C protocol is needed) * After downloading, have to adjust Tool Option again. (3) Adjust Remote control (1) Push "IN-START" key in service remote control. (4) Video Signal Generator MSPG-925F 720p/216-Gray (2) Select "Tool Option 1" and push "OK" key. (Model: 217, Pattern: 78) (3) Punch in the number. (Each model has their number) 9.2.3. Adjustment (1) Set TV in Adj. mode using POWER ON 9. Optional adjustments (2) Zero Calibrate the probe of Color Analyzer, then place it on the center of LCD module within 10cm of the surface. 9.1. Manual ADC Calibration (3) Press ADJ key → EZ adjust using adj. R/C → 6. White- 9.1.1. Equipment & Condition Balance then press the cursor to the right (Key ►). (1) Adjustment Remote control W hen Key(►) is pressed 216 Gray internal pattern will be (2) 801GF(802B, 802F, 802R) or MSPG925FA Pattern Generator displayed. - Resolution: 480i Comp1(MSPG-925FA: model-209, pattern-65) (4) One of R Gain / G Gain / B Gain should be fixed at 192, - Resolution: 1080p Comp1(MSPG-925FA: model-225, pattern-65) and the rest will be lowered to meet the desired value. - Resolution : 1080p RGB (MSPG-925FA: model-225, pattern-65) (5) Adj. is performed in COOL, MEDIUM, WARM 3 modes of - Pattern : Horizontal 100% Color Bar Pattern color temperature. - Pattern level: 0.7±0.1 Vp-p ▪ If internal pattern is not available, use RF input. In EZ Adj. menu 6.White Balance, you can select one of 2 Test-pattern: 9.1.2. Adjust method ON, OFF. Default is inner(ON). By selecting OFF, (1) ADC 480i/1080p Comp1, RGB 1) Check connected condition of Comp1/RGB cable to the equipment 2) Give a 480i Mode, Horizontal 100% Color Bar Pattern to Comp1. (MSPG-925FA → Model: 209, Pattern: 65) 3) Change input mode as Component1 and picture mode as “Standard” Copyright © LG Electronics. Inc. All rights reserved. - 16 - LGE Internal Use Only Only for training and service purposes TROUBLESHOOTING GUIDE 1. Power-Up Boot Fail Trouble Shooting guide N N Check P2401 All Check power connector and Replace Power Board. Voltage Level (3.5V, 12V, 24V). RL_ON signal OK? Y N Check Q2407 output Check Q2407 application circuit Voltage(12V). Or replace Q2407. Y N Check LVDS Cable. Replace Cable. Y Check LCD Module Control board 2. No OSD Trouble Shooting guide N N Check P2401 All Check power connector and Replace Power Board. Voltage Level (3.5V, 12V, 24V). RL_ON signal OK? Y N Check IC8700 RESET pin. Check switch SW8700. Y N Check X8701 Clock Check X8701 application circuit 10MHz. or Replace X8701. Y N Check IC8700 IIC Check IIC line or replace Communication status. IC8700. Y N Check IR input state of IC8700 Check IR board. 13pin. Y Re-download NEC Micom Copyright © LG Electronics. Inc. All rights reserved. - 17 - LGE Internal Use Only Only for training and service purposes 3. Analog RF Video Trouble Shooting guide Check RF cable & signal. Y N Check TU6500 Pin8. Replace Tuner.. (Video output) Y N N Check tuner 5V power R6513. Check IC2404. Replace IC2404. Y N Check tuner 3.3V power L6502. Replace L6502 Y N Check tuner 1.8V power IC6501 Replace IC6501. 2pin : 1.8V Y N Check MTK LVDS output. Replace IC105. Copyright © LG Electronics. Inc. All rights reserved. - 18 - LGE Internal Use Only Only for training and service purposes 4. Digital RF Trouble Shooting guide Check RF cable & signal. Y N N Check tuner 5V power R6513. Check tuner 5V power R6513. Replace IC2404. Y N Check IIC Signal Replace TU6500. TU6500 Pin#3,4. Y N Check DIF Signal Replace TU6500. TU6500 Pin#10,11. Y N Check X100 and application Replace X100. circuit. Y Replace IC105. Copyright © LG Electronics. Inc. All rights reserved. - 19 - LGE Internal Use Only Only for training and service purposes 5. AV Video Trouble Shooting guide Check input signal format. Is it supported? Y Check AC cable for damage For damage or open conductor. Y Check JK4600 N Can you see the normal Replace JK4600. waveform? Y Check the input of MTK(IC105). Measure waveform at C616 because it’s more easy to check. Can you see the normal waveform? Y This board has big problem because Main chip (MTK) have some troubles. After checking thoroughly all path once again, You should decide to replace MTK or not. Copyright © LG Electronics. Inc. All rights reserved. - 20 - LGE Internal Use Only Only for training and service purposes 6. HDMI Video Trouble Shooting guide Check input signal format. Is it supported? Y Check AC cable for damage For damage or open conductor Y N Check JK3301/JK3302/JK3303 Replace JK3301, JK3302, Can you see the normal waveform? JK3303 Y N Check HDCP key NVRAM(IC100) Replace IC100. Power & I2C signal Y Check the input of MTK(IC105). Measure waveform at R323, R324 because it’s more easy to check. Can you see the normal waveform? Y This board has big problem because Main chip (MTK) have some troubles. After checking thoroughly all path once again, You should decide to replace MTK or not. Copyright © LG Electronics. Inc. All rights reserved. - 21 - LGE Internal Use Only Only for training and service purposes 7. RGB-PC Video Trouble Shooting guide Check input signal format. Is it supported? Y Check AC cable for damage For damage or open conductor. Y N Check JK3603 Replace JK3603. Can you see the normal waveform? Y Check the input of MTK(IC105). Measure waveform at R323, R324 because it’s more easy to check. Can you see the normal waveform? Y This board has big problem because Main chip (MTK) have some troubles. After checking thoroughly all path once again, You should decide to replace MTK or not. Copyright © LG Electronics. Inc. All rights reserved. - 22 - LGE Internal Use Only Only for training and service purposes 8. Analog RF Audio Trouble Shooting guide Check RF cable & signal. Y N Check TU6500 Pin6. Replace Tuner. (SIF output) Y N Check Audio AMP output L5402, Replace L5402, L5403, L5404, L5403, L5404, L5405. L5405. Y N Check IC5400. Replace IC5400. Y Check C352. (SIF signal to IC105) Y Replace IC105. Copyright © LG Electronics. Inc. All rights reserved. - 23 - LGE Internal Use Only Only for training and service purposes 9. AV / RGB-PC Audio in Trouble Shooting guide Check input signal format. Is it supported? Y Check AC cable for damage For damage or open conductor Y N Check JK4600/JK3604 Replace JK4600/JK3604. Can you see the normal waveform? Y Check the input of MTK(IC105). Measure waveform at C610, C611, C319, C320 because it’s more easy to check. Can you see the normal waveform? Y N Check Audio AMP output L5402, Replace L5402, L5403, L5404, L5403, L5404, L5405. L5405. Y This board has big problem because Main chip (MTK) have some troubles. After checking thoroughly all path once again, You should decide to replace MTK or not. Copyright © LG Electronics. Inc. All rights reserved. - 24 - LGE Internal Use Only Only for training and service purposes 10. HDMI Audio in Trouble Shooting guide Check input signal format. Is it supported? Y Check AC cable for damage For damage or open conductor. Y N Check JK3301/JK3302/JK3303. Replace JK3301, JK3302, Can you see the normal waveform? JK3303. Y N Check Audio AMP output L5402, Replace L5402, L5403, L5404, L5403, L5404, L5405. L5405 Y This board has big problem because Main chip (MTK) have some troubles. After checking thoroughly all path once again, You should decide to replace MTK or not. Copyright © LG Electronics. Inc. All rights reserved. - 25 - LGE Internal Use Only Only for training and service purposes Copyright © NAND SYSTEM Flash DDR3 X 4 SYSTEM EEPROM X 1 (16Gb) (2Gb) (256Kb) Rear RF Side USB1 Wi-Fi USB DIF(+/-) Only for training and service purposes USB to Demod CVBS(M) DVB T/C Serial M-Remote CVBS H/N TU HDMI3 SIF CI_Common CI_Parallel_ IN CI Slot USB2 HDMI2 HDMI CI_Parallel_ OUT S/W HDMI1 LG Electronics. Inc. All rights reserved. Magic WOL PHY TS TS_Serial_OUT Chip CLK S/W To LAN Pro:idiom Ethernet M ICOM Ethernet TS_Serial_IN HUB IC - 26 - AUX LAN LGE2112 CLOCK Display (EU Commercial) URAT NEC R ealtek WOL Sub Micom IR&Key RS-232C Video,RGB Video BLOCK DIAGRAM Audio Intelligent Audio Sensor A/V1 SC_ID, FB Full Scart ID,FB DTV/MNT_Vout & Audio out Video, Audio out 51 P (FHD) 37/42/47 RGB, H/V LVDS RGB,H/V 30P(HD) PC- RGB PC Audio RGB PC Audio 32 Ext. Speaker R/L Ext SPK L L/R OUT Audio Ext. SPK AMP Ext. Speaker I2S Out Speaker Vol+/ - Vol Control AMP R SPDIF SPDIF OUT HDCP Rear EEPROM LGE Internal Use Only EXPLODED VIEW IMPORTANT SAFETY NOTICE Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the Schematic Diagram and EXPLODED VIEW. It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards. Do not modify the original design without permission of manufacturer. 400 401 521 810 LV1 540 530 910 550 900 120 200 570 510 * Stand Base + Body 500 * Set + Stand A10 501 A4 A2 300 Copyright © LG Electronics. Inc. All rights reserved. - 27 - LGE Internal Use Only Only for training and service purposes EAX6430790* : LD22* / LC22* EAX6443420* : LT22* / LJ22* / LA22* / LB22* 12pF Crystal&load cap. Crystal Matching Test result X100-*1 27.0MHZ : 27pF -> 20pF -> 24pF 12pF Crystal +3.3V_NORMAL +3.3V_NORMAL X-TAL C113-*1 8pF C115-*1 8pF +3.5V_ST NVRAM Write Protection X100 27MHz R119 50V 12pF Crystal 50V 12pF Crystal MT5369_XTAL_IN MT5369_XTAL_OUT C113 C115 0 - Low : Normal Operation 24pF 24pF R103 R105 IC104 +3.5V_ST - High : Write Protection MTK_JTAG Close to eMMC Flash 4.7K 4.7K OPT M24M01-HRMN6TP JTAG AR100 10K R146 10K R152 MTK_JTAG 1K P100 12507WS-12L (IC8100) R104 MTK_JTAG 4.7K NC VCC 1 8 1 EMMC_CLK OPT R182 R183 JTRST# 2 E1 WP 2 7 2.7K 2.7K R174 3 JTDI 10K E2 SCL IC105 3 6 R136 33 JTMS 4 SCL_NVRAM LGE2112 5 JTCLK VSS SDA 4 5 R137 33 SDA_NVRAM 6 R1030 OPT 33 I2C_SCL4 R143 33 R1031 OPT 33 JTDO 7 AP14 AR18 I2C_SDA4 MTK_JTAG JTCLK JTCK U0TX SOC_TX +3.3V_NORMAL 8 AM14 AP18 JTDI JTDI U0RX SOC_RX AR14 9 JTDO JTDO R144 AR15 AU16 10K 10 JTMS JTMS U1RX MTK_NEC_RX AN14 AT16 JTRST# JTRST U1TX MTK_NEC_TX 11 HDCP_EEPROM_MICRO HDCP EEPROM IC100-*1 24LC16B R145 10K MTK_JTAG R149 10K MTK_JTAG 12 13 OSDA0 OSCL0 AP12 AN12 OSDA0 OSCL0 POWE POOE A35 C33 B34 EMMC_CMD EMMC_DATA[2-7] A0 1 VCC POCE1 8 AP15 D33 +3.3V_NORMAL OSDA1 OSDA1 POCE0 EMMC_DATA[7] A1 2 WP AN15 D29 HDCP_EEPROM_ST 7 OSCL1 OSCL1 PDD7 EMMC_DATA[6] C30 IC100 PDD6 M24C16-R A2 3 SCL EMMC_DATA[5] C101 6 AT34 D30 0.1uF MT5369_XTAL_IN XTALI PDD5 EMMC_DATA[4] 16V VSS 4 SDA AU34 B31 +3.3V_NORMAL NC_1 VCC 5 MT5369_XTAL_OUT XTALO PDD4 1 8 A31 EMMC_DATA[3] AVDD_33SB PDD3 EMMC_DATA[2] NC_2 WC R181 4.7K AK27 B32 2 7 +3.3V_NORMAL R157 AVDD33_XTAL_STB PDD2 C116 AH26 A32 4.7K NC_3 SCL R191 22 AVSS33_XTAL_STB PDD1 3 6 I2C_SCL1 0.1uF C32 OPT PDD0 VSS SDA R192 22 D32 4 5 I2C_SDA1 PARB R178 STRAPPING LED_PWM0 LED_PWM1 OPCTRL3 AVDD_33SB A34 R147 R150 R153 PACLE EMMC_DATA[1] 4.7K 1K 1K 1K AK18 C34 OPT OPT AVDD33_VGA_STB PAALE EMMC_DATA[0] OPT ICE mode + 27M + Serial boot 0 0 0 C117 AK17 C29 EMMC_CLK +3.3V_NORMAL LED_PWM0 0.1uF AVSS33_VGA_STB EMMC_CLK ICE mode + 27M + ROM to Nand boot 0 0 1 LED_PWM1 AM20 ICE mode + 27M + Rom to eMMC boot 0 1 0 OPWRSB R155 OPCTRL3 VDD3V3 10K R148 R151 R154 from eMMC pins (share pins w/s NAND) R1003 100 1K AK23 AM22 OPT 1K 1K AVDD33_PLLGP ORESET Q1001 OPT ICE mode + 27M + ROM to eMMC boot 0 1 1 C118 AM27 OPT AVSS33_PLLGP C MMBT3904(NXP) from SDIO pins 0.1uF AU21 R158 33 IR OPT OIRI B OPT SOC_RESET AJ20 D27 R159 4.7K R1002 AVDD10_LDO FSRC_WR 10K E OPT C107 C108 2.2uF 2.2uF AT21 10V 10V STB_SCL STB_SCL AR21 R172 22 CI_ADDR[0-14] STB_SDA STB_SDA CI_ADDR[0] H32 T34 C114 GPIO0 DEMOD_RST PCM_RST CI_ADDR[1] F37 T32 0.1uF SOC -> Pro:Idiom or CI SLOT GPIO1 DEMOD_TSCLK 16V I2C_1 : AMP, L/DIMMING,HDCP KEY CI_ADDR[2] F36 T36 SOC <- P:I I2C I2C_2 I2C_3 : : T-CON MICOM TS_S_OUT_VAL TS_S_OUT_SYNC CI_ADDR[3] CI_ADDR[4] G37 G36 GPIO2 GPIO3 DEMOD_TSDATA0 DEMOD_TSDATA1 U36 T33 TS_S_IN_0_CLK GPIO4 DEMOD_TSDATA2 TS_S_IN_0_VAL I2C_4 : S/Demod,T2/Demod, LNB TS_S_OUT_DATA CI_ADDR[5] G35 T30 GPIO5 DEMOD_TSDATA3 TS_S_IN_0_SYNC I2C_5 : NVRAM CI_ADDR[6] G34 V33 GPIO6 DEMOD_TSDATA4 TS_S_IN_0_DATA SOC -> Pro:Idiom or CI SLOT CI_ADDR[7] H34 V32 +3.3V_NORMAL I2C_6 : TUNER_MOPLL(T/C,ATV) GPIO7 DEMOD_TSDATA5 R1021 0 CI_ADDR[8] L34 V31 MT5369_MCLKI_SW GPIO8 DEMOD_TSDATA6 CI_ADDR[9] L32 V30 SOC -> CI SLOT GPIO9 DEMOD_TSDATA7 CI_ADDR[10] K33 T35 MT5369_MIVAL_ERR R1022 0 GPIO10 DEMOD_TSSYNC R128 R131 R134 R139 R142 R173 R185 R188 R156 R160 CI_ADDR[11] K32 T31 R164 R177 OPT R1023 0 GPIO11 DEMOD_TSVAL 1.2K 1.2K 2.7K 2.7K 2.7K 2.7K 2.7K 2.7K 2.7K 2.7K R1026 0 MT5369_MISTRT CI_ADDR[12] H33 2.7K 2.7K GPIO12 MT5369_TS_OUT[0-7] CI_ADDR[13] L35 N36 +3.3V_NORMAL GPIO13 CI_INT /PCM_REG STB_SCL R110 33 I2C_SCL1 CI_ADDR[14] K36 T37 GPIO14 CI_TSCLK /PCM_CE1 STB_SDA R111 33 I2C_SDA1 J32 R35 GPIO15 CI_TSDATA0 MT5369_TS_SYNC CI SLOT -> SOC OPCTRL_11_SCL R112 33 I2C_SCL2 R1028 J34 R37 GPIO16 CI_TSSYNC /PCM_WE R113 33 IC106 10K K34 R36 OPCTRL_10_SDA I2C_SDA2 NLASB3157DFT2G /PCM_OE 0 GPIO17 CI_TSVAL R114 33 MT5369_TS_OUT[0] K35 OSCL1 I2C_SCL3 TCLK_SEL GPIO18 R115 33 MT5369_TS_OUT[1] R1024 K37 R34 R1005 0 OSDA1 I2C_SDA3 GPIO19 PVR_TSCLK MT5369_TS_VAL CI SLOT -> SOC R116 33 B1 SELECT +3.3V_NORMAL MT5369_TS_OUT[2] J36 R32 R1006 0 OSCL2 I2C_SCL4 TS_S_OUT_CLK 1 6 GPIO20 PVR_TSVAL CI_A_VS1 R117 33 MT5369_TS_OUT[3] J37 R33 R1007 0 OSDA2 I2C_SDA4 GPIO21 PVR_TSSYNC MT5369_TS_CLK CI SLOT -> SOC R118 33 MT5369_TS_OUT[4] J35 P33 R1008 0 OSCL0 I2C_SCL5 GND VCC GPIO22 PVR_TSDATA0 /PCM_IRQA R121 33 2 5 MT5369_TS_OUT[5] J33 P34 R1001 OSDA0 I2C_SDA5 GPIO23 PVR_TSDATA1 0 /PCM_WAIT CI_DATA[0-7] R122 33 C121 MT5369_TS_OUT[6] G33 OPCTRL_1_SCL I2C_SCL6 GPIO24 B0 A 0.1uF MT5369_TS_OUT[7] H35 N37 +3.3V_NORMAL OPCTRL_0_SDA R123 33 I2C_SDA6 3 4 MT5369_MCLKI MT5369_MCLKI_SW GPIO25 SPI_CLK1 /CI_CD2 CI_DATA[0] H31 P35 GPIO26 SPI_CLK /CI_CD1 CI_DATA[1] F34 N34 GPIO27 SPI_DATA /PCM_IORD R168 R161 CI_DATA[2] E36 N35 R166 4.7K 4.7K GPIO28 SPI_CLE /PCM_IOWR 2.7K OPT CI_DATA[3] N33 OPT GPIO29 OPT R171 OPT CI_DATA[4] P32 AU12 22 R1027 0 GPIO30 OPWM2 PWM_DIM2 CI_DATA[5] M35 AT12 R170 22 GPIO31 OPWM1 PWM_DIM1 CI_DATA[6] M37 AR12 R169 10K GPIO32 OPWM0 A_DIM CI_DATA[7] M33 OPT GPIO33 C120 F35 A37 R197 R198 MT5369_TS_IN[0] GPIO34 SD_D0 1K 2.2uF 1K E35 C35 10V MT5369_TS_IN[1] GPIO35 SD_D1 +3.3V_NORMAL Model Option CI SLOT -> SOC MT5369_TS_IN[2] MT5369_TS_IN[3] E37 N32 GPIO36 GPIO37 SD_D2 SD_D3 A36 B35 PWM1_PULL_DOWN_1K OPT PWM2_PULL_DOWN_1K M34 B36 MT5369_TS_IN[4] GPIO38 SD_CMD M36 B37 MT5369_TS_IN[5] GPIO39 SD_CLK M32 MTK_OPTIC_Tx_IC MTK_DVB_T2_TUNER MTK_3D_DEPTH_IC MTK_Int_FRC/URSA5 MTK_DVB_C2_TUNER MTK_DVB_S_TUNER MT5369_TS_IN[6] GPIO40 SoC L33 MTK_DDR_768MB MTK_FRC3/URSA5 MT5369_TS_IN[7] MTK_CP_BOX NO_FRC internal LG FRC2 Reserved GPIO41 E33 AT11 FRC /USB_OCD2 MTK_FHD MTK_EPI GPIO42 LDM_CS R140 4.7K R135 4.7K R175 4.7K R130 4.7K E32 AU11 R186 4.7K R132 4.7K R125 4.7K R106 4.7K R108 4.7K R189 4.7K R101 4.7K MODEL_OPT_0 0 0 1 1 /USB_OCD1 GPIO43 LDM_CLK L/DIM0_SCLK R1010 100 F32 AR10 WARM_MODE GPIO44 LDM_VSYNC L/DIM0_VS MODEL_OPT_1 0 1 0 1 USB_CTL2 A29 AM9 GPIO45 LDM_DO L/DIM0_MOSI USB_CTL1 D31 AP10 GPIO46 LDM_DI MODEL_OPT_0 C102 C106 C123 C31 C122 /USB2SER_RESET GPIO47 0.1uF 0.1uF 0.1uF 0.1uF R1033 0 E30 MODEL_OPT_1 LAN1_DET GPIO48 HIGH LOW OPT OPT OPT OPT E31 AN22 MODEL_OPT_0 GPIO49 LED_PWM1 LED_PWM1 MODEL_OPT_2 F31 AP21 MODEL_OPT_1 GPIO50 LED_PWM0 LED_PWM0 MODEL_OPT_2 FHD HD E29 MODEL_OPT_3 ERROR_OUT GPIO51 AP9 MODEL_OPT_3 OPTIC NON_OPTIC MODEL_OPT_3 GPIO52 /S2_RESET MODEL_OPT_4 AT9 MODEL_OPT_7 M_RFModule_ISP GPIO53 5V Tolerance MODEL_OPT_4 3D DEPTH 3D_Depth_IC NON_3D_Depth_IC AR9 AU20 MODEL_OPT_5 MODEL_OPT_5 GPIO54 OPCTRL11 OPCTRL_11_SCL SC_ID_SOC AU9 AT20 GASKET9.5T_HEATSINK DDR DDR_768MB DDR_Default GASKET3.5T_HEATSINK MODEL_OPT_5 MODEL_OPT_6 OPCTRL_10_SDA GASKET3.5T_HEATSINK GASKET3.5T_HEATSINK GPIO55 OPCTRL10 GASKET3.5T_HEATSINK MODEL_OPT_6 AN18 OPCTRL9 LAN2_DET M_RFModule_ISP MODEL_OPT_7 MODEL_OPT_6 CP BOX Enable Disable NON_EU AP20 OPCTRL8 SC_DET R193 10K AN23 AM18 MODEL_OPT_7 MDS62110214 MODEL_OPT_8 DSUB_DET MTK_NON_OPTIC_Tx_IC ADIN0_SRV OPCTRL7 MDS62110213 T2 Tuner Support Not Support MDS62110213 MDS62110213 MDS62110213 R176 10K AN24 AN19 R1025 100 ADIN1_SRV OPCTRL6 TCLK_SEL MTK_NON_DVB_T2_TUNER MTK_NON_DVB_C2_TUNER MODEL_OPT_9 MTK_NON_3D_DEPTH_IC MTK_NO_FRC/Int_FRC R162 AP23 AP19 MTK_NON_DVB_S_TUNER MODEL_OPT_8 S Tuner Support 10K M24 Not Support M23 HDMI_CEC M21 M22 ADIN2_SRV OPCTRL5 M20 MTK_NO_FRC/FRC3 MTK_DDR_DEFAULT R163 10K AR23 AR19 R1014 0 OPT MTK_NON_CP_BOX MODEL_OPT_10 MAIN_AMP_RESET ADIN3_SRV OPCTRL4 MTK_NON_EPI MODEL_OPT_9 Reserved Default AU23 AN21 R1015 33 OPT M_RFModule_RESET ADIN4_SRV OPCTRL3 OPCTRL3 MTK_HD AT23 AM19 R1009 R133 4.7K R102 4.7K 0 R107 4.7K R129 4.7K R127 4.7K R109 4.7K R141 4.7K R138 4.7K R184 4.7K R187 4.7K R190 4.7K MODEL_OPT_10 EPI Support Not Support OPC_EN ADIN5_SRV OPCTRL2 EXT_SPK_DET R1016 100 AM24 AN20 /TU_RESET ADIN6_SRV OPCTRL1 OPCTRL_1_SCL AM23 AR20 MODEL_OPT_4 /S2_RESET ADIN7_SRV OPCTRL0 OPCTRL_0_SDA MODEL OPTION 8 is just for CP Box It should not be appiled at MP THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS xxLT760H-UA 2011.09.29 ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MID_MAIN_1 8 Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes PLACE AT JACK SIDE 1608 sizs For EMI C319 10uF R314 16V PC_L_IN PC_L_IN_SOC 0 R300 C300 C314 470K 560pF 100pF OPT 50V 50V OPT OPT C320 1608 sizs For EMI 10uF R336 16V PC_R_IN PC_R_IN_SOC 0 R301 C301 C315 470K 560pF 100pF OPT 50V 50V OPT OPT +5V_NORMAL R308 1.2K R302 OPT C311 180 ARC HDMI_ARC DSUB_VSYNC DSUB_VSYNC_SOC R303 1uF OPT 10V C329 R324 22 82 R309 R325 100K 5pF 2K 50V OPT DSUB_HSYNC OPT DSUB_HSYNC_SOC C330 R323 22 R326 5pF 2K 50V OPT IC105 IC105 LGE2112 LGE2112 CHANGE SYMBOL OPT AG3 R380 0 AA32 AG35 AO3N To NEC & HDMI HDMI_CEC HDMI_CEC HDMI_0_RX_0 D0+_HDMI2_JACK AG4 AG34 AO3P HDMI_0_RX_0B D0-_HDMI2_JACK AG1 AG33 AG37 AO4N DDC_SCL_2_JACK HDMI_0_SCL HDMI_0_RX_1 D1+_HDMI2_JACK AG2 AE33 AG36 AO4P DDC_SCL_3_JACK HDMI_1_SCL HDMI_0_RX_1B D1-_HDMI2_JACK AF3 AC33 AF35 AOCLKN HDMI_2_SCL HDMI_0_RX_2 D2+_HDMI2_JACK AF4 AH32 AF34 AOCLKP DDC_SCL_4_JACK HDMI_3_SCL HDMI_0_RX_2B D2-_HDMI2_JACK AE3 AH35 AO2N HDMI_0_RX_C CK+_HDMI2_JACK AE4 AF33 AH34 AO2P DDC_SDA_2_JACK HDMI_0_SDA HDMI_0_RX_CB CK-_HDMI2_JACK AE1 AD33 AO1N DDC_SDA_3_JACK HDMI_1_SDA F27 AE2 AB33 AE37 MODEL_OPT_8 TCON0 AO1P TXA4N TP301 HDMI_2_SDA HDMI_1_RX_0 D0+_HDMI3_JACK E27 AD1 AH33 AE36 MODEL_OPT_9 TCON1 AO0N DDC_SDA_4_JACK HDMI_3_SDA HDMI_1_RX_0B D0-_HDMI3_JACK F30 AD2 TXA4P TP302 AD35 MODEL_OPT_10 TCON2 AO0P HDMI_1_RX_1 D1+_HDMI3_JACK F29 R304 1K AG31 AD34 TCON3 5V_HDMI_2_JACK HDMI_0_PWR5V HDMI_1_RX_1B D1-_HDMI3_JACK R318 OPT 22 B27 AL3 TXB4N TP303 R305 1K AE31 AC35 MAIN_AMP_MUTE TCON4 AE4N 5V_HDMI_3_JACK HDMI_1_PWR5V HDMI_1_RX_2 D2+_HDMI3_JACK R319 OPT 22 A27 AL4 AC31 AC34 EXT_AMP_MUTE TCON5 AE4P TXB4P HDMI_2_PWR5V HDMI_1_RX_2B D2-_HDMI3_JACK R316 22 B28 AL1 TP304 AH31 AE35 EXT_SPK_VOL+ EXT_SPK_CONTROL 5V_HDMI_4_JACK R307 1K TCON6 AE3N HDMI_3_PWR5V HDMI_1_RX_C CK+_HDMI3_JACK R317 22 EXT_SPK_CONTROL A28 AL2 AE34 EXT_SPK_VOL- TCON7 AE3P HDMI_1_RX_CB CK-_HDMI3_JACK R347 0 OPT C28 AK3 AG32 PANEL_CTL TCON8 AECLKN MTK_HPD HDMI_0_HPD R348 0 OPT D28 AK4 AE32 AB35 INV_CTL TCON9 AECLKP HDMI_HPD_3_JACK HDMI_1_HPD HDMI_2_RX_0 E28 AJ3 AC32 AB34 MODEL_OPT_2 TCON10 AE2N HDMI_2_HPD HDMI_2_RX_0B F28 AJ4 AJ32 AA35 PCM_5V_CTL TCON11 AE2P +1.2V_MTK_AVDD HDMI_HPD_4_JACK HDMI_3_HPD HDMI_2_RX_1 B29 AJ1 AA34 EMMC_RST TCON12 AE1N HDMI_2_RX_1B AJ2 AA24 AA37 AE1P AVDD12_HDMI_0_RX HDMI_2_RX_2 +1.2V_MTK_AVDD AH3 C356 Y24 AA36 AE0N AVDD12_HDMI_1_RX HDMI_2_RX_2B AH4 10uF W24 AC37 AE0P 10V AVDD12_HDMI_2_RX HDMI_2_RX_C AG6 AB24 AC36 AVDD12_LVDS_1 AVDD12_HDMI_3_RX HDMI_2_RX_CB AJ6 AT2 AVDD12_LVDS_2 BO4N TXA4N CI_ADDR[0-14] C350 C354 VDD3V3 AF6 AU2 CH3 AB29 AK35 0.1uF 0.1uF AVDD12_VPLL BO4P TXA4P AVDD33_HDMI_0_RX HDMI_3_RX_0 D0+_HDMI4_JACK AE6 AT1 CI_ADDR[0] VDD3V3 AA29 AK34 AVDD33_LVDSB BO3N TXA3N TP312 AVDD33_HDMI_1_RX HDMI_3_RX_0B D0-_HDMI4_JACK AH7 AU1 CI_ADDR[1] Y29 AJ35 C347 AVDD33_LVDSA BO3P TXA3P TP313 AVDD33_HDMI_2_RX HDMI_3_RX_1 D1+_HDMI4_JACK AR1 CI_ADDR[2] AC29 AJ34 0.1uF BOCLKN TXACLKN TP314 AVDD33_HDMI_3_RX HDMI_3_RX_1B D1-_HDMI4_JACK AJ5 AR2 TXACLKP CH2 CI_ADDR[3] TP315 AJ37 AVSS12_LVDS_2 BOCLKP HDMI_3_RX_2 D2+_HDMI4_JACK AG5 AP1 CI_ADDR[4] C304 C307 AB30 AJ36 AVSS12_LVDS_1 BO2N TXA2N TP316 AVSS33_HDMI_RX_1 HDMI_3_RX_2B D2-_HDMI4_JACK AF5 AP2 CI_ADDR[5] 0.1uF 0.1uF AD30 AJ33 TXA2P TP317 AVSS12_VPLL BO2P CI_ADDR[6] AVSS33_HDMI_RX_2 HDMI_3_RX_C CK+_HDMI4_JACK AE5 AN1 AF31 AK33 AVSS33_LVDSB BO1N TXA1N TP318 AVSS33_HDMI_RX_3 HDMI_3_RX_CB CK-_HDMI4_JACK AH5 AN2 CH1 CI_ADDR[7] AF32 AVSS33_LVDSA BO1P TXA1P TP319 AVSS33_HDMI_RX_4 AM3 CI_ADDR[8] BO0N TXA0N TP320 AG7 AM4 CI_ADDR[9] C36 REXT_VPLL BO0P TXA0P TP321 USB_DP1 USB_DP_P0 CI_ADDR[10] USB2 W/O HUB C37 R343 TP322 USB_DM1 USB_DM_P0 24K AT6 CI_ADDR[11] BE4N TXB4N TP323 USB Port was changed !!!! 1% AU6 CI_ADDR[12] D36 BE4P TXB4P TP324 USB_DP2 USB_DP_P1 AP6 CI_ADDR[13] USB1 W/ HUB D37 BE3N TXB3N TP325 USB_DM2 USB_DM_P1 AR6 CI_ADDR[14] BE3P TXB3P TP326 AP5 AT13 BECLKN TXBCLKN WIFI_DP USB_DP_P2 AR5 AU13 BECLKP TXBCLKP WIFI_DM USB_DM_P2 AT4 BE2N TXB2N AT14 BE2P AU4 TXB2P CH6 USB2SER_DP USB_DP_P3 SC_R_IN_SOC AP4 VDD3V3 AU14 BE1N TXB1N USB2SER_DM USB_DM_P3 SC_L_IN_SOC AR4 CH5 For PCB Pattern BE1P TXB1P AP3 D35 BE0N TXB0N AP13 AVDD33_USB_P0P1 BE0P AR3 TXB0P CH4 SCART_ROUT_SOC For PCB Pattern AVDD33_USB_P2P3 SCART_LOUT_SOC C302 CI_DATA[0-7] AU37 AN35 0.1uF D34 AIN0_R_AADC AR0_ADAC AVSS33_USB_P1 AU35 AN34 EXT_SPK_ROUT_MAIN AR13 AIN0_L_AADC AL0_ADAC AVSS33_USB_P2 R311 30K AT35 CI_DATA[0] PC_R_IN_SOC EXT_SPK_LOUT_MAIN TP338 AIN1_R_AADC CI_DATA[1] R310 30K AT37 AM32 W35 AT18 PC_L_IN_SOC AIN1_L_AADC AR1_ADAC TP339 PCIE11_TXP TXVP_0 EPHY_TDP AU36 AM34 CI_DATA[2] W34 AU18 AIN2_R_AADC AL1_ADAC TP340 +1.2V_MTK_AVDD PCIE11_TXN TXVN_0 EPHY_TDN AP34 CI_DATA[3] Y34 AIN2_L_AADC TP341 PCIE11_RXN AT36 AM37 CI_DATA[4] Y35 AU17 AIN3_R_AADC AR2_ADAC TP342 PCIE11_RXP RXVN_1 EPHY_RDN AR37 AM33 CI_DATA[5] VDD3V3 C316 AT17 AIN3_L_AADC AL2_ADAC TP343 RXVP_1 EPHY_RDP AR33 CI_DATA[6] 0.1uF U24 TP344 AIN4_R_AADC CI_DATA[7] AVDD12_PCIE11 AP32 AM36 1.2K R376 1.2K R378 V24 AN16 AIN4_L_AADC AR3_ADAC TP345 AVDD33_PCIE11 PHYLED1 EPHY_ACTIVITY AR36 AM35 1.2K R377 1.2K R379 C308 AM16 AIN5_R_AADC AL3_ADAC 0.1uF PHYLED0 EPHY_LINK AP37 C398 C399 C3001 W30 AIN5_L_AADC C397 1200pF 1200pF AVSS12_PCIE11 AR35 AG30 1200pF 1200pF AD15 24K R315 AIN6_R_AADC AVDD33_DAC REXT AP36 AF30 W36 +1.2V_MTK_AVDD AIN6_L_AADC AVDD33_DAC1 DAC_3V3 PCIE11_REFCKN W37 AD14 PCIE11_REFCKP AVDD12_REC C321 VDD3V3 VDD3V3 AVSS33_DAC AK30 C365 C380 SPDIF_OUT PLACE AT JACK SIDE AE30 AD16 10uF AVSS33_DAC1 0.01uF 0.1uF AVDD33_COM 10V AL31 ARC AD17 TUNER_SIF C305 C362 AVDD33_AADC AVDD33_LD C328 AJ28 Y33 L300 1uF 0.1uF SC_ID_SOC 0.1uF AVSS33_AADC ALIN DSUB_R+ TP354 25V AR16 AL16 ASPDIF0 BLM15BD121SN1 /CI_CD2 TP355 AVSS33_LD AJ27 Y32 C333 AL15 VMID_AADC ASPDIF1 R322 /CI_CD1 TP356 AVSS33_COM AR11 R366 100 47pF 75 D301 AL14 AOBCK AUD_SCK 50V /PCM_IORD TP357 AVSS12_REC C352 0.01uF AN28 AP11 R367 100 ADLC 5S 02 015 MPXP AOLRCK AUD_LRCK 5.5V /PCM_IOWR TP358 C312 AM12 R368 100 R339 AOMCLK AUD_MASTER_CLK C358 C363 AM10 R371 100 PCM_RST TP307 2.2K AUD_LRCH 0.01uF 1uF AOSDATA4 /PCM_REG OPT AM11 TP308 33pF 50V 25V AOSDATA3 C387 C389 C393 C396 AN11 Don’t use as GPIO /PCM_CE1 TP309 22pF 22pF 22pF 33pF L301 R346 0 R334 51 AOSDATA2 IF_P AN10 OPT OPT OPT OPT DSUB_G+ C336 1uF AOSDATA1 /PCM_WE AN9 BLM15BD121SN1 TP311 10V AOSDATA0 C335 R321 /PCM_OE Close to Tuner C309 47pF D300 TP359 OPT Close to MT5369 75 AU32 AN25 50V ADLC 5S 02 015 ADCINP_DEMOD HSYNC DSUB_HSYNC_SOC R331 0 C337 1uF R335 51 AT32 AM25 5.5V IF_N ADCINN_DEMOD VSYNC DSUB_VSYNC_SOC AR25 0.01uF C366 100 R356 10V VDD3V3 RP C310 AD22 AR24 0.01uF C367 100 R357 AVDD33_DEMOD GP L304 +1.2V_MTK_AVDD C364 AU24 0.01uF C368 100 R358 /PCM_WAIT TP364 BP DSUB_B+ 0.1uF AP24 0.01uF C369 100 R359 33pF BLM15BD121SN1 SC_R_IN_SOC TP365 COM AL27 AT24 1500pF C370 C334 SC_L_IN_SOC C353 AVDD12_DEMOD SOG R320 TP366 C351 AR22 47pF D302 10uF 75 SC_CVBS_IN_SOC TP367 0.1uF VGA_SDA RGB_DDC_SDA 50V ADLC 5S 02 015 10V AM28 AP22 AVSS33_DEMOD VGA_SCL RGB_DDC_SCL 5.5V SC_COM_SOC AJ26 TP368 R332 10K R342 10K AVSS12_DEMOD SC_G_SOC TP369 IF_AGC AT26 COM1 SC_COM_SOC SC_R_SOC TP370 Close to Tuner 0.047uF AR26 C341 PB1P SC_G_SOC SC_B_SOC TP371 0.047uF C355 AP26 PR1P SC_R_SOC SC_FB_SOC TP372 U35 AU26 IF_AGC Y1P SC_B_SOC DTV/MNT_V_OUT_SOC TP373 U34 AP25 For PCB Pattern C333 / C334 / C335 MTK Recommend : 10 pF SC_FB_SOC Close to MT5369 TP300 RF_AGC SOY1 AU28 SCART_ROUT_SOC TP374 COM0 SCART_LOUT_SOC TP375 AP31 AT28 LOUTN PB0P AN30 AR28 LOUTP PR0P PCM_5V_CTL TP377 AP27 Y0P SC_DET V35 AR27 TP378 OSCL2 OSCL2 SOY0 V34 OSDA2 OSDA2 OPT AU30 0 R349 VDACX_OUT AP28 AP29 0 R350 SC0 VDACY_OUT DTV/MNT_V_OUT_SOC AR29 SC_CVBS_IN_SOC SY0 VDD3V3 AD20 AVDD33_VDAC_BG AT30 AD21 For PCB Pattern CVBS3P AVDD33_VDAC AR30 CVBS2P R340 100 C359 0.047uF AR31 AD19 TU_CVBS CVBS1P AVDD12_RGB AN29 +1.2V_MTK_AVDD CVBS0P C361 1uF AP30 CVBS_COM AJ22 VDD3V3 AVSS33_VDAC_BG C382 AK24 AJ21 AVDD33_CVBS_1 AVSS12_RGB 0.1uF AK25 AL24 AVDD33_CVBS_2 AVSS33_VDAC AL25 AVSS33_CVBS_1 AM26 AVSS33_CVBS_2 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS xxLT760H-UA 2011.09.29 ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MID_MAIN_2 9 Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes +3.3V_NORMAL VDD3V3 +1.2V_MTK_CORE 5600mA 60mA L500 BLM18PG121SN1D IC105 C524 C506 C505 C529 C532 C535 LGE2112 IC105 C500 C503 C510 C504 10uF 10uF 10uF 0.1uF 0.1uF 0.1uF 10uF 10uF 0.1uF 2.2uF LGE2112 +1.2V_MTK_CORE +1.2V_MTK_CORE AR7 AC22 VCCK_43 VCCK_31 R2 R6 AT7 AC23 DVSS_51 DVSS_55 VCCK_45 VCCK_32 R3 R20 AU7 AD24 DVSS_52 DVSS_62 VCCK_47 VCCK_36 J4 T20 AP8 P23 DVSS_37 DVSS_73 VCCK_42 VCCK_8 R4 U20 AR8 R24 DVSS_53 DVSS_83 +1.2V_MTK_CORE VCCK_44 VCCK_10 Y4 V20 AT8 T24 DVSS_107 DVSS_92 VCCK_46 VCCK_12 F5 W20 AU8 AC24 DVSS_20 DVSS_104 VCCK_48 VCCK_33 J5 Y20 AM7 AC21 DVSS_38 DVSS_117 VCCK_37 VCCK_30 R5 AA20 C539 C543 C546 C548 C550 C552 C553 AN7 P20 DVSS_54 DVSS_127 VCCK_39 VCCK_7 Y5 AB20 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF AP7 AC20 DVSS_108 DVSS_137 VCCK_41 VCCK_29 W5 G16 AM8 P19 DVSS_95 DVSS_29 VCCK_38 VCCK_6 L7 R21 AN8 AC18 DVSS_44 DVSS_63 VCCK_40 VCCK_27 M7 T21 P14 P18 DVSS_46 DVSS_74 VCCK_1 VCCK_5 R7 U21 R14 AC17 DVSS_56 DVSS_84 VCCK_9 VCCK_26 AA5 V21 T14 P17 DVSS_120 DVSS_93 VDD3V3 VCCK_11 VCCK_4 AB5 W21 AVDD_33SB U14 AD18 DVSS_130 DVSS_105 VCCK_13 VCCK_34 K7 Y21 V14 AD23 DVSS_43 DVSS_118 L501 VCCK_14 VCCK_35 U7 AA21 BLM18PG121SN1D W14 DVSS_77 DVSS_128 VCCK_16 VDD3V3 W7 AB21 Y14 DVSS_97 DVSS_138 VCCK_18 E9 R22 C509 C501 AA14 DVSS_13 DVSS_64 10uF +1.2V_MTK_CORE +1.2V_MTK_AVDD VCCK_20 E8 T22 0.1uF AB14 AL9 DVSS_12 DVSS_75 10V VCCK_22 VCC3IO_B_4 F9 U22 L502 AC14 AK10 DVSS_22 DVSS_85 BLM18PG121SN1D VCCK_23 VCC3IO_B_2 G14 V22 AC19 AK9 DVSS_28 DVSS_94 VCCK_28 VCC3IO_B_1 J6 W22 P15 AK11 DVSS_39 DVSS_106 C525 VCCK_2 VCC3IO_B_3 R15 Y22 AC15 H29 DVSS_57 DVSS_119 10uF VCCK_24 VCC3IO_A_5 T15 AA22 P16 J29 DVSS_68 DVSS_129 VCCK_3 VCC3IO_A_7 U15 AB22 AC16 H30 DVSS_78 DVSS_139 VCCK_25 VCC3IO_A_6 V15 R23 V23 J30 DVSS_87 DVSS_65 VCCK_15 VCC3IO_A_8 W15 T23 W23 G31 DVSS_99 DVSS_76 VCCK_17 VCC3IO_A_3 Y15 U23 Y23 G32 DVSS_112 DVSS_86 VCCK_19 VCC3IO_A_4 AA15 AB23 AA23 F33 DVSS_122 DVSS_140 VCCK_21 VCC3IO_A_2 AB15 W6 E34 DVSS_132 DVSS_96 VCC3IO_A_1 H11 G17 DVSS_34 DVSS_30 R16 F25 DVSS_58 DVSS_27 T16 Y6 DVSS_69 DVSS_109 U16 E21 DVSS_79 DVSS_17 +5V_NORMAL DAC_3V3 V16 F21 DVSS_88 DVSS_25 W16 L8 IC501 DVSS_100 DVSS_45 Y16 T7 AP1117E33G-13 DVSS_113 DVSS_66 AA16 D11 DVSS_123 DVSS_7 AB16 E11 INADJ/GND DVSS_133 DVSS_14 R17 D12 OUT DVSS_59 DVSS_8 POWER_ON/OFF1 T17 E22 DVSS_70 DVSS_18 TP500 C526 U17 F22 10uF DVSS_80 DVSS_26 V17 G25 10V DVSS_89 DVSS_33 Y17 AB19 DVSS_114 DVSS_136 T18 AA19 DVSS_71 DVSS_126 V18 P22 DVSS_90 DVSS_49 Y18 W19 DVSS_115 DVSS_103 R500 T19 U19 1 DVSS_72 DVSS_82 V19 R19 DVSS_91 DVSS_61 Y19 Y7 DVSS_116 DVSS_110 C540 C544 W17 AB18 10uF 0.1uF DVSS_101 DVSS_135 AA17 AA18 10V 16V DVSS_124 DVSS_125 AB17 W18 DVSS_134 DVSS_102 R18 U18 DVSS_60 DVSS_81 AB6 AA7 DVSS_131 DVSS_121 H19 N22 DVSS_35 DVSS_47 H22 T8 DVSS_36 DVSS_67 J11 W8 DVSS_40 DVSS_98 J12 Y8 DVSS_41 DVSS_111 J22 E7 DVSS_42 DVSS_11 F8 DVSS_21 +3.3V_NORMAL +3.3V_NORMAL EMMC_VCCQ 3.3V_EMMC L504 L506 BLM18PG121SN1D BLM18PG121SN1D C512 C522 0.1uF 0.1uF 16V 16V DECAP FOR SOC (HIDDEN - UCC) +1.2V_MTK_CORE +1.2V_MTK_CORE C514 C520 C527 C531 C537 C545 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF +1.5V_DDR +1.5V_DDR C508 C523 C533 C536 C547 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS xxLT760H-UA 2011.09.29 ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MID_MAIN_3 10 Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes PLACE AT JACK SIDE R610 51K SC_ID SC_ID_SOC 1/16W 1% R613 10K READY FOR FILTER (EMI) R611 SC_CVBS_IN SC_CVBS_IN_IF 120-ohm C607 R604 C601 75 10pF 100pF 1% OPT SC_FB SC_FB_SOC R609 R608 22 75 1% PLACE AT MAIN SOC SIDE R623 100 C615 0.01uF SC_R SC_R_SOC C604 R605 10pF 75 1% R622 100 C614 0.01uF SC_G SC_G_SOC C605 R606 10pF 75 1% R620 100 C612 0.01uF SC_COM_SOC R621 100 C613 0.01uF SC_B SC_B_SOC R607 75 1% C606 10pF PLACE AT IC8602 R617 100 C616 0.047uF SC_CVBS_IN_IF SC_CVBS_IN_SOC +12V OPT R630 R632 100K 15K R618 SCART_ROUT_SOC SCART_Rout 0 +12V OPT R627 R631 330pF OPT 100K 50V R628 100K 15K R619 R633 SCART_LOUT_SOC SCART_Lout 0 OPT R603 R629 330pF 100K 50V READY FOR FILTER (EMI) C610 10uF 16V R614 0 SC_L_IN SC_L_IN_SOC R625 C608 1/16W 30K 100pF 5% R601 C602 50V 470K 330pF OPT 50V OPT C611 10uF 16V R624 0 SC_R_IN SC_R_IN_SOC R626 C609 1/16W R602 30K 100pF 5% 470K C603 50V OPT 330pF 50V OPT READY FOR FILTER (EMI) R600 R616 R615 0 DTV/MNT_V_OUT_SOC C600 C617 DTV/MNT_V_OUT 75 75 1% 1% 220pF 220pF OPT OPT TU_CVBS TP600 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS MID_MAIN_SCART 2011.11.21 ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 11 Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes +1.5V_DDR IC701 IC703 H5TQ2G63BFR-PBC H5TQ2G63BFR-PBC A_RVREF2 C703 C701 +1.5V_DDR C750 C752 C754 C756 C758 A_RVREF4 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 1uF 10uF ARA[0-13] 10V ARA[0-13] +1.5V_DDR ARA[0] ARA[0] N3 M8 M8 N3 A0 VREFCA A_RVREF2 VREFCA A0 ARA[1] ARA[1] P7 C735 P7 A1 R720 0.1uF @optio A1 ARA[2] P3 A_RVREF3 1K A_RVREF1 P3 ARA[2] 1% A_RVREF1 C713 A2 A2 ARA[3] ARA[3] N2 H1 R706 0.1uF H1 N2 1K ARA[4] P8 A3 VREFDQ 1% VREFDQ A3 ARA[4] P8 A4 1% 1% A4 ARA[5] ARA[5] P2 240 R721 P2 A5 R716 1K C736 R710 240 A5 ARA[6] ARA[6] R8 L8 1% 0.1uF L8 R8 A6 ZQ +1.5V_DDR R707 ZQ A6 ARA[7] R2 1K C714 R2 ARA[7] +1.5V_DDR 1% +1.5V_DDR ARA[8] A7 0.1uF A7 ARA[8] T8 T8 A8 A8 ARA[9] ARA[9] R3 B2 B2 R3 A9 VDD_1 C704 VDD_1 A9 ARA[10] ARA[10] L7 D9 C745 C751 C753 C755 C757 C702 D9 L7 +1.5V_DDR 10uF A10/AP VDD_2 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 1uF VDD_2 A10/AP ARA[11] ARA[11] R7 G7 10V +1.5V_DDR G7 R7 A11 VDD_3 VDD_3 A11 ARA[12] ARA[12] N7 K2 K2 N7 A12/BC VDD_4 VDD_4 A12/BC ARA[13] T3 K8 A_RVREF3 C733 K8 T3 ARA[13] A13 VDD_5 R718 0.1uF A_RVREF4 VDD_5 A13 N1 1K C715 N1 VDD_6 1% R708 0.1uF VDD_6 M7 N9 1K N9 M7 A15 VDD_7 1% VDD_7 A15 R1 R1 VDD_8 VDD_8 M2 R9 R719 R9 M2 ARBA0 BA0 VDD_9 1K C734 VDD_9 BA0 ARBA0 N8 1% R709 N8 ARBA1 0.1uF 1K C716 ARBA1 ARCLK1 BA1 BA1 M3 1% 0.1uF M3 ARBA2 BA2 BA2 ARBA2 ARCLK0 A1 A1 VDDQ_1 VDDQ_1 J7 A8 A8 J7 R714 CK VDDQ_2 VDDQ_2 CK R712 100 K7 C1 C1 K7 100 5% CK VDDQ_3 VDDQ_3 CK 5% K9 C9 C9 K9 ARCKE CKE VDDQ_4 VDDQ_4 CKE ARCKE D2 D2 VDDQ_5 /ARCLK0 /ARCLK1 L2 VDDQ_5 E9 IC105 E9 L2 /ARCS VDDQ_6 CS /ARCS K1 CS VDDQ_6 F1 LGE2112 F1 K1 ARODT ODT VDDQ_7 VDDQ_7 ODT ARODT J3 H2 H2 J3 /ARRAS +1.5V_DDR /ARRAS RAS VDDQ_8 IC701-*3 IC701-*2 IC701-*1 VDDQ_8 RAS K3 H9 H5TQ2G63DFR-PBC K4B2G1646C-HCK0 NT5CB128M16BP-DI H9 K3 /ARCAS CAS VDDQ_9 IC703-*2 VDDQ_9 CAS /ARCAS IC703-*1 IC703-*3 L3 NT5CB128M16BP-DI K4B2G1646C-HCK0 AC1 C19 L3 /ARWE WE H5TQ2G63DFR-PBC DDRV_44 ARDQM0 ARDQM0 N3 M8 N3 M8 M8 N3 WE /ARWE J1 AC2 C21 P7 A0 VREFCA P7 A0 VREFCA VREFCA A0 P7 J1 NC_1 N3 M8 DDRV_45 ARDQS0 ARDQS0 A1 P3 A1 P3 A1 P3 NC_1 T2 J9 N3 A0 VREFCA M8 A0 VREFCA N3 A0 VREFCA M8 A3 B21 N2 A2 H1 N2 A2 H1 H1 A2 N2 J9 T2 ARREST RESET NC_2 P7 A1 P7 A1 P7 A1 DDRV_1 ARDQS0 /ARDQS0 ARDQ[0-7] P8 A3 VREFDQ P8 A3 VREFDQ VREFDQ A3 P8 NC_2 RESET ARREST L1 P3 A2 P3 A2 P3 A2 A4 C23 P2 A4 P2 A4 A4 P2 L1 NC_3 N2 A3 VREFDQ H1 N2 P8 A3 VREFDQ H1 N2 A3 VREFDQ H1 DDRV_2 ARDQ0 A5 R8 A5 L8 R8 A5 L8 L8 R8 NC_3 L9 P8 A4 A4 P8 A4 B4 B17 R2 A6 ZQ R2 A6 ZQ ZQ A6 R2 L9 NC_4 P2 A5 P2 R8 A5 L8 P2 A5 DDRV_5 ARDQ1 A7 T8 A7 T8 A7 T8 NC_4 F3 T7 R8 A6 ZQ L8 A6 ZQ R8 A6 ZQ L8 C4 D23 R3 A8 B2 R3 A8 B2 B2 A8 R3 T7 F3 ARDQS2 DQSL NC_6 ARA[14] R2 A7 R2 A7 R2 A7 DDRV_8 ARDQ2 L7 A9 VDD_1 D9 L7 A9 VDD_1 D9 D9 VDD_1 A9 L7 ARA[14] NC_6 DQSL ARDQS0 G3 T8 A8 T8 A8 T8 A8 D4 C17 R7 A10/AP VDD_2 G7 R7 A10/AP VDD_2 G7 G7 VDD_2 A10/AP R7 G3 /ARDQS2 DQSL R3 A9 VDD_1 B2 R3 A9 VDD_1 B2 R3 A9 VDD_1 B2 DDRV_10 ARDQ3 N7 A11 VDD_3 K2 N7 A11 VDD_3 K2 K2 VDD_3 A11 N7 DQSL /ARDQS0 L7 A10/AP VDD_2 D9 L7 A10/AP VDD_2 D9 L7 A10/AP VDD_2 D9 B3 D24 A12/BC VDD_4 A12/BC VDD_4 VDD_4 A12 R7 G7 R7 G7 R7 G7 T3 K8 T3 A13 VDD_5 K8 K8 VDD_5 NC_6 T3 N7 A11 VDD_3 K2 N7 A11 VDD_3 K2 A11 VDD_3 DDRV_4 ARDQ4 A13 VDD_5 N1 N1 N1 C7 A9 A12 VDD_4 A12/BC VDD_4 N7 A12/BC VDD_4 K2 C3 C16 M7 VDD_6 N9 M7 VDD_6 N9 N9 VDD_6 M7 A9 C7 ARDQS3 DQSU VSS_1 T3 NC_6 VDD_5 K8 T3 A13 VDD_5 K8 T3 A13 VDD_5 K8 DDRV_7 ARDQ5 NC_5 VDD_7 R1 NC_5 VDD_7 R1 R1 VDD_7 NC_5 VSS_1 DQSU ARDQS1 B7 B3 VDD_6 N1 VDD_6 N1 VDD_6 N1 AC3 C24 M2 VDD_8 R9 M2 VDD_8 R9 R9 VDD_8 M2 B3 B7 /ARDQS3 DQSU VSS_2 M7 NC_5 VDD_7 N9 M7 NC_5 VDD_7 N9 M7 NC_5 VDD_7 N9 DDRV_46 ARDQ6 N8 BA0 VDD_9 N8 BA0 VDD_9 VDD_9 BA0 N8 VSS_2 DQSU /ARDQS1 E1 VDD_8 R1 VDD_8 R1 VDD_8 R1 AC4 D15 M3 BA1 M3 BA1 BA1 M3 E1 VSS_3 M2 BA0 VDD_9 R9 M2 N8 BA0 VDD_9 R9 M2 BA0 VDD_9 R9 DDRV_47 ARDQ7 BA2 BA2 A1 BA2 A1 A1 VSS_3 E7 G8 N8 BA1 BA1 N8 BA1 J7 VDDQ_1 A8 J7 VDDQ_1 A8 A8 VDDQ_1 J7 G8 E7 ARDQM2 DML VSS_4 M3 BA2 M3 BA2 M3 BA2 K7 CK VDDQ_2 C1 K7 CK VDDQ_2 C1 C1 VDDQ_2 CK K7 VSS_4 DML ARDQM0 D3 J2 VDDQ_1 A1 VDDQ_1 A1 VDDQ_1 A1 G10 D21 K9 CK VDDQ_3 C9 K9 CK VDDQ_3 C9 C9 VDDQ_3 CK K9 J2 D3 ARDQM3 DMU VSS_5 J7 CK VDDQ_2 A8 J7 CK VDDQ_2 A8 J7 CK VDDQ_2 A8 TP700 MEMTP ARDQM1 ARDQM1 CKE VDDQ_4 D2 CKE VDDQ_4 D2 D2 VDDQ_4 CKE VSS_5 DMU ARDQM1 J8 K7 CK VDDQ_3 C1 K7 CK VDDQ_3 C1 K7 CK VDDQ_3 C1 G9 B20 VDDQ_5 L2 VDDQ_5 E9 E9 VDDQ_5 L2 J8 ARDQ[16-23] VSS_6 K9 C9 K9 CKE VDDQ_4 C9 K9 C9 TP701 MEMTN ARDQS1 ARDQS1 L2 CS VDDQ_6 E9 K1 CS VDDQ_6 F1 F1 VDDQ_6 CS K1 VSS_6 ARDQ[0-7] ARDQ[16] E3 M1 CKE VDDQ_4 VDDQ_5 D2 VDDQ_5 D2 CKE VDDQ_4 D2 RVREF_A RVREF_B C20 K1 F1 ODT VDDQ_7 ODT VDDQ_7 VDDQ_7 ODT M1 E3 L2 E9 L2 E9 L2 VDDQ_5 E9 /ARDQS1 ARDQ[8-15] J3 H2 J3 H2 H2 VDDQ_8 RAS J3 ARDQ[17] DQL0 VSS_7 CS VDDQ_6 K1 CS VDDQ_6 F1 CS VDDQ_6 ARDQS1 K3 RAS VDDQ_8 H9 K3 RAS VDDQ_8 H9 H9 K3 VSS_7 DQL0 F7 M9 K1 ODT VDDQ_7 F1 ODT VDDQ_7 K1 ODT VDDQ_7 F1 G13 A17 L3 CAS VDDQ_9 L3 CAS VDDQ_9 VDDQ_9 CAS L3 M9 F7 DQL1 VSS_8 J3 RAS VDDQ_8 H2 J3 RAS VDDQ_8 H2 J3 H2 RVREF_B ARDQ8 WE J1 WE J1 J1 WE VSS_8 DQL1 ARDQ[18] F2 P1 K3 CAS VDDQ_9 H9 K3 CAS VDDQ_9 H9 K3 RAS VDDQ_8 H9 G21 A23 CAS VDDQ_9 T2 NC_1 J9 T2 NC_1 J9 J9 NC_1 T2 P1 F2 DQL2 VSS_9 L3 WE L3 WE L3 RVREF_A ARDQ9 RESET NC_2 L1 RESET NC_2 L1 L1 NC_2 RESET VSS_9 DQL2 ARDQ[19] F8 P9 NC_1 J1 NC_1 J1 WE J1 D17 NC_1 NC_3 L9 NC_3 L9 L9 NC_3 P9 F8 DQL3 VSS_10 T2 RESET NC_2 J9 T2 RESET NC_2 J9 T2 J9 ARDQ10 F3 NC_4 T7 F3 NC_4 T7 T7 NC_4 F3 VSS_10 DQL3 ARDQ[20] H3 T1 NC_3 L1 NC_3 L1 RESET NC_2 L1 B23 NC_3 G3 DQSL NC_6 G3 DQSL NC_6 NC_7 DQSL G3 T1 H3 DQL4 VSS_11 NC_4 L9 NC_4 L9 L9 ARDQ11 DQSL DQSL DQSL VSS_11 DQL4 ARDQ[21] H8 T9 F3 DQSL NC_7 T7 F3 DQSL NC_6 T7 F3 NC_4 T7 F10 D20 DQSL NC_6 C7 A9 C7 A9 A9 C7 T9 H8 DQL5 VSS_12 G3 DQSL G3 DQSL G3 ARCKE ARCKE ARDQ12 B7 DQSU VSS_1 B3 B7 DQSU VSS_1 B3 B3 VSS_1 DQSU B7 VSS_12 DQL5 ARDQ[22] G2 DQSL D22 DQSU VSS_2 E1 DQSU VSS_2 E1 E1 VSS_2 DQSU G2 DQL6 C7 DQSU VSS_1 A9 C7 DQSU VSS_1 A9 C7 A9 ARDQ13 E7 VSS_3 G8 E7 VSS_3 G8 G8 VSS_3 E7 DQL6 ARDQ[23] H7 B7 DQSU VSS_2 B3 B7 DQSU VSS_2 B3 B7 DQSU VSS_1 B3 D9 D19 DQSU VSS_2 D3 DML VSS_4 J2 D3 DML VSS_4 J2 J2 VSS_4 DML D3 H7 DQL7 VSS_3 E1 E7 VSS_3 E1 G8 VSS_3 E1 ARCLK1 ARCLK1 ARDQ14 VSS_5 DMU DMU VSS_5 J8 DMU VSS_5 J8 J8 DQL7 ARDQ[24-31] B1 E7 DML VSS_4 G8 DML VSS_4 E7 DML VSS_4 G8 C9 C22 E3 VSS_6 M1 E3 VSS_6 M1 M1 VSS_6 E3 B1 ARDQ[8-15] VSSQ_1 D3 DMU VSS_5 J2 D3 DMU VSS_5 J2 D3 J2 /ARCLK1 ARCLK1 ARDQ15 F7 DQL0 VSS_7 M9 F7 DQL0 VSS_7 M9 M9 VSS_7 DQL0 F7 VSSQ_1 ARDQ[24] D7 B9 VSS_6 J8 VSS_6 J8 DMU VSS_5 J8 VSS_6 F2 DQL1 VSS_8 P1 F2 DQL1 VSS_8 P1 P1 VSS_8 DQL1 F2 B9 D7 DQU0 VSSQ_2 E3 DQL0 VSS_7 M1 E3 DQL0 VSS_7 M1 E3 M1 F8 DQL2 VSS_9 P9 F8 DQL2 VSS_9 P9 P9 VSS_9 DQL2 F8 VSSQ_2 DQU0 ARDQ[25] C3 D1 F7 DQL1 VSS_8 M9 F7 DQL1 VSS_8 M9 F7 DQL0 VSS_7 M9 A20 A7 DQL1 VSS_8 H3 DQL3 VSS_10 T1 H3 DQL3 VSS_10 T1 T1 VSS_10 DQL3 H3 D1 C3 DQU1 VSSQ_3 F2 DQL2 VSS_9 P1 F2 DQL2 VSS_9 P1 F2 P1 ARCLK0 ARCLK0 ARDQM2 ARDQM2 H8 DQL4 VSS_11 T9 H8 DQL4 VSS_11 T9 T9 VSS_11 DQL4 H8 VSSQ_3 DQU1 ARDQ[26] C8 D8 F8 DQL3 VSS_10 P9 F8 DQL3 VSS_10 P9 F8 DQL2 VSS_9 P9 A21 B9 DQL3 VSS_10 G2 DQL5 VSS_12 G2 DQL5 VSS_12 VSS_12 DQL5 G2 D8 C8 DQU2 VSSQ_4 H3 DQL4 VSS_11 T1 H3 DQL4 VSS_11 T1 H3 T1 /ARCLK0 ARCLK0 ARDQS2 ARDQS2 H7 DQL6 H7 DQL6 DQL6 H7 VSSQ_4 DQU2 ARDQ[27] C2 E2 H8 DQL5 VSS_12 T9 H8 DQL5 VSS_12 T9 H8 DQL4 VSS_11 T9 A9 DQL5 VSS_12 DQL7 B1 DQL7 B1 B1 DQL7 E2 C2 DQU3 VSSQ_5 G2 DQL6 G2 DQL6 G2 ARDQS2 /ARDQS2 D7 VSSQ_1 B9 D7 VSSQ_1 B9 B9 VSSQ_1 D7 VSSQ_5 DQU3 ARDQ[28] A7 E8 H7 DQL7 H7 DQL7 H7 DQL6 E18 C12 ARDQ[16-23] DQL7 C3 DQU0 VSSQ_2 D1 C3 DQU0 VSSQ_2 D1 D1 VSSQ_2 DQU0 C3 E8 A7 DQU4 VSSQ_6 VSSQ_1 B1 VSSQ_1 B1 B1 ARODT ARODT ARDQ16 C8 DQU1 VSSQ_3 D8 C8 DQU1 VSSQ_3 D8 D8 VSSQ_3 DQU1 C8 VSSQ_6 DQU4 ARDQ[29] A2 F9 D7 DQU0 VSSQ_2 B9 D7 DQU0 VSSQ_2 B9 D7 VSSQ_1 B9 +1.5V_DDR F17 D6 DQU0 VSSQ_2 C2 DQU2 VSSQ_4 E2 C2 DQU2 VSSQ_4 E2 E2 VSSQ_4 DQU2 C2 F9 A2 DQU5 VSSQ_7 C3 DQU1 VSSQ_3 D1 C3 DQU1 VSSQ_3 D1 C3 D1 /ARRAS ARRAS ARDQ17 A7 DQU3 VSSQ_5 E8 A7 DQU3 VSSQ_5 E8 E8 VSSQ_5 DQU3 A7 VSSQ_7 DQU5 ARDQ[30] B8 G1 C8 DQU2 VSSQ_4 D8 C8 DQU2 VSSQ_4 D8 C8 DQU1 VSSQ_3 D8 E17 B12 DQU2 VSSQ_4 A2 DQU4 VSSQ_6 F9 A2 DQU4 VSSQ_6 F9 F9 VSSQ_6 DQU4 A2 G1 B8 DQU6 VSSQ_8 C2 DQU3 VSSQ_5 E2 C2 DQU3 VSSQ_5 E2 C2 E2 /ARCAS ARCAS ARDQ18 B8 DQU5 VSSQ_7 G1 B8 DQU5 VSSQ_7 G1 G1 VSSQ_7 DQU5 B8 VSSQ_8 DQU6 ARDQ[31] A3 G9 A7 DQU4 VSSQ_6 E8 A7 DQU4 VSSQ_6 E8 A7 DQU3 VSSQ_5 E8 E16 C5 DQU4 VSSQ_6 A3 DQU6 VSSQ_8 G9 A3 DQU6 VSSQ_8 G9 G9 VSSQ_8 DQU6 A3 G9 A3 DQU7 VSSQ_9 A2 DQU5 VSSQ_7 F9 A2 DQU5 VSSQ_7 F9 A2 DQU5 VSSQ_7 F9 RVREF_A C746 /ARCS ARCS ARDQ19 VSSQ_9 DQU7 B8 G1 DQU7 VSSQ_9 DQU7 VSSQ_9 VSSQ_9 DQU7 B8 DQU6 VSSQ_8 G1 DQU6 VSSQ_8 B8 DQU6 VSSQ_8 G1 R730 D14 C13 A3 DQU7 VSSQ_9 G9 A3 DQU7 VSSQ_9 G9 A3 DQU7 VSSQ_9 G9 1K 0.1uF /ARWE ARWE ARDQ20 1% A5 ARDQ21 DDR_HYNIX_NEW DDR_SS DDR_NANYA B14 A12 DDR_NANYA DDR_SS DDR_HYNIX_NEW ARREST ARRESET ARDQ22 B5 DDR_HYNIX DDR_HYNIX R731 C760 ARDQ23 1K C747 A13 1% 1uF ARBA0 ARBA0 0.1uF G11 E10 10V ARBA1 ARBA1 ARDQM3 ARDQM3 D16 C8 ARBA2 ARBA2 ARDQS3 ARDQS3 D8 ARDQ[24-31] ARDQS3 /ARDQS3 F18 C6 +1.5V_DDR ARCSX ARDQ24 D10 ARA[14]C15 ARDQ25 D7 ARA[13]A15 ARA14 ARDQ26 C11 RVREF_B C748 ARA13 ARDQ27 ARA[12]F13 C7 R732 0.1uF 1K ARA[11]C14 ARA12 ARDQ28 1% C10 ARA[10]F11 ARA11 ARDQ29 B7 ARA[9] E15 ARA10 ARDQ30 B10 R733 C761 ARA[8] D13 ARA9 ARDQ31 1K C749 AVDD3V3_MEMPLL 1% 0.1uF 1uF ARA[7] B15 ARA8 +1.5V_DDR 10V ARA7 ARA[6] E14 N14 +3.3V_NORMAL ARA[5] F16 ARA6 AVDD33_MEMPLL AVDD3V3_MEMPLL N15 ARA[4] E13 ARA5 AVSS33_MEMPLL L700 C718 C720 C722 C724 C726 C728 C705 C707 ARA[3] B13 ARA4 BLM18PG121SN1D 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 1uF 10uF ARA3 10V ARA[2] A14 R1 ARA[1] F14 ARA2 DVSS_50 C700 C759 P21 0.1uF 10uF ARA[0] F15 ARA1 DVSS_48 @optio 10V ARA0 ARA[0-14] +1.5V_DDR C717 C719 C721 C723 C725 C727 C706 C708 1uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 10V IC105 LGE2112 RVREF_C @optio RVREF_D P13 G2 RVREF_C BRDQM0 BRDQM0 V7 E4 RVREF_D BRDQS0 BRDQS0 E3 BRDQS0 /BRDQS0 BRDQ[0-7] F4 A1 BRCLK0 BRCLK0 BRDQ0 F3 J1 /BRCLK0 BRCLK0 BRDQ1 B2 BRDQ2 V4 J2 BRCLK1 BRCLK1 BRDQ3 V3 C2 /BRCLK1 BRCLK1 BRDQ4 K1 BRDQ5 P6 A2 BRCKE BRCKE BRDQ6 +1.5V_DDR K2 IC702 BRDQ7 H6 H5TQ2G63BFR-PBC IC704 BRODT BRODT H4 D1 +1.5V_DDR RVREF_C /BRRAS BRDQM1 B_RVREF6 H5TQ2G63BFR-PBC B_RVREF8 R726 C741 H5 BRRAS BRDQM1 F1 1K 0.1uF /BRCAS BRCAS BRDQS1 BRDQS1 +1.5V_DDR BRA[0-13] 1% K3 F2 /BRCS /BRDQS1 BRDQ[8-15] M8 N3 BRA[0] BRA[0-13] BRCS BRDQS1 B_RVREF7 C739 J3 VREFCA A0 BRA[1] BRA[0] N3 BRDQ8 P7 M8 R724 0.1uF N1 B1 B_RVREF5 B_RVREF5 A1 A0 VREFCA 1K BRBA0 BRBA0 BRDQ9 C709 P3 BRA[2] BRA[1] P7 1% R727 R702 B_RVREF7 1K C742 C762 P5 H3 0.1uF A2 BRA[2] A1 1% BRBA1 BRBA1 BRDQ10 1K H1 N2 BRA[3] P3 0.1uF 1uF K4 D3 1% VREFDQ A3 A2 BRBA2 P8 BRA[4] BRA[3] N2 H1 10V BRBA2 BRDQ11 R725 G3 A4 BRA[4] A3 VREFDQ BRDQ12 1% P2 BRA[5] P8 1K C740 L4 C1 A5 A4 1% 1% 0.1uF /BRWE BRWE BRDQ13 R703 R711 240 L8 R8 BRA[6] BRA[5] P2 240 BRA[0-14] 1K C710 G4 ZQ A6 BRA[6] A5 R717 BRDQ14 1% 0.1uF R2 BRA[7] R8 L8 +1.5V_DDR BRA[14] L5 D2 +1.5V_DDR A6 ZQ A7 BRA[8] BRA[7] R2 BRA14 BRDQ15 T8 +1.5V_DDR BRA[13] M4 A8 BRA[8] T8 A7 BRA13 B2 R3 BRA[9] BRA[12] N5 Y1 VDD_1 A9 BRA[9] R3 A8 +1.5V_DDR RVREF_D C743 BRA12 BRDQM2 BRDQM2 BRDQ[16-23] D9 L7 BRA[10] B2 BRA[11] M5 V2 +1.5V_DDR VDD_2 A10/AP A9 VDD_1 R728 0.1uF G7 R7 BRA[11] BRA[10] L7 D9 1K BRA[10] BRA11 BRDQS2 BRDQS2 1% P4 V1 VDD_3 A11 BRA[11] R7 A10/AP VDD_2 BRA10 BRDQS2 /BRDQS2 K2 N7 BRA[12] G7 BRA[9] M3 T4 VDD_4 A12/BC A11 VDD_3 B_RVREF8 C737 K8 T3 BRA[13] BRA[12] N7 K2 R722 BRA[8] BRA9 BRDQ16 B_RVREF6 C711 0.1uF L6 AB4 VDD_5 A13 BRA[13] T3 A12/BC VDD_4 1K R729 BRA8 BRDQ17 R704 0.1uF N1 K8 1% C763 BRA[7] L3 P2 1K VDD_6 A13 VDD_5 1K C744 1% N9 M7 N1 1% 0.1uF 1uF BRA[6] BRA7 BRDQ18 N4 AB3 VDD_7 A15 VDD_6 10V BRA6 BRDQ19 R1 M7 N9 BRA[5] K5 P3 VDD_8 A15 VDD_7 R723 BRA5 BRDQ20 R9 M2 R1 1K C738 BRA[4] N6 AB1 R705 VDD_9 BA0 BRBA0 VDD_8 1% 1K C712 N8 M2 R9 0.1uF BRA[3] BRA4 BRDQ21 1% BRBA1 BRBA0 BA0 N2 P1 0.1uF BA1 VDD_9 BRA3 BRDQ22 M3 N8 BRA[2] M1 AB2 BA2 BRBA2 BRCLK0 BRBA1 BA1 A1 M3 BRA[1] BRA2 BRDQ23 BRBA2 BA2 N3 VDDQ_1 BRCLK1 BRA1 A8 J7 A1 BRA[0] K6 U1 VDDQ_2 CK R713 VDDQ_1 BRDQM3 C1 K7 100 J7 A8 BRA0 BRDQM3 5% R715 CK W3 VDDQ_3 CK VDDQ_2 BRDQS3 BRDQS3 C9 K9 100 K7 C1 G5 W4 VDDQ_4 CKE BRCKE 5% CK VDDQ_3 +1.5V_DDR /BRDQS3 BRDQ[24-31] D2 K9 C9 BRCSX BRDQS3 BRCKE CKE AA3 VDDQ_5 /BRCLK0 VDDQ_4 BRDQ24 E9 L2 D2 D5 U4 VDDQ_6 CS /BRCS /BRCLK1 VDDQ_5 DDRV_11 BRDQ25 F1 K1 L2 E9 E5 AA4 VDDQ_7 ODT BRODT /BRCS CS VDDQ_6 H2 J3 K1 F1 DDRV_13 BRDQ26 /BRRAS BRODT T5 T3 VDDQ_8 RAS ODT VDDQ_7 DDRV_38 BRDQ27 H9 K3 J3 H2 V5 Y3 VDDQ_9 CAS /BRCAS /BRRAS RAS VDDQ_8 L3 K3 H9 DDRV_42 BRDQ28 IC702-*3 IC702-*1 /BRWE /BRCAS U5 U3 H5TQ2G63DFR-PBC IC702-*2 WE CAS VDDQ_9 DDRV_40 BRDQ29 K4B2G1646C-HCK0 NT5CB128M16BP-DI J1 L3 IC704-*1 IC704-*2 IC704-*3 E6 Y2 NC_1 /BRWE WE NT5CB128M16BP-DI K4B2G1646C-HCK0 H5TQ2G63DFR-PBC J9 T2 J1 DDRV_14 BRDQ30 N3 M8 BRREST F6 U2 +1.5V_DDR P7 A0 VREFCA N3 M8 M8 VREFCA A0 N3 NC_2 RESET NC_1 DDRV_18 BRDQ31 P3 A1 P7 A0 VREFCA A1 P7 L1 T2 J9 N3 M8 N3 M8 N3 M8 G6 A2 P3 A1 P3 NC_3 BRREST RESET NC_2 A0 VREFCA A0 VREFCA A0 VREFCA N2 A3 VREFDQ H1 N2 A2 H1 H1 A2 N2 L9 L1 P7 A1 P7 A1 P7 A1 DDRV_23 P8 A3 VREFDQ VREFDQ A3 P3 P3 P3 U6 M2 P2 A4 P8 A4 P8 NC_4 NC_3 N2 A2 H1 N2 A2 H1 N2 A2 H1 DDRV_41 BRRESET BRREST R8 A5 L8 P2 A4 A5 A5 P2 T7 F3 L9 P8 A3 VREFDQ P8 A3 VREFDQ P8 A3 VREFDQ T6 R2 A6 ZQ R8 L8 L8 ZQ A6 R8 BRA[14] NC_6 DQSL BRDQS0 NC_4 P2 A4 P2 A4 P2 A4 DDRV_39 T8 A7 R2 A6 ZQ A7 R2 G3 F3 T7 R8 A5 L8 R8 A5 L8 R8 A5 L8 AC5 E23 A8 T8 A7 T8 DQSL /BRDQS0 BRDQS2 DQSL NC_6 BRA[14] A6 ZQ A6 ZQ A6 ZQ R3 A9 VDD_1 B2 R3 A8 B2 B2 A8 R3 G3 R2 A7 R2 A7 R2 A7 DDRV_48 DDRV_16 L7 A10/AP VDD_2 D9 L7 A9 VDD_1 D9 D9 VDD_1 A9 L7 /BRDQS2 DQSL T8 A8 T8 A8 T8 A8 F7 F24 R7 A11 VDD_3 G7 R7 A10/AP VDD_2 G7 G7 VDD_2 A10/AP R7 A9 C7 R3 A9 VDD_1 B2 R3 A9 VDD_1 B2 R3 A9 VDD_1 B2 DDRV_19 DDRV_22 N7 K2 A11 VDD_3 VDD_3 A11 BRDQS1 L7 A10/AP VDD_2 D9 L7 D9 L7 D9 G7 G24 T3 A12/BC VDD_4 K8 N7 K2 K2 VDD_4 A12 N7 VSS_1 DQSU R7 G7 R7 A10/AP VDD_2 G7 R7 A10/AP VDD_2 G7 DDRV_24 DDRV_29 A13 VDD_5 N1 T3 A12/BC VDD_4 K8 K8 VDD_5 NC_6 T3 B3 B7 C7 A9 N7 A11 VDD_3 K2 N7 A11 VDD_3 K2 N7 A11 VDD_3 K2 AC6 F23 VDD_6 A13 VDD_5 N1 N1 VSS_2 DQSU /BRDQS1 BRDQS3 DQSU VSS_1 A12 VDD_4 A12/BC VDD_4 A12/BC VDD_4 M7 NC_5 VDD_7 N9 M7 VDD_6 N9 N9 VDD_6 M7 E1 B7 B3 T3 NC_6 VDD_5 K8 T3 A13 VDD_5 K8 T3 A13 VDD_5 K8 DDRV_49 DDRV_21 R1 NC_5 VDD_7 VDD_7 NC_5 /BRDQS3 DQSU N1 N1 N1 N7 G23 M2 VDD_8 R9 R1 R1 VDD_8 VSS_3 VSS_2 M7 VDD_6 N9 M7 VDD_6 N9 M7 VDD_6 N9 DDRV_36 DDRV_28 N8 BA0 VDD_9 M2 BA0 VDD_8 VDD_9 R9 R9 VDD_9 BA0 M2 G8 E7 E1 NC_5 VDD_7 R1 NC_5 VDD_7 R1 NC_5 VDD_7 R1 P7 E24 M3 BA1 N8 BA1 N8 VSS_4 DML BRDQM0 VSS_3 M2 VDD_8 R9 M2 VDD_8 R9 M2 VDD_8 R9 DDRV_37 DDRV_17 BA2 A1 M3 BA1 BA2 M3 J2 D3 E7 G8 N8 BA0 VDD_9 N8 BA0 VDD_9 N8 BA0 VDD_9 V6 E12 VDDQ_1 BA2 A1 A1 VSS_5 DMU BRDQM1 BRDQM2 DML VSS_4 M3 BA1 BA1 BA1 J7 CK VDDQ_2 A8 J7 VDDQ_1 A8 A8 VDDQ_1 J7 J8 D3 J2 BA2 M3 BA2 M3 BA2 DDRV_43 DVSS_15 K7 C1 CK VDDQ_2 VDDQ_2 CK BRDQ[0-7] BRDQM3 DMU A1 A1 A1 J10 F12 K9 CK VDDQ_3 C9 K7 C1 C1 VDDQ_3 CK K7 VSS_6 VSS_5 J7 VDDQ_1 A8 J7 VDDQ_1 A8 J7 VDDQ_1 A8 DDRV_35 DVSS_23 CKE VDDQ_4 K9 CK VDDQ_3 C9 C9 K9 M1 E3 J8 K7 CK VDDQ_2 C1 CK VDDQ_2 CK VDDQ_2 H10 A18 VDDQ_5 D2 CKE VDDQ_4 D2 D2 VDDQ_4 CKE VSS_7 DQL0 BRDQ[16-23] VSS_6 CK VDDQ_3 K7 CK VDDQ_3 C1 K7 CK VDDQ_3 C1 L2 CS VDDQ_6 E9 L2 VDDQ_5 E9 E9 VDDQ_5 L2 M9 F7 BRDQ[16] E3 M1 K9 CKE VDDQ_4 C9 K9 CKE VDDQ_4 C9 K9 CKE VDDQ_4 C9 DDRV_32 DVSS_1 K1 F1 CS VDDQ_6 VDDQ_6 CS DQL0 D2 D2 D2 H13 B18 J3 ODT VDDQ_7 H2 K1 F1 F1 VDDQ_7 ODT K1 VSS_8 DQL1 BRDQ[17] VSS_7 L2 VDDQ_5 E9 L2 VDDQ_5 E9 L2 VDDQ_5 E9 DDRV_33 DVSS_3 K3 RAS VDDQ_8 H9 J3 ODT RAS VDDQ_7 VDDQ_8 H2 H2 VDDQ_8 RAS J3 P1 F2 F7 M9 K1 CS VDDQ_6 F1 K1 CS VDDQ_6 F1 K1 CS VDDQ_6 F1 E20 C18 L3 CAS VDDQ_9 K3 H9 H9 VDDQ_9 CAS K3 VSS_9 DQL2 BRDQ[18] DQL1 VSS_8 J3 ODT VDDQ_7 H2 J3 ODT VDDQ_7 H2 J3 ODT VDDQ_7 H2 DDRV_15 DVSS_5 WE J1 L3 CAS WE VDDQ_9 WE L3 P9 F8 F2 P1 K3 RAS VDDQ_8 H9 K3 RAS VDDQ_8 H9 K3 RAS VDDQ_8 H9 F20 D18 T2 NC_1 J9 J1 J1 NC_1 VSS_10 DQL3 BRDQ[19] DQL2 VSS_9 L3 CAS VDDQ_9 L3 CAS VDDQ_9 L3 CAS VDDQ_9 DDRV_20 DVSS_9 RESET NC_2 L1 T2 RESET NC_1 NC_2 J9 J9 NC_2 RESET T2 T1 H3 F8 P9 WE J1 WE J1 WE J1 G20 E19 NC_3 L9 L1 L1 NC_3 VSS_11 DQL4 BRDQ[20] DQL3 VSS_10 T2 NC_1 J9 T2 NC_1 J9 T2 NC_1 J9 DDRV_27 DVSS_16 F3 NC_4 T7 NC_3 NC_4 L9 L9 NC_4 T9 H8 H3 T1 RESET NC_2 L1 RESET NC_2 L1 RESET NC_2 L1 G15 F19 G3 DQSL NC_6 F3 T7 T7 NC_7 DQSL F3 VSS_12 DQL5 BRDQ[21] DQL4 VSS_11 NC_3 L9 NC_3 L9 NC_3 L9 DDRV_25 DVSS_24 DQSL G3 DQSL DQSL NC_6 DQSL G3 G2 H8 T9 F3 NC_4 T7 F3 NC_4 T7 F3 NC_4 T7 G18 G19 C7 A9 DQL6 BRDQ[22] DQL5 VSS_12 G3 DQSL NC_7 G3 DQSL NC_6 G3 DQSL NC_6 DDRV_26 DVSS_31 B7 DQSU VSS_1 B3 C7 DQSU VSS_1 A9 A9 VSS_1 DQSU C7 H7 G2 DQSL DQSL DQSL D25 G22 DQSU VSS_2 E1 B7 B3 B3 VSS_2 DQSU B7 DQL7 BRDQ[23] DQL6 C7 A9 C7 A9 C7 A9 DDRV_12 DVSS_32 E7 VSS_3 G8 DQSU VSS_2 VSS_3 E1 E1 VSS_3 B1 BRDQ[8-15] H7 B7 DQSU VSS_1 B3 B7 DQSU VSS_1 B3 B7 DQSU VSS_1 B3 C25 E25 D3 DML VSS_4 J2 E7 G8 G8 VSS_4 DML E7 VSSQ_1 DQL7 DQSU VSS_2 E1 DQSU VSS_2 E1 DQSU VSS_2 E1 DDRV_9 DVSS_19 DMU VSS_5 J8 D3 DML DMU VSS_4 VSS_5 J2 J2 VSS_5 DMU D3 B9 D7 BRDQ[24-31] B1 E7 VSS_3 G8 E7 VSS_3 G8 E7 VSS_3 G8 B25 A26 E3 VSS_6 M1 J8 J8 VSS_6 VSSQ_2 DQU0 BRDQ[24] VSSQ_1 D3 DML VSS_4 J2 D3 DML VSS_4 J2 D3 DML VSS_4 J2 DDRV_6 DVSS_2 F7 DQL0 VSS_7 M9 E3 DQL0 VSS_6 VSS_7 M1 M1 VSS_7 DQL0 E3 D1 C3 D7 B9 DMU VSS_5 J8 DMU VSS_5 J8 DMU VSS_5 J8 A25 B26 F2 DQL1 VSS_8 P1 F7 M9 M9 VSS_8 DQL1 F7 VSSQ_3 DQU1 BRDQ[25] DQU0 VSSQ_2 E3 VSS_6 M1 E3 VSS_6 M1 E3 VSS_6 M1 DDRV_3 DVSS_4 F8 DQL2 VSS_9 P9 F2 DQL1 DQL2 VSS_8 VSS_9 P1 P1 VSS_9 DQL2 F2 D8 C8 C3 D1 F7 DQL0 VSS_7 M9 F7 DQL0 VSS_7 M9 F7 DQL0 VSS_7 M9 H7 C26 H3 DQL3 VSS_10 T1 F8 P9 P9 VSS_10 DQL3 F8 VSSQ_4 DQU2 BRDQ[26] DQU1 VSSQ_3 F2 DQL1 VSS_8 P1 F2 DQL1 VSS_8 P1 F2 DQL1 VSS_8 P1 DDRV_30 DVSS_6 H8 DQL4 VSS_11 T9 H3 DQL3 DQL4 VSS_10 VSS_11 T1 T1 VSS_11 DQL4 H3 E2 C2 C8 D8 F8 DQL2 VSS_9 P9 F8 DQL2 VSS_9 P9 F8 DQL2 VSS_9 P9 H8 D26 G2 DQL5 VSS_12 H8 T9 T9 VSS_12 DQL5 H8 VSSQ_5 DQU3 BRDQ[27] DQU2 VSSQ_4 H3 DQL3 VSS_10 T1 H3 DQL3 VSS_10 T1 H3 DQL3 VSS_10 T1 DDRV_31 DVSS_10 H7 DQL6 G2 DQL5 DQL6 VSS_12 DQL6 G2 E8 A7 C2 E2 H8 DQL4 VSS_11 T9 H8 DQL4 VSS_11 T9 H8 DQL4 VSS_11 T9 J8 DQL7 B1 H7 DQL7 H7 VSSQ_6 DQU4 BRDQ[28] DQU3 VSSQ_5 G2 DQL5 VSS_12 G2 DQL5 VSS_12 G2 DQL5 VSS_12 DDRV_34 D7 VSSQ_1 B9 DQL7 VSSQ_1 B1 B1 VSSQ_1 F9 A2 A7 E8 H7 DQL6 H7 DQL6 H7 DQL6 C3 DQU0 VSSQ_2 D1 D7 B9 B9 VSSQ_2 DQU0 D7 VSSQ_7 DQU5 BRDQ[29] DQU4 VSSQ_6 DQL7 B1 DQL7 B1 DQL7 B1 C8 DQU1 VSSQ_3 D8 C3 DQU0 DQU1 VSSQ_2 VSSQ_3 D1 D1 VSSQ_3 DQU1 C3 G1 B8 A2 F9 D7 VSSQ_1 B9 D7 VSSQ_1 B9 D7 VSSQ_1 B9 C2 DQU2 VSSQ_4 E2 C8 D8 D8 VSSQ_4 DQU2 C8 VSSQ_8 DQU6 BRDQ[30] DQU5 VSSQ_7 C3 DQU0 VSSQ_2 D1 C3 DQU0 VSSQ_2 D1 C3 DQU0 VSSQ_2 D1 A7 DQU3 VSSQ_5 E8 C2 DQU2 DQU3 VSSQ_4 VSSQ_5 E2 E2 VSSQ_5 DQU3 C2 G9 A3 B8 G1 C8 DQU1 VSSQ_3 D8 C8 DQU1 VSSQ_3 D8 C8 DQU1 VSSQ_3 D8 A2 DQU4 VSSQ_6 F9 A7 E8 E8 VSSQ_6 DQU4 A7 VSSQ_9 DQU7 BRDQ[31] DQU6 VSSQ_8 C2 DQU2 VSSQ_4 E2 C2 DQU2 VSSQ_4 E2 C2 DQU2 VSSQ_4 E2 B8 DQU5 VSSQ_7 G1 A2 DQU4 DQU5 VSSQ_6 VSSQ_7 F9 F9 VSSQ_7 DQU5 A2 A3 G9 A7 DQU3 VSSQ_5 E8 A7 DQU3 VSSQ_5 E8 A7 DQU3 VSSQ_5 E8 A3 DQU6 VSSQ_8 G9 B8 DQU6 VSSQ_8 G1 G1 VSSQ_8 DQU6 B8 DQU7 VSSQ_9 A2 DQU4 VSSQ_6 F9 A2 DQU4 VSSQ_6 F9 A2 DQU4 VSSQ_6 F9 DQU7 VSSQ_9 A3 G9 G9 A3 DQU5 VSSQ_7 DQU5 VSSQ_7 DQU5 VSSQ_7 VSSQ_9 DQU7 B8 G1 B8 G1 B8 G1 DQU7 VSSQ_9 DQU6 VSSQ_8 DQU6 VSSQ_8 DQU6 VSSQ_8 A3 G9 A3 G9 A3 G9 DQU7 VSSQ_9 DQU7 VSSQ_9 DQU7 VSSQ_9 DDR_HYNIX_NEW DDR_SS DDR_NANYA DDR_HYNIX DDR_HYNIX DDR_NANYA DDR_SS DDR_HYNIX_NEW THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS xxLT760H-UA 2011.09.06 ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. DDR ONE SIDE 12 Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes CI_A_DATA[0-7] CI_DATA[0-7] CI_A_DATA[0] AR904 0 CI_DATA[0] CI_A_DATA[1] CI_DATA[1] CI DETECT CI_A_DATA[2] CI_DATA[2] CI_A_DATA[3] CI_DATA[3] CI_A_DATA[4] AR905 0 CI_DATA[4] +3.3V_NORMAL CI_A_DATA[5] CI_DATA[5] CI TS INPUT CI_A_DATA[6] CI_DATA[6] CI_A_DATA[7] CI_DATA[7] Close to MT5369 R910 R914 +5V_CI_ON MT5369_TS_OUT[0-7] AR902 CI_MDI[0-7] 10K 10K 47 MT5369_TS_OUT[0] CI_MDI[0] MT5369_TS_OUT[1] CI_MDI[1] R929 R930 10K R933 R934 R935 R936 MT5369_TS_OUT[2] CI_MDI[2] /CI_CD1 47K 10K 10K 10K 10K MT5369_TS_OUT[3] CI_MDI[3] OPT OPT /CI_CD2 /PCM_WAIT MT5369_TS_OUT[4] CI_MDI[4] MT5369_TS_OUT[5] CI_MDI[5] +3.3V_NORMAL PCM_INPACK CI_A_ADDR[0-14] CI_ADDR[0-14] MT5369_TS_OUT[6] CI_MDI[6] MT5369_TS_OUT[7] CI_MDI[7] CI_VS1 CI_A_ADDR[0] AR906 0 CI_ADDR[0] AR903 R906 R913 R918 R919 R923 R924 /PCM_REG CI_A_ADDR[1] CI_ADDR[1] 47 10K 47K 47K 47K 10K 10K CI_A_ADDR[2] CI_ADDR[2] OPT OPT OPT /PCM_CE2 CI_A_ADDR[3] CI_ADDR[3] R907 47 CI_A_ADDR[4] AR907 0 CI_ADDR[4] MT5369_MISTRT CI_IN_TS_SYNC /PCM_IRQA R908 CI_A_ADDR[5] CI_ADDR[5] 47 CI_IN_TS_VAL MT5369_MIVAL_ERR CI_A_ADDR[6] CI_ADDR[6] MT5369_MCLKI R909 47 PCM_RST CI_IN_TS_CLK CI_A_ADDR[7] CI_ADDR[7] /PCM_IORD CI_A_ADDR[8] AR908 CI_ADDR[8] 0 C902 /PCM_IOWR Close to MT5369 CI_A_ADDR[9] CI_ADDR[9] 12pF 22 R931 50V /PCM_OE CI_VS1 CI_A_ADDR[10] CI_ADDR[10] OPT Close to CI Slot CI_A_VS1 OPT CI_A_ADDR[11] CI_ADDR[11] /PCM_WE CI_A_ADDR[12]AR909 0 CI_ADDR[12] R932 22 /PCM_CE1 CI_A_ADDR[13] CI_ADDR[13] /PCM_A_REG /PCM_REG OPT CI_A_ADDR[14] CI_ADDR[14] CI TS OUTPUT MT5369_TS_IN[0-7] Close to CI Slot CI_TS_DATA[0-7] MT5369_TS_IN[0] AR900 47 CI_TS_DATA[0] MT5369_TS_IN[1] CI_TS_DATA[1] MT5369_TS_IN[2] CI_TS_DATA[2] MT5369_TS_IN[3] CI_TS_DATA[3] MT5369_TS_IN[4] AR901 47 CI_TS_DATA[4] MT5369_TS_IN[5] CI_TS_DATA[5] MT5369_TS_IN[6] CI_TS_DATA[6] MT5369_TS_IN[7] CI_TS_DATA[7] Close to CI Slot +5V_CI_ON R915 47 MT5369_TS_CLK CI_TS_CLK R916 47 MT5369_TS_VAL CI_TS_VAL R917 47 MT5369_TS_SYNC CI_TS_SYNC C900 C904 C905 CI_A_DATA[0-7] 12pF 0.1uF 10uF 50V 10V Close to MT5369 OPT JK900 10067972-050LF 35 1 R927 100 36 2 CI_A_DATA[3] /CI_CD1 /PCM_CE1 CI_TS_DATA[3] 37 3 CI_A_DATA[4] 38 4 CI_A_DATA[5] CI_TS_DATA[4] 39 5 CI_A_DATA[6] CI_TS_DATA[5] 40 6 CI_A_DATA[7] CI_TS_DATA[6] CI_TS_DATA[7] 41 7 R939 22 R911 22 /PCM_CE2 42 8 CI_A_ADDR[10] /PCM_IORD R912 22 /PCM_IOWR CI_VS1 43 9 44 10 CI_A_ADDR[11] CI_MDI[0-7] 45 11 CI_A_ADDR[9] 46 12 CI_A_ADDR[8] CI_MDI[0] 47 13 CI_A_ADDR[13] R941 22 CI_MDI[1] 48 14 CI_A_ADDR[14] /PCM_OE CI_MDI[2] R942 22 49 15 /PCM_WE CI_MDI[3] 50 16 R940 22 /PCM_IRQA 51 17 C906 0.1uF C907 R926 R938 0.1uF 0 OPT 52 18 0 OPT 16V CI_MDI[4] 53 19 CI_MDI[5] 54 20 CI_MDI[6] 55 21 CI_A_ADDR[12] CI_MDI[7] 56 22 CI_A_ADDR[7] CI_TS_CLK 57 23 CI_A_ADDR[6] R921 22 58 24 PCM_RST CI_A_ADDR[5] R922 22 59 25 /PCM_WAIT CI_A_ADDR[4] R920 22 OPT 60 26 PCM_INPACK CI_A_ADDR[3] 61 27 CI_A_ADDR[2] /PCM_A_REG CI_TS_VAL 62 28 CI_A_ADDR[1] CI_TS_SYNC 63 29 CI_A_ADDR[0] 64 30 CI_A_DATA[0] CI_TS_DATA[0] 65 31 CI_A_DATA[1] +5V_CI_ON CI_TS_DATA[1] 66 32 CI_A_DATA[2] CI_TS_DATA[2] R928 100 67 33 R937 10K /CI_CD2 68 34 OPT R925 0 G2 69 G1 CI_IN_TS_VAL CI_IN_TS_CLK CI_IN_TS_SYNC THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS MID_MAIN_CI 2011.09.26 ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 13 Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes FROM LIPS & POWER B/D +3.5V_ST +3.5V_ST R2408 MMBT3906(NXP) Q2401 +12V PANEL_POWER TYP 1450mA 10K OPT R2461 1 3 L2408 R2463 10K NORMAL_EXCEPT_32 NORMAL_32 PANEL_VCC 0 BLM18SG121TN1D P2400 P2402 RL_ON OPT 2 +24V C FW20020-24S FM20020-24 R2464 4.7K Q2407 10K R2401 B Q2402 OPT AO3407A MTK_NON_EPI 10K R2442-*1 R2453 MMBT3904(NXP) C2432 C2433 S D L2403 OPT PWR ON 1 24V R2442 MTK_EPI 2 0.01uF 0.1uF PANEL_DISCHARGE_REG CIS21J121 PANEL_DISCHARGE_REG E 33K 24V 24V 50V 50V 10K 3 4 C2435 C2440 GND GND 4.7uF 1uF +3.5V_ST 5 6 G R2451 R2452 C2413 25V 1/8W L2402 1/8W 50V C2443 2K 2K GND 7 8 GND 0.1uF OPT CIS21J121 0.1uF 3.5V 3.5V 50V R2441 9 10 MTK_EPI 50V 1.8K MTK_NON_EPI 3.5V 3.5V R2441-*1 11 12 C2406 GND GND 5.6K 0.1uF 13 14 16V GND 15 16 GND/V-sync R2423 0 R2425 L/DIM0_VS 12V INV ON 100 INV_CTL 17 18 POWER_16_VSYNC 12V 19 20 A.DIM A_DIM R2426 C +12V 12V 21 22 P.DIM1 R2462 0 R2437 L2401 PWM_DIM1 10K GND/P.DIM2 Err OUT NON_37_LGD 10K B Q2406 CIS21J121 PWM_DIM2 23 24 PANEL_CTL POWER_24_GND MMBT3904(NXP) SLIM_32~55 0 POWER_16_GND R2420 C2401 R2460 E 25 0.1uF 50V SMAW200-H24S2 10K R2422 +3.3V_NORMAL 0 P2401 R2424 #16/#20/#23 4.7K LD - GND OR USE OPT LE(N.L.D.) - OPEN R2405 LE(L.D.) - USE ERROR_OUT 22 POWER_24_ERROR_OUT FOR LPB Download [To LED DRIVER] FOR LPB MODEL P2403 Power_DET 12507WR-08L +12V +3.5V_ST R2417 +5V_Normal 1 100K +3.5V_ST +12V +5V_NORMAL PD_12V OPT R2421 2 R2410 R2413 10K L2407 0 IC2402 2.7K OPT BLM18PG121SN1D 1% 5% NCP803SN293 3 R2419 POWER_DET VCC RESET 100 3 2 1 4 C2411 PD_12V 0.1uF C2415 GND R2409 16V 10uF IC2404 1.2K 16V TPS54327DDAR [EP]GND 5 1% C2412 FOR LPB MODEL 0.1uF POWER_ON/OFF2_3 R2458 R2435 33 16V 10K EN VIN 6 I2C_SCL5 1 8 C24001 On-semi THERMAL 0.1uF R1 1% 16V VFB VBST C2429 7 R2416 I2C_SDA5 9 +24V +3.5V_ST 2 7 100K R2415 0.1uF L2409 FOR LPB MODEL not to RESET at 8kV ESD R2459 16V 3.6uH 8 56K VREG5 SW 33 PD_3.5V IC2401 3 6 PD_24V C2416 R2429 100pF R2412 0 NCP803SN293 50V NR8040T3R6N 9 8.2K SS GND 5% C2430 1% VCC 3 2 RESET R2418 100 R2439 4 3A 5 22uF 10V 1 OPT 10K C2417 C2428 PD_24V C2410 24V-->3.48V R2 R2411 GND 1uF 3300pF 0.1uF 12V-->3.58V 1% 1.5K 10V 50V 16V 1% ST_3.5V-->3.5V POWER_ON/OFF1 POWER_ON/OFF2_1 POWER_ON/OFF2_2 POWER_ON/OFF2_3 POWER_ON/OFF2_4 DDR MAIN 1.5V +1.2V_MTK_CORE POWER_ON/OFF2_1 +12V R2430 +12V MAX 3.4 A +3.3V_NORMAL 10K L2404 C2420 L2400 IC2400 2uH AOZ1038PI [EP]LX L2410 IC2405 BLM18PG121SN1D 0.1uF BLM18PG121SN1D [EP]PGND TPS54425PWPR +3.3V_NORMAL *NOTE 17 +3.5V_ST C2423 PGND 1 8 NC_2 16V OPT R2404 0.1uF THERMAL R24000 C2407 C2408 C2409 C2414 C2441 Placed on SMD-TOP 5.6K 1% VIN NC_1 10uF 10uF 10uF 10uF 3300pF +1.5V_DDR 9 VIN2 VO EP[GND] 2 7 10V 10V 10V 10V 50V 14 1 C2405 OPT 16V R2 VIN_3 PWRGD THERMAL AGND EN BOOT 3 6 4700pF L2405 C2400 C2402 C2403 R2402 R1 R2428 EN 50V BLM18PG121SN1D 15 10uF 10uF 0.1uF FB COMP 3.3K VIN1 VFB 10K 16V 16V 16V 4 5 C2431 13 2 OPT L2406 10uF 1% 16 15 14 13 3.6uH 16V VIN_1 1 12 PH_3 VBST VREG5 R2406 12 3 THERMAL NR8040T3R6N 10K C2438 1% VIN_2 PH_2 R2403 R2 C2448 10uF C2418 10uF C2419 0.1uF 2 17 11 C2424 C2425 C2446 C2447 C2427 SW2 4A SS 1uF 10V C2404 10K GND_1 PH_1 0.1uF C2434 11 4 10V 10V 16V 3 IC2403 10 10uF 10uF 10uF 10uF 16V 0.1uF TPS54319TRE C2422 10V 10V 10V 10V 0.1uF R1 16V GND_2 4 9 SS/TR 50V C2445 POWER_ON/OFF1 3A 0.01uF SW1 10 5 GND R2427 33K 22pF 47K 1% R2407 C2439 1% R2434 C2426 50V 5 6 7 8 50V 100pF 100K 3300pF 50V PGND2 PG AGND VSENSE COMP RT/CLK 9 6 50V R2432 1/16W 330K 5% R1 PGND1 EN R2431 C2421 8 7 R2414 10K 15K 4700pF Vout=0.8*(1+R1/R2) 1/16W 5% 50V C2437 0.1uF POWER_ON/OFF2_2 +3.3V_NORMAL L2411 2uH R2433 56K R2 1/16W C2442 C2444 3A $ 0.145 1% 22uF 10V 22uF 10V Vout=0.827*(1+R1/R2)=1.521V Vout=(0.763+0.0017*Vout.set)*(1+R1/R2) THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS xxLT760H-UA 2011.09.29 ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MID_POWER 24 Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes 5V_HDMI_4_JACK 5V_HDMI_3_JACK R3310 R3312 5V_HDMI_3_JACK +5V_NORMAL 1K 4.7K R3330 R3336 SHIELD 1K 4.7K BODY_SHIELD C 20 R3311 1K C R3331 B 20 A1 A2 R3307 HDMI_HPD_4_JACK 1K 100K R3327 Q3303 B HDMI_HPD_3_JACK MMBD6100 19 100K MMBT3904(NXP) HPD Q3301 R3345 19 D3302 E MMBT3904(NXP) 4.7K HOT_PLUG_DETECT E R3346 18 C +5V_POWER OPT 4.7K 18 OPT VDD[+5V] 17 DDC/CEC_GND R3308 100 17 DDC_SDA_4_JACK DDC/CEC_GND R3328 100 16 DDC_SDA_3_JACK SDA R3309 100 16 C3302 DDC_SCL_4_JACK SDA R3329 100 0.1uF 15 16V SCL R3343 0 15 DDC_SCL_3_JACK R3337 R3339 SCL 47K 47K 14 IR_OUT_HDMI3 R3342 0 NC IR_OUT_HDMI2 14 CEC_REMOTE RESERVED 13 CEC_REMOTE CEC 13 DDC_SCL_3_JACK CK-_HDMI4_JACK CEC 12 CK-_HDMI3_JACK CLK- 12 TMDS_CLK- DDC_SDA_3_JACK 11 CLK_SHIELD 11 CK+_HDMI4_JACK TMDS_CLK_SHIELD 10 CK+_HDMI3_JACK CLK+ 10 D0-_HDMI4_JACK TMDS_CLK+ 9 D0-_HDMI3_JACK DATA0- 9 TMDS_DATA0- 8 DATA0_SHIELD 8 5V_HDMI_2_JACK +5V_NORMAL 5V_HDMI_4_JACK +5V_NORMAL D0+_HDMI4_JACK TMDS_DATA0_SHIELD 7 D0+_HDMI3_JACK DATA0+ 7 D1-_HDMI4_JACK TMDS_DATA0+ 6 D1-_HDMI3_JACK DATA1- 6 A1 A2 TMDS_DATA1- A1 A2 5 DATA1_SHIELD 5 MMBD6100 D1+_HDMI4_JACK TMDS_DATA1_SHIELD MMBD6100 4 D1+_HDMI3_JACK D3301 D3303 DATA1+ 4 C C D2-_HDMI4_JACK TMDS_DATA1+ 3 D2-_HDMI3_JACK DATA2- 3 TMDS_DATA2- 2 DATA2_SHIELD 2 D2+_HDMI4_JACK TMDS_DATA2_SHIELD C3301 C3303 1 D2+_HDMI3_JACK 0.1uF 0.1uF DATA2+ 1 16V 16V TMDS_DATA2+ R3324 R3326 R3338 R3340 47K 47K 47K 47K YKF45-7058V RSD-105156-100 DDC_SCL_2_JACK DDC_SCL_4_JACK JK3301 UI : HDMI2 JK3303 UI : HDMI3 DDC_SDA_2_JACK DDC_SDA_4_JACK 5V_HDMI_2_JACK R3316 R3318 1K 4.7K SHIELD C 20 R3317 Q3302 B 1K R3313 HDMI_HPD_2_JACK MMBT3904(NXP) 100K 19 R3347 HPD E 4.7K 18 OPT +5V_POWER 17 DDC/CEC_GND R3314 100 DDC_SDA_2_JACK 16 SDA 15 SCL R3315 R3300 100 0 DDC_SCL_2_JACK HPD SWITCH For CEC 14 NC HPD_CTL CONNECTION HPD_CTL CEC_REMOTE 13 CEC L B0 - A NEC_HPD IC3301 CK-_HDMI2_JACK +3.5V_ST NLASB3157DFT2G +3.5V_ST 12 H B1 - A MTK_HPD CLK- OPT R3341 0 11 IR_OUT_HDMI1 CLK_SHIELD CK+_HDMI2_JACK SELECT B1 R3376 0 10 HDMI_ARC 6 1 MTK_HPD CLK+ D0-_HDMI2_JACK C3306 9 0.1uF DATA0- VCC GND R3302 R3303 R3300 MTK Recommend : 0 Ohm 5 2 27K 120K 8 G DATA0_SHIELD D0+_HDMI2_JACK D3304 7 A B0 R3377 0 DATA0+ HDMI_HPD_2_JACK 4 3 NEC_HPD BAT54_SUZHO D1-_HDMI2_JACK From HDMI Connector CEC_REMOTE HDMI_CEC 6 To NEC D S DATA1- Q3300 5 RUE003N02 DATA1_SHIELD D1+_HDMI2_JACK HDMI_CEC_FET_ROHM 4 R3375 0 G DATA1+ D2-_HDMI2_JACK OPT Q3300-*1 3 DATA2- SI1012CR-T1-GE3 HDMI_CEC_FET_VISHAY D S 2 DATA2_SHIELD D2+_HDMI2_JACK 1 DATA2+ YKF45-7058V JK3302 UI : HDMI1 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS xxLT760H-UA 2011.09.29 ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. HDMI 4 33 Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes RGB_5V RGB_5V +5V_NORMAL RGB PC A1 C A2 MMBD6100 D3620 R3641 R3642 IC3600 M24C02-RMN6T 2.7K 2.7K E0 VCC 1 8 E1 WC 2 7 E2 SCL R3643 22 3 6 RGB_DDC_SCL VSS SDA R3644 22 4 5 RGB_DDC_SDA C3633 C3634 18pF 18pF 50V 50V DSUB_VSYNC OPT D3615 D3621 ADUC 5S 02 0R5L 30V 5.5V OPT DSUB_HSYNC OPT D3622 ADUC 5S 02 0R5L D3616 5.5V 30V OPT DSUB_B+ +3.3V_NORMAL DSUB_G+ R3646 10K DSUB_DET D3623 5.6V DSUB_R+ GREEN_GND DDC_CLOCK DDC_DATA BLUE_GND SYNC_GND RED_GND DDC_GND H_SYNC V_SYNC GND_2 GREEN GND_1 BLUE RED NC Closed to JACK SPG09-DB-010 SHILED 11 12 13 14 15 JK3603 16 10 6 7 8 9 1 2 3 4 5 PC AUDIO JK3604 PEJ027-04 3 E_SPRING 6A T_TERMINAL1 7A B_TERMINAL1 PC_R_IN JK3602 4 R_SPRING Diode_OLD +3.3V_NORMAL 2F01TC1-CLM97-4F D3624 for EMI_Cap T_SPRING 5.6V D3624-*1 GND 1 5 SPDIF OUT JP3605 18pF Fiber Optic 50V 7B B_TERMINAL2 OPT VCC R3620 2 2.7K 6B T_TERMINAL2 R3615 33 JP3606 VIN 3 PC_L_IN SPDIF_OUT D3613 C3615 4 5.5V 0.1uF Diode_OLD for EMI_Cap D3625 SHIELD OPT 16V D3625-*1 ADUC 5S 02 0R5L 5.6V 18pF 50V THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS xxLT760H-UA 2011.09.29 ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. JACK HIGH / MID 36 Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes EXT UART SWITCH RS232C 1A@5V /1A@12V FOR COMMERCIAL(RS-232C POWER) DBG_SW CONNECTION UART_SW2 CONNECTION L B0 - A MTK ADJ L B0 - A Interactive H B1 - A MTK DEBUG H B1 - A USB Download EXT_5V EXT_12V 10 5 UART_SW1 L3800 L3801 JP3811 UART_SW2 9 IC3811 IC3802 OPT NLASB3157DFT2G NLASB3157DFT2G JP3810 IR_OUT_RS232C 4 +3.5V_ST R3858 +3.5V_ST IC3800 8 SELECT B1 0 R3842 +3.5V_ST 6 1 0 B1 SELECT R3820 100 MTK_DBG_TX MTK_NEC_RX 1 6 MAX3232CDR JP3808 3 ON SEMICONDUCTOR L3802 ON SEMICONDUCTOR JP3812 VCC ANALOG SWITCH GND ANALOG SWITCH 7 5 2 GND VCC 2 5 0.1uF C3800 C1+ VCC R3821 100 JP3809 C3822 1 16 2 C3811 0.1uF A R3859 R3843 C3804 B0 0 B0 A 0.1uF +3.5V_ST 4 3 0 R3835 0 6 SOC_TX RS232_TX RS232_TX 3 4 NEC_TX C3801 V+ GND 0.1uF D3804 D3805 1K 0.1uF 2 15 50V 20V 20V 1 EAN38256201 EAN38256201 OPT OPT R3834 C1- DOUT1 BAP70-02 3 14 D3803 R3862 0 SPG09-DB-009 OPT 0.1uF C3802 C2+ RIN1 +3.5V_ST 4 13 JK3803 IC3812 IC3804 NLASB3157DFT2G NLASB3157DFT2G C2- ROUT1 5 12 R3811 R3814 R3860 4.7K 4.7K SELECT B1 R3847 0 0 B1 SELECT 6 1 MTK_DBG_RX 1 6 C3803 V- DIN1 MTK_NEC_TX 0.1uF 6 11 RS232_RX ON SEMICONDUCTOR ON SEMICONDUCTOR VCC ANALOG SWITCH GND ANALOG SWITCH RS232_TX 5 2 GND VCC 2 5 DOUT2 DIN2 C3823 7 10 C3813 0.1uF A R3861 R3846 B0 0 0.1uF 4 3 0 B0 A R3836 0 SOC_RX RS232_RX RS232_RX 3 4 NEC_RX RIN2 ROUT2 8 9 EAN38256201 EAN38256201 EAN41348201 R3863 0 OPT UART DBG SWITCH EXT_SPK_CONTROL & DBG OUT UART_DBG_SW CONNECTION DBG_SW CONNECTION +3.3V_NORMAL L B0 - A Debug NEC L B0 - A DEBUG_NEC/MTK DBG_SW H B1 - A Debug MTK IC3806 H B1 - A EXT.SPK VOL Control R3849 NLASB3157DFT2G +3.5V_ST +3.5V_ST UART_DBG_SW 3.6K IC3805 R3844 NLASB3157DFT2G B1 SELECT 4.7K EXT_SPK_VOL+ 1 6 ON SEMICONDUCTOR R3848 +3.5V_ST ANALOG SWITCH 0 B1 SELECT GND VCC MTK_DBG_TX 1 6 2 5 ON SEMICONDUCTOR C3816 GND ANALOG SWITCH VCC B0 A 0.1uF 2 5 JK_DBG_TX 3 4 C3814 B0 A 0.1uF EAN38256201 NEC_DBG_TXD 3 4 JK_DBG_TX JK3801 EAN38256201 PEJ027-04 +3.3V_NORMAL E_SPRING 3 +3.5V_ST JP3801 IC3808 T_TERMINAL1 NLASB3157DFT2G 6A R3851 +3.5V_ST IC3807 3.6K R3845 NLASB3157DFT2G B_TERMINAL1 7A 4.7K B1 SELECT OPT OPT EXT_SPK_VOL- 1 6 C3818 R3850 D3806 R_SPRING 4 0 B1 SELECT 1000pF 1 6 ON SEMICONDUCTOR C3817 50V 5.6V MTK_DBG_RX GND ANALOG SWITCH VCC 0.1uF 2 5 T_SPRING JP3802 ON SEMICONDUCTOR 5 GND ANALOG SWITCH VCC 2 5 C3815 B0 A B_TERMINAL2 7B JK_DBG_RX 3 4 0.1uF B0 A OPT NEC_DBG_RXD 3 4 JK_DBG_RX C3819 D3807 T_TERMINAL2 6B EAN38256201 1000pF 5.6V EAN38256201 50V OPT EXT_SPK_CONTROL NVRAM I2C SWITCH UART_SW2 CONNECTION L B0 - A NVRAM - NEC H B1 - A NVRAM - MTK EEPROM_SW IC3809 NLASB3157DFT2G +3.5V_ST R3852 SELECT B1 0 6 1 I2C_SCL5 ON SEMICONDUCTOR VCC ANALOG SWITCH GND 5 2 C3820 0.1uF A R3853 B0 0 SCL_NVRAM 4 3 NEC_EEPROM_SCL EAN38256201 R3856 0 OPT IC3810 NLASB3157DFT2G R3854 SELECT B1 0 6 1 I2C_SDA5 ON SEMICONDUCTOR VCC ANALOG SWITCH GND 5 2 C3821 0.1uF A R3855 B0 0 SDA_NVRAM 4 3 NEC_EEPROM_SDA EAN38256201 R3857 0 OPT THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS xxLT760H-UA 2011.09.29 ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. JACK_COMMON 38 Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes +3.3V_NORMAL IR & KEY +3.5V_ST I_SENSOR +3.5V_ST L4101 BLM18PG121SN1D +3.5V_ST P4102 R4101 R4117 R4118 C4110 C4109 C4108 12507WR-10L 47K 10K 10K 0.1uF 0.1uF 1000pF OPT 1% 1% 16V 16V 50V +3.5V_ST L4102 OPT I_SENSOR I_SENSOR IR R4103 R4113 BLM18PG121SN1D 47K 100 R4102 KEY1 1 C 10K B R4107 R4114 L4103 Q4100 E OPT 47K 100 BLM18PG121SN1D R4104 KEY2 2 2SC3052 C 47K OPT OPT B C4100 C4102 E 0.1uF 0.1uF D4101 R4108 0 3 Q4101 5.6V +3.5V_ST 2SC3052 D4100 AMOTECH L4100 NON_I_SENSOR 5.6V BLM18PG121SN1D AMOTECH 4 C4103 C4101 C4104 0.1uF 0.1uF 1000pF 5 16V 16V 50V OPT R4100 0 6 7 +5V_ST C4107 D4104 100pF 5.6V 50V AMOTECH R4126 1.5K LED_R 8 R4130 10K R4109 R4131 10K 9 22 OPT IR_OUT_RS232C R4123 100 R4132 I_SENSOR C 10K I2C_SCL2 10 Q4102 B R4127 OPT 100 2SC3052 I2C_SCL3 E I_SENSOR 11 I2C_SDA2 R4124 100 +5V_ST I2C_SDA3 R4128 100 R4134 OPT R4133 10K 22 D4105 D4106 IR_OUT_HDMI1 CDS3C05HDMI1 CDS3C05HDMI1 5.6V 5.6V R4136 C 10K Q4103 B 2SC3052 E R4135 30K C B Q4104 E 2SC3052 Zener Diode is +5V_ST R4138 close to wafer R4137 10K 22 IR_OUT_HDMI2 R4140 C 10K Q4105 B 2SC3052 E R4139 30K C IR_OUT_CTRL B Q4106 E 2SC3052 +5V_ST R4142 10K R4141 22 IR_OUT_HDMI3 R4144 C 10K Q4107 B 2SC3052 E R4143 30K C B Q4108 E 2SC3052 THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS xxLT760H-UA 2011.09.26 ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. IR / KEY 41 Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes USB To SERIAL I/F +3.3V_NORMAL +3.3V_USB2SER USB_WIFI M_REMOTE C4316 L4301 BLM18PG121SN1D C4312 C4311 20pF M_REMOTE X4300 C4315 20pF +5V_USB FOR USB C4313 0.1uF 0.1uF M_REMOTE M_REMOTE 0.1uF 16V 16V 16V M_REMOTE M_REMOTE 12MHz M_REMOTE R4305 +3.3V_USB2SER 1M 1% OPT +12V +3.3V_USB2SER L4305 IC4305 X1/CLKI BLM18PG121SN1D +5V_USB M_REMOTE [EP]PGND TPS54425PWPR GND_3 VCC_2 +5V_USB R4304 L4302 [EP] P3.0 P3.1 P3.3 P3.4 R4307 10K X2 BLM18PG121SN1D 91K OPT VIN2 VO 1% 14 1 32 31 30 29 28 27 26 25 C4319 WIFI C4339 THERMAL C4321 VREGEN TEST1 0.1uF C4320 MAX 0.4A R4331 M_REMOTE M_REMOTE 1 24 10uF 10uF 15 16V 0.1uF VIN1 VFB 22K THERMAL 10V 13 2 M_REMOTE 16V 10V M_REMOTE C4324 R4310 10K R4308 SUSPEND 2 33 23 TEST0 100K C4310 C4309 WIFI WIFI 10uF 1% OPT WIFI WIFI R2 1% 0.01uF 0.1uF For EMI P4301 16V VCC_1 3 22 CLKOUT VBST VREG5 25V 16V 12507WR-04L 12 3 VDD18 IC4304 DTR C4327 R4301 1.5K 4 TUSB3410RHBR 21 WIFI SW2 4A SS 1uF 10V PUR 5 20 RTS C4326 11 4 M_REMOTE_DEV VDD R4302 33 M_REMOTE DP SOUT/IR_SOUT 1 0.1uF R1 USB2SER_DP 6 19 M_REMOTE_TX 50V R4330 C4332 SW1 GND 10 5 120K 22pF R4303 33 DM GND_2 DM R4328 C4329 50V USB2SER_DM 7 18 2 1% M_REMOTE_DEV WIFI_DM 3300pF 100K M_REMOTE GND_1 8 17 SIN/IR_SIN PGND2 PG 50V M_REMOTE_RX 9 6 M_REMOTE DP C4317 22pF 10 11 12 13 14 15 16 C4318 3 22pF WIFI_DP 9 PGND1 EN R4329 10K 8 7 RESET SDA SCL WAKEUP CTS DSR DCD RI/CP RCLAMP0502BA GND 4 C4328 POWER_ON/OFF2_4 0.1uF +5V_USB D4300 5 L4308 OPT +3.3V_USB2SER +3.3V_USB2SER M_REMOTE To SOC . 2uH R4306 C4333 C4334 R4309 22uF 22uF 15K 10K 10V 10V M_REMOTE /USB2SER_RESET C4314 1uF M_REMOTE Vout=(0.763+0.0017*Vout.set)*(1+R1/R2)=4.98V USB2 USB1 +3.3V_NORMAL +3.3V_NORMAL R4327 10K R4323 R4311 OPT 10K 10K R4312 OPT 10K IC4303 TPS2554 [EP] IC4306 TPS2554 [EP] +5V_USB +5V_USB GND FAULT 1 10 GND FAULT 1 10 THERMAL THERMAL 11 IN_1 OUT_2 2 9 11 IN_1 OUT_2 2 9 IN_2 OUT_1 C4323 3 8 IN_2 OUT_1 3 8 C4340 10uF ILIM_SEL 4 7 ILIM0 10V DVR Ready ILIM_SEL ILIM0 10uF 10V DVR Ready /USB_OCD1 4 7 USB_CTL1 EN 5 6 ILIM1 MAX 1.8A /USB_OCD2 EN ILIM1 MAX 1.8A USB_CTL2 5 6 R4300 1/10W R4341 1/10W R4314 1/10W JK4303 R4313 1/10W 27K 27K OPT JK4304 27K 27K OPT 1 3AU04S-345-ZC-H-LG 1 USB DOWN STREAM 3AU04S-345-ZC-H-LG USB DOWN STREAM 2 USB_DM1 2 USB_DM2 RCLAMP0502BA RCLAMP0502BA 3 USB_DP1 3 USB_DP2 D4303 4 D4304 OPT 4 OPT 5 5 To SOC To SOC THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS xxLT760H-UA 2011.09.29 ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. USB3_HUB_WiFi 43 Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes Full Scart +3.3V_NORMAL +12V R4601 10K CLOSE TO JUNCTION SC_DET D4611-*2 D4611-*1 C4604 E C4606 D4611 MMBT3906(NXP) R4605 5.6V 5.6V 5.6V 0.1uF Q4600 470 0.1uF 200pF 200pF 50V OPT B ESD_LG1152_SCART ESD_MTK_SCART C Q4601 R4606 MMBT3904(NXP) C 47K R4602 SC_CVBS_IN 390 B C4607 47uF D4609 D4609-*1 D4609-*2 E 25V 5.5V 5.5V 5.5V 15pF 15pF R4603 AV_DET OPT 390 ESD_MTK_SCART ESD_LG1152_SCART DTV/MNT_V_OUT 22 Gain=1+Rf/Rg COM_GND Rf R4607 Rg 21 75 R4600 R4604 15K SYNC_IN 180 20 D4610 SYNC_OUT 5.5V D4610-*1 C4605 19 OPT 5.5V 100uF SYNC_GND2 15pF 16V R4608 0 18 ESD_MTK_SCART SYNC_GND1 OPT 17 RGB_IO 16 SC_FB R_OUT 15 D4601 RGB_GND 5.6V D4601-*1 OPT D4601-*2 14 5.6V R_GND 5.6V 200pF 200pF 13 ESD_MTK_SCART D2B_OUT ESD_LG1152_SCART 12 G_OUT SC_R 11 D2B_IN D4602 D4602-*1 10 G_GND 5.5V 5.5V 9 OPT 15pF ID ESD_MTK_SCART 8 B_OUT SC_G 7 AUDIO_L_IN D4603 D4603-*1 6 B_GND 5.5V 5.5V OPT 15pF 5 AUDIO_GND ESD_MTK_SCART 4 AUDIO_L_OUT 3 SC_B AUDIO_R_IN 2 D4604 D4604-*1 AUDIO_R_OUT 5.5V 5.5V 1 15pF OPT ESD_MTK_SCART PSC008-01 SC_ID JK4600 SC_L_IN D4605 D4605-*1 D4605-*2 D4600 5.6V 5.6V 5.6V 20V 200pF OPT 200pF OPT ESD_LG1152_SCART D4600-*2 ESD_MTK_SCART D4600-*1 20V 20V 10pF 10pF ESD_MTK_SCART ESD_LG1152_SCART SC_R_IN D4606 D4606-*1 D4606-*2 5.6V 5.6V 5.6V OPT 200pF 200pF ESD_MTK_SCART ESD_LG1152_SCART [SCART AUDIO MUTE] BLM18PG121SN1D L4600 DTV/MNT_L_OUT DTV/MNT_L_OUT D4607 5.6V C4600 C4602 OPT 1000pF 4700pF +3.5V_ST 50V C Q4602 B BLM18PG121SN1D MMBT3904(NXP) L4601 DTV/MNT_R_OUT E R4625 D4608 4.7K C4603 OPT 5.6V C4601 4700pF R4623 SCART_MUTE OPT 1000pF 50V 510 DTV/MNT_R_OUT C Q4603 B MMBT3904(NXP) E THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS SCART GENDER 2011.10.26 ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 46 Copyright © 2012 LG Electronics. Inc. All rights reserved. LGE Internal Use Only Only for training and service purposes
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