i Preface Welcome to the Volume 5 Number 2 of the International Journal of Design, Analysis and Tools for Integrated Circuits and Systems (IJDATICS). This issue comprises of i) enhanced and extended version of research papers from the International DATICS Workshops in 2014, and ii) ordinary manuscript submissions in 2014. DATICS Workshops were created by a network of researchers and engineers both from academia and industry in the areas of i) Design, Analysis and Tools for Integrated Circuits and Systems and ii) Communication, Computer Science, Software Engineering and Information Technology. The main target of DATICS Workshops is to bring together software/hardware engineering researchers, computer scientists, practitioners and people from industry to exchange theories, ideas, techniques and experiences. This IJDATICS issue presents three high quality academic papers. This mix provides a well-rounded snapshot of current research in the field and provides a springboard for driving future work and discussion. The three papers presented in this volume are summarized as follows: • Text Clustering: Ciganaitė, Mackutė-Varoneckienė, and Krilavičius investigate the performance of bag of words, and inverse document frequency along with three common clustering algorithm on less popular languages such as Azeri or Lithuanian. • Feedback Control System: Lei, Lee, Kwan, Lee, Huang, and Kwok propose and build a smart three- layer hierarchical power conversion system for laboratories as a means for enhancing cross- disciplinary integrated design coursework. • HDL SoC diagnostics: Vladimir Hahanov, Baghdadi Ammar Awni Abbas, Eugenia Litvinova, and Svetlana Chumachenko describes technology for diagnosis SoC HDL-models, based on transaction graph. We are beholden to all of the authors for their contributions to the Volume 5 Number 2 of IJDATICS. We would also like to thank the IJDATICS editorial team. Editors: Ka Lok Man, Xi’an Jiaotong-Liverpool University, China, David Afolabi, Xi’an Jiaotong-Liverpool University, China. ii Table of Contents Vol. 5, No. 2, December 2014 Preface .......………………...………………..…………………………………....… i Table of Contents …......………………………………..………………………....... ii 1. Text Document Clustering ………………………………………….……….……… ……………………………. G. Ciganaitė, A. Mackutė-Varoneckienė, T. Krilavičius 1 2. Undergraduate Cross-Discipline Integrated Learning through Designing a Smart Hierarchical Power Conversion System ………………………………………….…. Chi-Un Lei, Christopher H.T. Lee, T.O. Kwan, C.K. Lee, K.B. Huang, R.Y.K. Kwok 6 3. HDL SoC TAB-model for Diagnosis and Repair ……………Vladimir Hahanov Baghdadi Ammar Awni Abbas, Eugenia Litvinova, Svetlana Chumachenko 9 INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR INTEGRATED CIRCUITS AND SYSTEMS, VOL. 5, NO. 2, DECEMBER 2014 1 Text Document Clustering G. Ciganaitė, A. Mackutė - Varoneckienė, T. Krilavičius Abstract—Document clustering is a well known technique II. D OCUMENT R EPRESENTATION for improving information retrieval results, organizing them, browsing in a collection of documents. It is quite well investigated Feature set is represented by n × m matrix with m features for English and some other popular languages, however, the (columns) and n objects (rows), where usually n < m. In this performance of different techniques, combining features, their case, features are words (t) and objects are documents (d ∈ D, selection and clustering methods for less popular languages, such as Azeri, Lithuanian or Russian is not known. In this paper where D is set of document). we compare the performance of two document representations, The best known method to form feature matrix is Bag namely word frequency in documents (bag of words, BOW) Of Words (BOW). This method counts the frequency ωt,d of and term frequency - inverse document frequency (TF-IDF) words in a document. The most popular method is a simple and three clustering algorithms (k-means, spherical k-mean and frequency: ωt,d = f (t, d). The problem with BOW is that hierarchical clustering with Ward linkage) with Euclidean and cosinus distances. sometimes words which occur many times but are not signif- The performance was evaluated using a number of criteria: icant can make a big influence to the dissimilarity measure. precision, recall, F-score, Rand index and purity. Overall, the best The solution is TF-IDF [11], [10]. It reduces the influence results were achieved using TF-IDF document representation, of insignificant words to distance measure and increase the cosine dissimilarity and spherical k-means. influence of significant words. This procedure is a product of Index Terms—Text documents clustering; distance measures; frequency and idft,D = ln N n , where n = |{d ∈ D : t ∈ k-means algorithm; spherical k-means algorithm; hierarchical d}| is a number of documents which contain word t, then clustering with Ward linkage. tfidf (t, d, D) = ωt,d · idft,D [11], [12], [2]. In practice, more methods can be used, for example, stem- I. I NTRODUCTION ming, but not all languages have tools for preprocessing, D OCUMENT clustering is a well know technique for grouping documents by their similarity (or dissimilarity) [1], [2]. The goal of the clustering is to group objects into while BOW does not require information about properties of a language. clusters where objects are as homogeneous as possible, and ob- jects in different clusters clearly differ from each other [3], [2]. III. C LUSTERING METHODS Document clustering is well researched for English and some In this paper we will use the most popular clustering tech- other popular languages [1], [2], and applied for improving niques: k-means, spherical k-means and hierarchical methods, information retrieval results [2], [4]. As in most cases in Nat- which are defined in sections III-B–III-D, respectively. ural Language Processing, clustering is not language agnostic, We have n × m matrix of features, the set of classes C = therefore we investigate the performance of different document (C1 , C2 , ..., Ck ) and document dependence on one of them. representation and clustering techniques for the Azeri language The main goal of clustering is to group the same documents [5], [6], [7]. Most common clustering methods are k-means [2] to such clusters as they are classified, but we are not dependent and spherical k-means [8] for flat (partitional) clustering and on labels of classes or clusters we get. It means that despite hierarchical clustering [2], therefore we experiment using them the fact that documents are clustered in cluster Ci although in combination with most common document representations, we know that all of them depend on class j (i 6= j), clustering namely bag of words (BOW) [9] and TF-IDF [7], [10], [11]. will be assumed as correct. The performance of techniques is compared with each other and random baseline using a number of criteria: precision, recall, F-score, Rand index and purity [2]. A. Distance measure Document representation techniques are discussed in sec- Distance measure in clustering is a numeric expression tion II, measures to determine relation between documents which expresses similarity or dissimilarity between documents described in section III-A, k-means, spherical k-means and hierarchical clustering algorithms are presented in sections d1 = (ωt1 ,d1 , ωt2 ,d1 , ..., ωtm ,d1 ) III-B – III-D, respectively and clustering quality evaluation d2 = (ωt1 ,d2 , ωt2 ,d2 , ..., ωtm ,d2 )) indexes are described in section III-E. Experimental results are given in section IV. Conclusions and feature plans are In case of binary feature representation where ω(t,d) = 1 defined in section V. when word occurs in a document or ω(t,d) = 0 vice versa the G. Ciganaitė and A. Mackutė - Varoneckienė – Vytautas Magnus University, Jaccard index [2], [3] could be used: Faculty of Informatics, Kaunas, Lithuania. T. Krilavičius – Vytautas Magnus University, Faculty of Informatics, Kaunas, Lithuania, Baltic Institute of Advanced Technology, Vilnius, Lithuania. |di ∩ dj | distJ (di , dj ) = 1 − (1) The research was partially funded by ESFA (VP1-3.1-MM-10-V-02-025). |di ∪ dj | INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR INTEGRATED CIRCUITS AND SYSTEMS, VOL. 5, NO. 2, DECEMBER 2014 2 In other cases the most popular measure is Minkowski C. Spherical k-means distance: Spherical k-means (SK-means) is a popular method for v u n u X document clustering. Its execution is quite similar to k-means, p dist(di , dj ) = t |ωtk ,di − ωtk ,dj |p but SK-means uses cosine similarity and operates on vectors i=1 that lie on the unit sphere [20], [21]: Let us assume that we know the number of clusters k. where k = 1, 2, ..., m and i, j = 1, 2, ..., n. When value p = 1, (0) (0) (0) Minkowski distance is called Manhattan distance: Step 1: initialize centroid set {c1 , c2 , ..., ck }; (t) n ci is the mean vector of cluster P normalized to the unit (0) x X dM (di , dj ) = |ωtk ,di − ωtk ,dj | (2) (0) x∈π (0) Euclidean norm: ci = P i , where πi - i=1 (0) x x∈πi and when p = 2, it is an Euclidean distance [13], [14], [2], initial document partition, t = 0, 1, ... - iteration index, [3] v i = 1, 2, ..., k. um uX Step 2: assign documents to the closest centroid by cosine dE (di , dj ) = t (ωtk ,di − ωtk ,dj )2 (3) similarity; i=1 Step 3: recompute centroids corresponding to the parti- For text documents often cosine distance [15], [16], [2], [3] tion completed P in step 2; is used: (t+1) x (t+1) x∈π Pn ci = P i ωt ,di · ωtk ,dj || x∈π(t+1) x|| dcos (di , dj ) = 1 − qP i=1 k q . (4) i n Step 4: repeat the 2nd and 3rd steps while increase of 2 Pn 2 i=1 ωtk ,di · i=1 ωtk ,dj k objective function Φ({π i }i=1 ) is greater than ε. k Pk P B. K-means Objective function is Φ {πi }i=1 = i=1 x∈πi xT ci K-means is an iterative technique whose basic aim is to D. Hierarchical clustering assign documents to the nearest centroid (object which is The main aim of hierarchical clustering is creating a hier- considered as a center of cluster). Usually, k-means for de- archy of clusters. Usually, agglomerative or divisive [15], [1] termination of document interrelation uses Euclidean distance. approaches are used. In this paper we will use an agglomera- The method works in 4 steps [17], [2], [3]: tive method, because it is less complex [2], [3]. Step 1: select a number of clusters k; Agglomerative hierarchical clustering algorithm consists of In this paper we will assume that we know the number 4 steps [2]: k. However, naturally, it is not known, and different Step 1: calculate proximity matrix; techniques are used to determine it, e.g. elbow, silhouette, This is n × n matrix which describes distances between gap statistics [18], [19]. documents. Distances can be calculated by one of the Step 2: distribute all documents to the nearest centroid measures described above. ci , i = 1, 2, .., k; Step 2: merge the closest pair of clusters; The initial set of centroids C = (C1 , C2 , ..., Ck ) is According to proximity matrix, the closest pair of docu- selected at random and other documents are assigned ments is merged to one cluster. to that centroid where the distance is the shortest. As Step 3: update proximity matrix. a result of random initial centroids, most of the times the While every document is in the separate cluster, merging outcomes of the method will be different. is a very simple operation: the closest pair of documents Step 3: recalculate centroids ci ; is merged to one cluster. After the first iteration simi- In this part the method calculates the mean of all clusters larity among clusters should be calculated. Usually, the individually. This value will be assumed as a new cen- following criteria are used. troid. In step 2 centroids are solely documents. After the Single link method interprets similarity as the short- first recalculation of centroids it could be not a document est segment between documents in separate clusters: but a point in the space Rm . Step 4: repeat the 2nd and 3rd steps while centroids do dists (U, V ) = min dist(xi , yj ), (6) xi ∈U,yj ∈V not change their position and documents do not migrate among clusters. According to a complete link method, similarity is The main criteria of k-means clustering is SSE: the longest segment between documents in separate clusters: k X X SSE = dist(ci , d)2 (5) distc (U, V ) = max dist(xi , yj ), (7) xi ∈U,yj ∈V i=1 x∈Ci average link – similarity is the segment between the where ci is a centroid of Ci cluster, d is a document in Ci average value of clusters: cluster. X X dist(xi , yj ) This criteria can be treated as an optimization problem and dista (U, V ) = (8) then minimize SSE is an objective function [1], [2]. v U nV xi ∈U yj ∈V INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR INTEGRATED CIRCUITS AND SYSTEMS, VOL. 5, NO. 2, DECEMBER 2014 3 TABLE II With Ward method two clusters are the closest if S TRUCTURE OF EACH CLASS . after merging SSE increases the least: Class ID Title # of Documents ||Ū − V̄ ||2 distw (U, V ) = 1 1 (9) (1) Economy 500 nU + nV (2) Energetics 328 (3) Disasters 490 Here, U , V - clusters, xi , yj - documents, nU , nV - (4) Policy 500 number of elements in clusters U and V respectively, Ū , (5) Entertainment 480 (6) Sport 495 V̄ - the mean of clusters U and V respectively. (7) Technology 350 Experiments have shown that results of single link, com- Overall 3143 plete link and average link are very poor, while the results of Ward method and k-means are quite similar. Step 4: repeat 2nd and 3rd steps while only one cluster IV. E XPERIMENTAL E VALUATION is left. A. Dataset E. Clustering Quality Evaluation All experiments were performed with Internet media texts If documents were assigned to the right class, the model corpora in the Azeri language. Corpora consists of 3143 can be considered as suitable for the document set. Indexes documents and each of them is characterized by 118714 (evaluation measures) are the best way to check suitability. features. Table II describes the structure of each class. In this paper we used the following methods: precision, recall, F-value, purity and Rand index. All indexes require to form confusion matrix. The following contingency table is B. Experiments computed in accordance with the confusion matrix [3], [15], [1], [2]: Clustering algorithms were executed with two different distance measures and two feature representation methods. TABLE I C ONTINGENCY TABLE . Clustering results were evaluated in subsection III-E. Statistical tool R [22] was chosen for experiments. Relevant Not relevant First of all we formed 3143 × 118714 size BOW feature Retrieved True positive (tp) False positive (fp) Not retrieved False negative (fn) True negative (tn) matrix. To reduce clustering time and memory requirements we removed terms which occur in more than 2/3 of documents. Let us assume that we know information about real classes, Features which occur less than in 3 documents were removed then contingency table helps to estimate the following indexes. as insignificant, as well. Thus, only 34,88% of features have Precision –The fraction of selected documents that are left. The size of the reduced feature matrix is 3143 × 441406. relevant [2]: From such matrix TF-IDF feature matrix was calculated. tp We use random baseline for the evaluation of results: each P = ∈ [0, 1]. (10) document is assigned to one of 7 classes at random ten times. tp + f p After this we estimated values of indexes and presented the Recall – the fraction of relevant documents that are retrieved results as mean and standard deviation. [2]: tp Clustering results are presented in table III: HWE - R= ∈ [0, 1]. (11) hierarchical Ward method with Euclidean distance, HWC tp + f n - hierarchical Ward method with Cosine distance, KM - F-measure is a harmonic mean of P and R [2]: K-means method with Euclidean distance, SKM - Spherical 2P R K-means with Cosine similarity. Experiments with clustering F = . (12) P +R algorithms KM and SKM were repeated 10 times and results Index F varies in the interval [0, 1]. Higher value are presented by mean ± standard deviation of index values. means better clustering. High values of all indexes in result table III show that Rand Index – It measures the probability of the right cosine distance is very effective and appropriate dissimilarity decisions. measure for document clustering despite the way of document tp + tn representation. Comparing the results of BOW and TF-IDF RI = ∈ [0, 1]. (13) tp + f p + f n + tn can be said that feature representation method TF-IDF is more Purity: effective because execution time is shorter and results of SKM 1X method with TF-IDF matrix completed the best clustering purity(U, V ) = max(ui ∩ vj ). (14) of all methods which were experimented. It is possible that n i j deeper research of representation matrix could help to make Here U = (u1 , u2 , ..., ui ), V = (v1 , v2 , ..., vj ) are SKM execution time shorter and positively effect clustering clusters. Index sums the most popular class objects results. It is important to note that all methods showed better in each cluster and divides by number of objects results than random baseline. n. purity(U, V ) ∈ [0, 1], higher value means better clustering. INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR INTEGRATED CIRCUITS AND SYSTEMS, VOL. 5, NO. 2, DECEMBER 2014 4 Fig. 1. Chart of clustering quality. TABLE III C LUSTERING RESULTS . Method P R F RI purity Relative duration, HWE 0.302 0.359 0.328 0.82 0.41 642.41 HWC 0.814 0.698 0.752 0.913 0.696 5.82 BOW KM 0.214 ± 0.008 0.261 ± 0.009 0.235 ± 0.008 0.796 ± 0.003 0.326 ± 0.021 10.78 SKM 0.723 ± 0.053 0.674 ± 0.055 0.698 ± 0.054 0.905 ± 0.015 0.673 ± 0.048 279.01 HWE 0.301 0.318 0.309 0.802 0.341 642.99 HWC 0.692 0.54 0.606 0.88 0.603 1.00 TF-IDF KM 0.264 ± 0.049 0.25 ± 0.018 0.255 ± 0.023 0.793 ± 0.008 0.298 ± 0.037 9.31 SKM 0.821 ± 0.07 0.794 ± 0.073 0.807 ± 0.072 0.948 ± 0.019 0.827 ± 0. 054 211.95 Random baseline 0.161 ± 0.017 0.161 ± 0.017 0.161 ± 0.017 0.754 ± 0.076 0.176 ± 0.018 – V. C ONCLUSIONS R EFERENCES [1] P.-N. Tan, M. Steinbach, and V. Kumar, Introduction to Data Mining, a) Results: Experiments were performed with (First Edition). Boston, MA, USA: Addison-Wesley Longman Pub- lishing Co., Inc., 2005. 1) Azeri corpora. [2] C. D. Manning, P. Raghavan, and H. Schütze, Introduction to Infor- mation Retrieval. New York, NY, USA: Cambridge University Press, 2) Two document representation techniques, namely BOW 2008. and TF-IDF. [3] M. Kantardzic, Data Mining: Concepts, Models, Methods and Algo- 3) Two dissimilarity measures: Euclidean and cosine. rithms. New York, NY, USA: John Wiley & Sons, Inc., 2002. 4) Three clustering methods: k-means, spherical k-means [4] E. M. Rasmussen, “Clustering algorithms,” in Information Retrieval: Data Structures & Algorithms, 1992, pp. 419–442. and hierarchical clustering with Ward linkage. [5] G. Ciganait, A. Mackut-Varoneckien, and T. Krilaviius, “Text documents 5) Clustering results were evaluated using precision, recall, clustering,” Informacins technologijos. XIX tarpuniversitetin magistrant F-score, Rand index and purity criteria and compared ir doktorant konferencija ”Informacin visuomen ir universitetins studi- jos” (IVUS 2014) : konferencijos praneim mediaga, 2014. with each other and random baseline. [6] T. Krilavičius, Ž. Medelis, J. Kapočiūtė-Dzikienė, and T. Žalandauskas, “News media analysis using focused crawl and natural language pro- cessing: Case of lithuanian news websites,” in Information and Software b) Conclusions: Technologies. Springer, 2012, pp. 48–61. [7] A. Mackut-Varoneckien and T. Krilaviius, Empirical Study on Unsuper- 1) The best results were achieved using TF-IDF, spherical vised Feature Selection for Document Clustering. IOS Press, 2014. k-means and cosine dissimilarity. [8] I. S. Dhillon, Y. Guan, and J. Kogan, “Refining clusters in high dimensional text data,” in Proceedings of the Workshop on Clustering 2) All methods have shown better results than random High Dimensional Data and its Applications, Second SIAM International baseline. Conference on Data Mining. SIAM, 2002, pp. 71–82. [9] C. Potts, “Distributional approaches to word meanings,” 2013. [10] J. Ramos, “Using tf-idf to determine word relevance in document c) Future plans: queries.” [11] J. Zobel and A. Moffat, “Exploring the similarity space,” SIGIR FO- RUM, vol. 32, pp. 18–34, 1998. 1) Reduction of feature matrix for faster and more precise [12] B. K. W and et al., “Clustering more than two million biomedical clustering. publications: comparing the accuracies of nine text-based similarity 2) Features as symbolic n-grams. approaches,” PLOS ONE, vol. 6, March 2011. 3) Outliers analysis. [13] A. K. Jain, M. N. Murty, and P. J. Flynn, “Data clustering: A review,” 1999. 4) Determination of number of clusters. [14] A. Singh, A. Yadav, A. E. Block, A. Rana, E. Block, and G. Floor, 5) Experiments with more clustering methods. “K-means with three different distance metrics.” INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR INTEGRATED CIRCUITS AND SYSTEMS, VOL. 5, NO. 2, DECEMBER 2014 5 [15] M. Steinbach, G. Karypis, and V. Kumar, “A comparison of document Tomas Krilavičius received PhD degree in Com- clustering techniques,” in In KDD Workshop on Text Mining, 2000. puter Science from University of Twente, Enschede, [16] K. Hornik, I. Feinerer, M. Kober, and C. Buchta, “Spherical k-means The Netherlands, in 2006. Now he works at In- clustering,” Journal of Statistical Software, vol. 50, no. 10, pp. 1–22, formatics faculty, Vytautas Magnus University and 2012. Baltic Institute of Advanced Technology. His current [17] V. ekanaviius and G. Murauskas, Statistika 2. TEV, 2002. research interests include robotics, language tech- [18] T. M. Kodinariya and P. R. Makwana, “Rewiew on determining number nologies and data mining. of cluster in k-means clustering,” International journal of Advance Research in Computer Science and Management Studies, 2013. [19] R. Tibshirani, G. Walther, and T. Hastie, “Estimating the number of clusters in a dataset via the gap statistic,” vol. 63, pp. 411–423, 2000. [20] I. S. Dhillon, Y. Guan, and J. Kogan, “Refining clusters in high dimensional text data,” in Proceedings of the Workshop on Clustering High Dimensional Data and its Applications, Second SIAM International Conference on Data Mining. SIAM, 2002, pp. 71–82. Greta Ciganaitė received bachelor degree in math- [21] S. Zhong, “Efficient online spherical $k$-means clustering,” in Proc. ematics at Vytautas Magnus University (Kaunas, 2005 IEEE International Joint Conference on Neural Networks, vol. 5, Lithuania) in 2015. Main research interests are statis- 2005, pp. 3180–3185. tics and data mining. Currently she is working on [22] R. Ihaka and R. Gentleman, programming language R. [Online]. text documents clustering. Available: http://www.r-project.org/ Aušra Mackutė-Varoneckienė received PhD degree in Informatics at Vytautas Magnus University (Kau- nas, Lithuania) in 2007. Currently she is researcher and lecturer at Informatics faculty, Vytautas Magnus University. Main research interests are data mining, text mining, global optimization, multiobjective op- timization, multidimensional data visualization. INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR INTEGRATED CIRCUITS AND SYSTEMS, VOL. 5, NO. 2, DECEMBER 2014 6 Undergraduate Cross-Discipline Integrated Learning through Designing a Smart Hierarchical Power Conversion System Chi-Un Lei, Christopher H.T. Lee, T.O. Kwan, C.K. Lee, K.B. Huang, R.Y.K. Kwok Abstract—The manuscript describes the design of a smart • Problems encountered and experiences gained in the hierarchical power conversion system as a project vehicle in a prototyping stage have been summarized. cross-discipline integrated design project (IDP) course. A three-layer hierarchical design process has been used to design the II. REQUIREMENTS OF THE PROJECT VEHICLE project vehicle: electrical circuit level, feedback control system level and decision support network level. This project allows According to Kolb's learning cycle [12], for learning to take senior undergraduate students to consolidate their technical place in experiential learning courses (e.g. design courses), the knowledge and design skills of feedback control systems, energy project vehicle should be designed carefully. In particular, the storage systems, big data analysis systems and high-power vehicle should be designed, such that the following events can electrical systems. Since students learn experientially, the project is also useful to motivate students towards adapting electrical be accomplished: system design as well as provide solid learning evidence to their • concrete experiencing (i.e. working actively, instead of future employers, in the era of Internet of Things and Big Data. simply watching or reading), • reflective observation (i.e. observe and reflect what has Index Terms—cross-discipline learning, data sciences, design been done and experienced), project, energy conversion, project-based learning, project • abstract conceptualization (i.e. frame the observation), and vehicle. • active experimentation (i.e. put what they have learnt into practice). I. INTRODUCTION Meanwhile, in order to help students equip product design R skills, the project vehicle should help students master the ECENTLY, emerging student learning technologies and following contents: process have been introduced to reshape the scope of engineering education [1−6]. In particular, in order to assess • design principles of an integrated system, students’ competence comprehensively, various project-based • design techniques of electronic systems, learning curricula have been revamped. In our department, we • use of computer-aided design tools and equipment for have also reformulated the cross-discipline integrated design building electronic systems, project (IDP) course. We hope that through the revamped IDP, • integrated knowledge and skills from different electrical senior undergraduate students in teams can have an opportunity and electronic engineering disciplines (i.e., computer to apply and integrate their knowledge and skills in practices, to engineering, electronic engineering and electrical implement a practical electrical/electronic system, in the era of engineering), and Internet of Things (IoT) and Big Data [7−11]. In order to assist • techniques of problem solving and project management in students learn effectively and solidly, project vehicle (i.e. the a mixed design team. product to be designed) has to be designed carefully. Thus, the project vehicle should have a clear design purpose, In this paper, we discuss how a smart energy converter can functionality and hierarchy, such that students are assisted to be used as a project vehicle in our IDP course. Contributions of conceive, design and implement an electronic system [13]. In our paper are as follows: the course, the project vehicle contains the following modules: • Pedagogical requirements and technical requirements of • electrical circuits that interacts with physical quantities, the project vehicle have been described. including high-power quantities, • feedback control systems that integrate actuators, sensors • Design of the smart power conversion system has been and microcontrollers for processing, and outlined, based on an intelligence hierarchy. • decision support networks that turn external and internal data into actionable knowledge for the system This research is partially supported by the Research Development Fund (RDF-13-01-13) from Xi'an Jiaotong-Liverpool University, China. Chi-Un Lei, Christopher H.T. Lee, T.O. Kwan are with the Department of Electrical and Electronic Engineering, University of Hong Kong, Hong Kong. Email: culei@eee.hku.hk INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR INTEGRATED CIRCUITS AND SYSTEMS, VOL. 5, NO. 2, DECEMBER 2014 7 Peltier (With Sensors) 48V AC AC-DC DC Storage and PWM Motor Motor A Current Source Converter Stabilizer Controller (With Sensors) Electrical Circuit Power Microcontroller Motor B Level Current Sensors Converter (Intel 8051) (With Sensors) Feedback Microcontroller Control System (Arduino UNO) Level Microcontroller Decision Support (Arduino UNO “High power” Network Level with WIFI Shield) “Low power” Data Fetching Channel Data Device Data Weather Data and Writing Analysis Distribution Aggregation Fig. 1 Block diagram of the proposed energy conversion system. peltier and blower fans to perform a full-load operation, but can III. DESIGN OF THE SMART POWER CONVERSION SYSTEM charge up capacitors one by one. However, when the Based on requirements described in Section II, a smart temperature has to be lowered in a short period of time, charged energy conversion system for temperature regulations in smart capacitors can be discharged to provide an extra power for fans laboratories [3] has been proposed as the project vehicle. and the peltier, in order to perform a full-load operation Besides circuits for sensing and actuating, feedback control and temporarily (e.g. 15 seconds). Operation control of capacitors, decision support have been added to enhance the functionality fans and peltier are handled by an Intel 8051 microcontroller, of the system. The block diagram of the system is shown in Fig. through a battery management system configuration. We have 1. Through designing the system, students can explore the provided a standard topology for students to imitate the design following topics: process. A prototype (as shown in Fig. 2) has been developed • Control of thermoelectrical cooling systems for demonstrations. Meanwhile, students are encouraged to • Power storage and regulations revise the standard and develop their own design, according to their strengths and limitations. • Feedback control via open-source hardware • Decision support via big data analysis B. Feedback Control System Level A. Electrical Circuit Level An open-source microcontroller board Arduino is used for providing feedback to circuits and establishing a closed-loop In order to regulate the environment, a solid-state feedback control. In the system, sensors are connected to the thermoelectric heat pump (i.e. a peltier device) is used here to board for measuring temperatures, currents and other physical transfer heat from air in metal ventilation ducts to the ambient. quantities. Based on the measurement, feedback control signals Two blower fans are placed at the opening of ventilation ducts, (e.g. desired fan speed and delivery power of the peltier) are in order to bring air out from the ducts. The current/power sent from the Arduino board to inform the Intel MCS-51 supplied to electrical devices (i.e. the system cooling strength) microcontroller board. Multi-thread control and external is controlled by a pulse-width modulation power driver. interrupt control are used with teacher/community guidance. For safety reasons, the “high-voltage” input power source is LCD panel is also installed for displaying messages to users. In replaced by a 48V AC current source. Furthermore, an array of the prototyping stage, we discovered that there may be large capacitors is used as a temporarily power boosting device. insufficient input/output (I/O) ports for sensing and actuating in In normal situations, supplied power is not enough for the some situations. Thus, students have to learn to use INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR INTEGRATED CIRCUITS AND SYSTEMS, VOL. 5, NO. 2, DECEMBER 2014 8 REFERENCES [1] N. Paulino, J.P. Oliveira, R. Santos-Tavares, "The design of an audio power amplifier as a class project for undergraduate students," in Proc. IEEE ISCAS, pp. 2565-2568, May 2013. [2] C.-U. Lei, H. K.-H. So, E. Y. Lam, K. K.-Y. Wong, R. Y.-K. Kwok, and C. K. Chan, “Teaching introductory electrical engineering: a project-based learning experience,” in Proc. IEEE TALE, Aug. 2012 [3] C.U. Lei, K.L. Man, H.-N. Liang, E.G. Lim, K. Wan, “Building an Intelligent Laboratory Environment via a Cyber-Physical System,” International Journal of Distributed Sensor Networks, vol. 2013, Article ID 109014, 9 pages, 2013 [4] C.-U. Lei, “Teaching Introductory Circuits and Systems: Enhancing Learning Experience via Iterative Design Process and Pre-/Post-Project Learning Activities,” in Proc. IEEE ISCAS, pp. 2413-2416, Jun 2014. [5] C.-U. Lei, N. Wong, K.L. Man, “Integration of a Wireless Sensor Network Project for Introductory Circuits and Systems Learning,” in Fig. 2. Implementation of the project vehicle (Electrical circuit level Proc. IEEE ISCAS, pp. 2569-2572, May 2013. and decision feedback system level) in the prototyping stage. [6] C.-U. Lei, C. H.T. Lee, T.O. Kwan, C.K. Lee, K.B. Huang, R.Y.K. Kwok, K.L. Man, “The Design of a Smart Power Conversion System as an multiplexing techniques (via shift registers) for saving I/O Undergraduate Cross-Discipline Integrated Design Project”, in Proc. ports. IEEE ISOCC, Nov. 2014. [7] Michael E. Porter, James E. Heppelman, “How Smart, Connected C. Decision Support Network Level Products Are Transforming Competition”, Harvard Business Review, vol. 92, no. 11, Nov. 2014. An Arduino with a WIFI shield is used to make high-level [8] M. Iansiti, K. R. Lakhani, "Digital Ubiquity: How Connections, Sensors, control judgments as well as exchange data between the system and Data Are Revolutionizing Business", Harvard Business Review, vol. and the internet. In particular, the system can aggregate 92, no. 11, Nov. 2014. [9] G.F. Hurlburt, J. Voas, "Big Data, Networked Worlds," Computer, real-time data via APIs of online services (e.g. weather vol.47, no.4, pp.84-87, Apr. 2014. information and user schedules), as well as distribute data to [10] G. Kortuem, A.K. Bandara, N. Smith, M. Richards, M. Petre, "Educating online internet-of-things (IoT) channels for detailed analysis the Internet-of-Things Generation," Computer, vol.46, no.2, pp.53-61, Feb. 2013. through Matlab. Through these interfaces, analytic charts and [11] L. Trappeniers et al. "The Internet of Things: the Next Technological construct exploratory summaries of data can be shown to users Revolution," Computer, vol. 46, no. 2, pp. 24-25, Feb, 2013. in support of manual control decisions. Furthermore, the [12] David A. Kolb, “Experiential learning: Experience as the source of learning and development.” Englewood Cliffs, NJ: Prentice-Hall, 1984. system has installed LEDs and an infrared remote controller for [13] Edward F Crawley, “Creating the CDIO syllabus, a universal template for notifications and manual control. engineering education,” in Proc. FIE, pp. F3F-8-F3F-13, 2002. In order to connect to the internet, WIFI shield has been used. Furthermore, I2C has been to communicate between other Arduino broads. Thus, open-source peripheral libraries have been used for JSON decoding, network communications, service API communications and inter-board communications. In the prototyping stage, we discovered that there may be insufficient internal memory for network communications and using online services in some situations. Thus, students have to perform tradeoff analysis and design a slim program for memory saving. Through designing, students have to learn techniques for data exchanging, analysis and visualization, which are valuable skills in the coming Big Data Era. IV. CONCLUSIONS In this paper, we have shown how a smart hierarchical power conversion system can be used as a project vehicle for an integrated design project. In particular, we have developed a smart cooler for smart laboratories as the standard prototype. We hope that through designing the conversion system, students are better equipped to learn other advanced EEE materials and practically design electronic systems for their future career development in the era of Internet of Things and Big Data. INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR INTEGRATED CIRCUITS AND SYSTEMS, VOL. 5, NO. 2, DECEMBER 2014 9 HDL SoC TAB-model for Diagnosis and Repair Vladimir Hahanov, Baghdadi Ammar Awni Abbas, Eugenia Litvinova, Svetlana Chumachenko Abstract —This article describes technology for diagnosis SoC An analytical model for verification by using a temporal HDL-models, based on transaction graph. Diagnosis method is assertion (additional observation statements or lines) is focused to decrease the time of fault detection and memory for focused to achieve the specified diagnosis depth and storage of diagnosis matrix by means of forming ternary presented as follows: relations between test, monitor, and functional component. The following problems are solved: creation of digital system model Ω = f (G, A, B, S, T), in the form of transaction graph and multi-tree of fault G = (A * B) × S;S = f (T, B); detection tables, as well as ternary matrices for activating functional components of the selected set of monitors by using A = {A1, A 2 ,..., A i ,..., A h }; test patterns; development of a method for analysis of the B = {B1, B 2 ,..., Bi ,..., B n }; activation matrix to detect the faulty blocks with given depth and synthesis logic functions for subsequent embedded S = {S1, S2 ,..., Si ,..., Sm }; hardware fault diagnosis. T = {T1, T2 ,..., Ti ,..., Tk }. (3) Keywords – HDL SoC model; diagnosis; faulty blocks detection; Here G = (A * B) × S is functionality, represented by Code- transaction graph. Flow Transaction (CFT) Graph (Fig. 1); I. TAB-MODEL FOR DIAGNOSIS FAULTY SOC S = {S1 , S 2 ,..., Si ,..., S m } are nodes or software states when COMPONENTS simulating test segments (patterns). Otherwise the graph can The goal is creation of a TAB-matrix model (Tests – be considered as an ABC-graph – Assertion Based Coverage Assertions – Blocks functional) model and diagnosis method Graph. Each state Si = {Si1 , Si2 ,..., Sij ,..., Sip } is determined to decrease the time of testing and memory for storage by by the values of design essential variables (Boolean, register means of forming ternary relations (test – monitor – variables, memory). The oriented graph arcs are represented functional component) in a single table. by a set of software blocks: The problems are: 1) development of digital system HDL-model in the form of a transaction graph for diagnosing functional blocks by using assertion set [1-6,15]; 2) (4) development method for analyzing TAB-matrix to detect The assertion A i ∈ A = {A1 , A 2 ,..., A i ,..., A n } can be minimal set of fault blocks [4-7,13]; 3) Synthesis of logic functions for embedded fault diagnosis procedure [8-11,14]. inserted to each block B i – a sequence of code statements Model for testing a digital system HDL-code is which determines the state of the graph node Si = f (T, B i ) represented by the following xor-relation between the depending on the test pattern The parameters <test – functionality – faulty blocks B*>: assertion monitor, uniting the assertions of incoming arcs A(Si ) = A i1 ∨ A i2 ∨ ... ∨ A ij ∨ ... ∨ A iq can be put on each T ⊕ B ⊕ B* = 0; node. B* = T ⊕ B = {T × A} ⊕ B, (1) which transforms relationship of the components in the TAB-matrix: M = {{T × A}× {B}}, M ij = (T × A)i ⊕ B j. (2) Here, the coordinate of the matrix is equal to 1, if the pair test–monitor (T × A)i detects or activates some faults of the functional block B j ∈ B . B = ( B1B3 B9 ∨ ( B2 B7 ∨ B1B5 ) B11 ) B13 ∨ ∨ (( B1B4 ∨ B2 B6 ) B10 ∨ B2 B8 B12 ) B14 = Vladimir Hahanov, Eugenia Litvinova, and Svetlana Chumachenko = B1B3 B9 B13 ∨ B2 B7 B11B13 ∨ B1B5 B11B13 ∨ are with National University of Radioelectronics, Kharkov, Ukraine. Email: hahanov@kture.kharkov.ua ∨ B1B4 B10 B14 ∨ B2 B6 B10 B14 ∨ B2 B8 B12 B14 . Baghdadi Ammar Awni Abbas is with Baghdad University, Iran. Fig. 1. Example of ABC-graph of HDL-code INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR INTEGRATED CIRCUITS AND SYSTEMS, VOL. 5, NO. 2, DECEMBER 2014 10 The model of HDL-code, represented in the form of on the test pattern T is determined, by forming ABC-graph, describes not only software structure, but also . Detecting faulty functional blocks is based test segments of the functional coverage, generated by using software blocks, incoming to the given node. The last one on xor-operation between the real assertion response vector defines the relationship between achieved on the test variable and TAB-matrix columns space and potential one, which forms the functional coverage . (7) of graph node state . In the aggregate all The faulty block is defined by a vector B j , which gives nodes have to be full state coverage space of software result with minimal number of 1-unit coordinates: variables, which determines the test quality, equal to 100%: h . Furthermore, the assertion set B = min [B j = ∑ (Bij ⊕ A*i )]. j=1, n i =1 (8) that exists in the graph, allows monitoring arcs (code-coverage) and nodes As an addition to the diagnosis model, necessary to describe the following important features of the TAB-matrix: (functional coverage) The assertions on arcs Bi ∈ B are designed for diagnosis of the 1) M i = (Ti × A j ); functional failures in software blocks. The assertions on m n graph nodes Si ∈ S carry information about the quality of 2) ∨ M ij → ∀ M j = 1; test and assertion set for their improvement or complement. i =1 j=1 The ABC-graph makes possible the following: 1) to estimate n the software quality via diagnosability design; 2) to minimize 3) M ij ⊕ M rj ≠ M ij ; the costs for generating tests, diagnosing and correcting the j=1 functional failures by using assertions; 3) to optimize test k synthesis via coverage all arcs and nodes by a minimum set 4) M ij ⊕ M ir ≠ M ij ; of activated test paths. For instance, the minimal test for the i =1 above mentioned ABC-graph has six segments, which 5) log 2 n ≤ k ↔ log 2 B ≤ T activate all existent arcs and as well as nodes: 6) B j = f(T, A) → B ⊕ T ⊕ A = 0. T = S 0 S1S3S 7 S9 ∨ S 0 S1S 4 S8S9 ∨ S 0 S1S5S 7 S9 ∨ (9) ∨ S 0 S 2 S 4 S8 S 9 ∨ S 0 S 2 S 5 S 7 S 9 ∨ S 0 S 2 S 6 S8 S 9 . The features mean: 1) Each row of the matrix is a subset of (5) the Cartesian product between test and monitor. 2) For diagnosing, test segments T = {T1, T2 ,..., Tr ,..., Tk } Disjunction of all matrix rows gives a vector equal to 1-unit over the all coordinates. 3) All matrix rows are distinct, activate transaction paths in the graph model covered all which eliminates the test redundancy. 4) All matrix columns nodes and arcs. Generally, the testing model is represented are distinct, which exclude the existence of equivalent faulty by the Cartesian product M = T × A × B that accordingly has blocks. 5) The number of matrix rows must be greater than the dimension Q = k × h × n. To reduce the amount of the binary logarithm of the number of columns that diagnosys data, separate monitor or assertion point for determines the potential diagnosability of every block. 6) visualization functional blocks activation is assigned to each The diagnosis function of every block depends on the test segment. It makes possible to decrease the matrix complete test and monitors, which must be minimized dimension to Q = n × k and retain all features of the triad without diagnosability reduction. relationship M =< T × A × B > . Pair «test – monitor» are In accordance with 6 test segments activated the following represented by three possible forms: graph nodes paths relatively assertion point S9: (6) T = S0S1S3S7S9 ∨ S0S1S4S8S9 ∨ S0S1S5S7S9 ∨ The method for diagnosis of functional block failure uses ∨ S0S2S4S8S9 ∨ S0S2S5S7S9 ∨ S0S2S6S8S9 , pre-built TAB-matrix (table) M = [M ij ] , where the row is (10) the relation between the test segment and a subset of it will be easy using graph structure to define all functional activated blocks blocks (oriented arcs) activated by test: Ti → A j ≈ (M i1, M i2 ,..., M ij ,..., M in ), M ij = {0,1} , B = B1B3B9 B13 ∨ B 2 B7 B11B13 ∨ B1B5B11B13 ∨ observed by the monitor A j . Column of the table describes ∨ B1B 4 B10 B14 ∨ B 2 B6 B10 B14 ∨ B 2 B8B12 B14 . the relation between the functional blocks, detected on test (11) segments, relatively monitors . The next step allows creating 6 rows of TAB-matrix For faulty blocks diagnosis at the testing procedure, the in the form of relations between test segments and real assertion response (vector) blocks activated respectively (See Table I): INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR INTEGRATED CIRCUITS AND SYSTEMS, VOL. 5, NO. 2, DECEMBER 2014 11 TABLE I 1. It means, the first matrix dimension is a little bit less TAB-MATRIX than the second, but diagnosability is a better in the second variant of matrix, which becomes the winner of the whole. Comparing to the well-known solutions [12], when every cell of a matrix contains all existing assertions the second variant evaluates the following low value: ]log 214[ 14 Q 2 [M (6 × 3 × 14)] = × = 0,2. 6×3 14 So, the TAB-matrix operating by the selected pair test- assertion concurrently allows having the essential advantages The TAB-matrix of paths activation shows the existence in memory size reducing in times with the same of equivalent failure blocks 3 and 9, 8 and 12, on 6 test segments with one assertion point in the graph node 9. The diagnosability value. columns 3 and 9, 8 and 12 are equivalent. To resolve The TAB-matrix diagnosis quality is the ratio of the bit indistinguishability of two pairs faulty blocks it is necessary number needed for identification (recognition) of all blocks to create two additional monitors in the nodes S3 and S6 for related to the real number of code bits, presented by test segments T1 and T6 respectively. As a result, three the product of test length and number of assertions T × A . assertions in the nodes allow distinguishing If the first part E of quality criterion Q is equal to 1 and all faulty blocks of software HDL-code. Thus, the graph every block with functional failures is recognized in the field enables not only to synthesize the optimal test, but also to of the rest components N d = N , it means a test and determine the minimal number of assertion monitors in the assertions are optimal, that gives the best quality criterion of nodes to detect faulty blocks with a given diagnosis depth. diagnosis model Q=1. The purpose of the ABC-graph analysis is structured II. DESIGN FOR DIAGNOSABILITY evaluation of assertion monitor placement, which make Diagnosability is the relationship D = between possible to obtain maximal diagnosis depth of fault blocks. Diagnosability of the ABC-graph is a function depending on the recognized faulty blocks amount N d , (when there are the number N n of transit not ended nodes where exist only not equivalent components, or the diagnosis depth is equal to 1), and the total number N of HDL-blocks. two adjacent arcs, one of which is incoming, other one is For the expense E evaluation of the TAB-matrix model outgoing. Such arcs form paths though the node without fan- for detecting functional failures, it can use the pair test- in and fan-out branches (N is the total number of arcs in the assertions efficiency for a given diagnosis depth. Criterion E graph): functionally depends on the relation between the ideal . (14) ]log 2 N[×N and real T × A × N memory sizes or resources The estimation N n is the number of unrecognizable or (where T – the test length, A – a number of assertions) equivalent functional blocks. Potential installation of for the corresponding TAB-matrices, which compose the additional monitors for improving diagnosability of failure relative expense reduced to 0-1 intervals: blocks is pure transit nodes composed . The diagnosis ]log 2 N[×N ]log 2 N[ quality criterion of the ABC-graph takes the form: E= = . ]log 2 N[ N - N n T × A ×N T×A Q = E×D = × . (15) (12) T×A N The general diagnosis quality criterion depends on expense E The last expression produce some practical rules for and diagnosability D: synthesis of diagnosable HDL-code: 1) Test or testbench ]log 2 N[ N d must create a minimal number of single activation paths, Q = E×D = × (13) T×A N covered all the nodes and arcs in the ABC-graph. 2) The base number of monitors equals to the end node number of For instance, the diagnosis quality of the TAB-matrix the graph with no outgoing arcs. 3) An additional monitor before and after adding two rows equal to can be placed on each not ended node, which has one ]log 214[ 10 incoming and one outgoing arc. 4) Parallel independent code Q1[M (6 × 1 × 14)] = × = 0,47; blocks must have n monitors and a single concurrent test, or 6×1 14 one integrated monitor and n serial tests. 5) Serially ]log 214[ 14 connected blocks have one activation test for serial path and Q 2[M (8 ×1×14)] = × = 0,5. n-1 monitor, or n tests and n monitors. 6) The graph nodes, 8×1 14 which have more than 1 number of input and output arcs, create good conditions for the diagnosability of the current INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR INTEGRATED CIRCUITS AND SYSTEMS, VOL. 5, NO. 2, DECEMBER 2014 12 section by single path activation tests without installation universal engine in form of algorithm (Fig. 3, block 6) for additional monitors. 7) The test pattern or testbench has to be traversal of tree branches on the depth, specified a priory: 100% functional coverage for the nodes of the ABC-graph. 8) Diagnosis quality criterion as a function depending on the 0 → {B r +1,s , R}; graph structure, test and assertion monitors can always be rs = j B rs j ⊕ A increased close to the 1-value. For this purpose there are two 1 → {B rs , T}. alternative ways. The first one is increasing test segments by j+1, activating new paths for recognition equivalent faulty blocks without increasing assertions, if the software graph structure Here xor-vector-operation is executing the matrix columns allows the potential links. The second way is adding with the assertion (output) response vector A rs , which is assertion monitors on transit nodes of the graph. A third so called hybrid variant is possible, based on the joint determined by the real (m) and gold (g) functionality application of two above-mentioned ways. responses under test patterns based on xor-operation: . If all coordinates of vector xor- III. MULTILEVEL DIAGNOSIS METHOD OF DIGITAL SYSTEM sum B rs rs j ⊕ A = 0 is equal to zero then one of the Multilevel model of the multi-tree B (Fig. 2) is shown, where each node is represented by digital or computer following action is performed: the transition to the activation system component, which has a three-dimensional activation TAB-matrix of functional unit subcomponents. Fig. 2. Diagnosis multitree model The outcoming from the node arcs are transitioning to a lower detailed level in diagnosing process, when replacing faulty block is too expensive: Fig. 3. Engine for traversal of diagnosis multitree n m r p rs k rs B = [Bijrs ], cardB = ∑ ∑ ∑ rs ∑ Bij , (16) matrix of the lower level Brj +1,s or repair of the functional r =1 s =1 i =1 j=1 block . where n is a number of diagnosis multi-tree levels; m r is a One of two analysis ways is executed, what is the most important: 1) the time (t>m, block 10) – then repair of faulty number of functional units or components at the level r; k rs block is performed; 2) the money (t<m) – than a transition ( ) is a number of components (test length) in the table down is specify more exact fault location, because replacement of smaller block decreases the repair cost. If at B rs ; Bijrs = {0,1} is a component of an activation table, least one coordinate of the resulting xor-sum vector is equal which is defined by 1-unit the detected faulty functionality to one B rs rs j ⊕ A = 1 , then transition to the next matrix under the test segment T relatively to the observed column is performed. When all coordinates of the assertion i-Ai monitor-assertion A i . Each node-table has the number of vector are equal to zero , fault-free state of a HS- outcoming down arcs equal to the number of functional system is defined. If all vector sums by executig TAB-matrix components, which are represented by activation TAB- column are not equal to zero , it means a test, matrixes as well. generated for detecting the given component of functionality Method for faulty blocks diagnosis Hardware-Software has to be corrected. If more than one wector sum obtained by HS-system, based on multi-tree model, allows creating the executig TAB-matrix column are equal to zero INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR INTEGRATED CIRCUITS AND SYSTEMS, VOL. 5, NO. 2, DECEMBER 2014 13 , it means an assertion engine, created for diagnosis quality criteria allow solving the problems of quasi-optimal coverage for software and hardware blocks by detecting the given component of functionality on the test and assertions. The model shown in Fig. 4 allows represented test has to be supplemented an extra assertion effectively servicing complex HS-system. The advantages monitors. So, the TAB-engine has four end-nodes, where one of this functionality that is invariant to the hierarchical of them is B-good which indicates successful finishing of the levels, lies in simplification of preparation and presentation testing. Anoters three means the intermediate results in the test process, which is nessessary to take into account for the of diagnosis information in the form of minimized incresing a test quality and diagnosis depth by using extra activation table for functional blocks by using test segments. assertions and/or additional test segments generation. In the last case, the effect – time benefits – is obtained via Thus, the graph shown in the Fig. 2, allows realizing introducing the additional infrastructure to the design, Fig. efficient infrastructure IP for the complex technical systems. 5, which allows performing selective testing and diagnosis, The advantages of the TAB-engine, which is invariant to the as well as reprogramming some modules in the faulty hierarchical levels, are the simplicity of preparation and detected blocks. presentation of diagnostic information in the form of minimized activation table of functional blocks on the test segments. Technological model of infrastructure for embedded testing, diagnosis and repairing of faulty blocks (Fig. 4) has three components: 1. Block testing (Unit Under Test – UUT) by using a reference gold model (Model Under Test – MUT) for generating the assertion response vector which dimension corresponds to the number of test patterns. 2. Searching faulty blocks based on analysis of the TAB- matrix. 3. Repairing faulty blocks by replacing the good components from the Spare Primitives. Fig. 5. Infrastructure for testing CS Here (fig. 4) the blocks are shown: Testbench – tests for functional blocks, FC – functional test coverage, F – functional blocks, DI – diagnosis information in form of faulty blocks detection tables, DT – methods and tools for diagnosing, DA – results of diagnosis analysis, FB – faulty functional modules, Repairing – repair of functional modules. The boundary scan cell, shown in Fig. 6, performs service of a single functional cell. Fig. 6. Boundary scan cell IV. CASE STUDY FOR DIAGNOSIS Fig. 4. Model for embedded testing HS-components To illustrate the performance of the proposed model and method the functionalities of three modules of the digital Process model of embedded IP service operates in real time filter of Daubechies [11] are considered below. and allows supporting good state of the HS-system without As a second test case for the practical use of the proposed human actions distantly. The proposed algorithm or TAB- activation model and xor-method TAB-matrix analysis for engine for analysis of TAB-matrix, as well as the introduced INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR INTEGRATED CIRCUITS AND SYSTEMS, VOL. 5, NO. 2, DECEMBER 2014 14 searching faulty blocks is further proposed the synthesis of bins zero={0}; diagnosis matrix for the main graph filter, shown in Fig. 7. bins zero2=(0=>0); } endgroup The rest 12 modules of the transaction graphs, activation TAB-matrices, and logic functions are developed for testing and fault detection in the discrete cosine transform too. A fragment of monitor engine is presented by Listing 2. Listing 2. Code fragment of monitor engine sequence first( reg[7:0] a, reg[7:0]b); Fig. 7. Transaction main-TL graph reg[7:0] d; (!RST,d=a) The graph is associated with the following diagnosis TAB- ##7 (b==d); matrix, which has 6 activated test segments and 8 assertions endsequence (See Table II): property f(a,b); @(posedge CLK) TABLE II // disable iff(RST||$isunknown(a)) TAB-MATRIX first(a,b); !RST |=> first(a,b); endproperty odin:assert property (f(xin,xa7_in)) // $display("Very good"); else $error("The end, xin =%b,xa7_in=%b", $past(xin, 7),xa7_in); Testing of discrete cosine transformation in the environment Riviera, Aldec detects incorrectness in seven rows of HDL-models: The system of diagnosis functions for hardware //add_sub1a <= xa7_reg + xa0_reg;// implementation as a part of Infrastructure IP corresponding to the rows or monitors is followed: Subsequent correcting code allowed obtaining the following code (Listing 3). Listing 3. Corrected code fragment add_sub1a <= ({xa7_reg[8],xa7_reg} + {xa0_reg[8],xa0_reg}); add_sub2a <= ({xa6_reg[8],xa6_reg} +{xa1_reg[8],xa1_reg}); add_sub3a <= ({xa5_reg[8],xa5_reg} +{xa2_reg[8],xa2_reg}); add_sub4a <= ({xa4_reg[8],xa4_reg} + {xa3_reg[8],xa3_reg}); Synthesis of the diagnosis matrix for one discrete cosine end transform module from the Xilinx library in the form of else if (toggleA == 1'b0) functional coverage is shown in Listing 1. begin add_sub1a <= ({xa7_reg[8],xa7_reg} - Listing 1. Part of functional coverage {xa0_reg[8],xa0_reg}); c0: coverpoint xin add_sub2a <= ({xa6_reg[8],xa6_reg} - { {xa1_reg[8],xa1_reg}); bins minus_big={[128:235]}; add_sub3a <= ({xa5_reg[8],xa5_reg} - bins minus_sm={[236:255]}; {xa2_reg[8],xa2_reg}); bins plus_big={[21:127]}; add_sub4a <= ({xa4_reg[8],xa4_reg} - bins plus_sm={[1:20]}; {xa3_reg[8],xa3_reg}); bins zero={0}; } Practical implementation of models and verification c1: coverpoint dct_2d methods is integrated into the simulation environment { Riviera of Aldec Inc., Fig. 8. New assertion and diagnosis bins minus_big={[128:235]}; bins minus_sm={[236:255]}; modules, added into the system, improved the existing bins plus_big={[21:127]}; verification process, which allowed 15% reduces the design bins plus_sm={[1:20]}; time of digital product. INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR INTEGRATED CIRCUITS AND SYSTEMS, VOL. 5, NO. 2, DECEMBER 2014 15 Actually, application of assertions makes possible to implemented in hardware with certain constraints on a subset decrease the length of test-bench code and considerably of the supported language structures. Products Riviera reduce (х3) the design time (Fig. 9), which is the most including the components of assertion temporal verification, expensive. Assertion engine allows increasing the diagnosis which allow improved the design quality for 3-5%, currently, depth of functional failures in software blocks up to level 10- occupies a leading position in the world IT market with the 20 HDL-code statements. number of system installations of 5,000 a year in 200 companies and universities in more than 20 countries. V. CONCLUSION 1. Infrastructure and technology for digital systems analysis are presented. Proposed transactional graph model and method for diagnosis of digital systems-on-chips are focused to considerably reducing the time of faulty blocks detection and memory for storing the diagnosis compact matrix describing ternary relations in format: the monitor- oriented test-segments which detect faulty functional components of the Hardware-Software system. Fig. 8. Implementation of results in the system Riviera 2. New diagnosis quality criterion as a function depending on the graph structure, test, and assertion monitors Due to the interaction of simulation tools and assertion is proposed. For this purpose there are two alternative ways. engine, automatically placed inside the HDL-code, an access It allows making good choices in diagnosability improving of diagnosis tools to the values of all internal signals is by increasing test segments set for recognition equivalent appeared. This allows quickly identifying the location and faulty blocks or adding assertion monitors on transit nodes of type of the functional failure, as well as reducing the time of the activation HDL-code graph. error detection in the evolution of product with top-down 3. An improved TAB-engine or algorithm for functional design. Application of assertion for 50 real-life designs (from failures detection in software or hardware is proposed. It is 5 thousand up to 5 million gates) allowed obtaining hundreds characterized by using the xor-operation, which makes of dedicated solutions, included in the verification template possible to improve the diagnosis performance for single and library VTL, which generalizes the most popular on the multiple faulty blocks on the basis of parallel analysis of the market EDA (Electronic Design Automation) temporal TAB-matrix, boundary scan standard IEEE 1500, and verification limitations for the broad class of digital products. vector’s operations called and, or, xor. Software implementation of the proposed system for 4. A model for diagnosing the functionality of system-on- analyzing assertions and diagnosing HDL-code is part of a chip in the form of multi-tree and method for tree traversal, multifunctional integrated environment Aldec Riviera for implemented in the engine for detecting faulty blocks with simulation and verification of HDL-models. given depth, are developed. They considerably increase the Time-to-market comparison performance of software and hardware Infrastructure IP. 30,00 5. Test verification of the diagnosis method is performed by three real case studies, presented by SoC components of a Time-to-market (KMen/Hour) 25,00 Design + Classic Testbench Design + Stimulus + Assertions cosine transform filter, which showed the consistency of the 20,00 results in order to minimize the time of faulty blocks 15,00 detection and memory for storing diagnosis information, as well as increase the diagnosis depth of digital unit. 10,00 5,00 REFERENCES 0,00 0,112 0,207 0,315 0,389 0,504 0,620 0,731 0,824 0,931 1,015 [1] P.P. Parhomenko, “Technical diagnosis basics” Moscow: Energy, Design capacity (MGates) 1976. [2] P.P.Parhomenko, and E.S. Sogomonyan, “Technical diagnosis basics Fig. 9. Comparative analysis of verification methods (Optimization of diagnosis algorithms, hardware tools)”, Moscow: Energy, 1981. High performance and technological combination of [3] M.F. Bondarenko, O.A. Guz, V.I. Hahanov, and Yu.P. Shabanov- assertion analysis system and HDL-simulator of Aldec Kushnarenko, “Infrastructure for brain-like computing”, Kharkov: Novoye Slovo, 2010. Company is largely achieved through integration with the [4] V.I. Hahanov, I.V. Hahanova, E.I. Litvinova, and О.А. Guz, “Design internal simulator components, including HDL-language and Verification of digital systems on chips”, Kharkov: Novoye compilers. Processing the results of the assertion analysis Slovo, 2010. system is provided by a set of visual tools of the Riviera [5] V.V. Semenets, I.V. Hahanova, and V.I. Hahanov, “Design of digital environment to facilitate the diagnosis and removal of systems by using VHDL language”, Kharkov: KHNURE, 2003. functional failures. The assertion analysis model can also be [6] V.I. Hahanov, and I.V. Hahanova, “VHDL+Verilog = synthesis for minutes”, Kharkov: KHNURE, 2006. INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR INTEGRATED CIRCUITS AND SYSTEMS, VOL. 5, NO. 2, DECEMBER 2014 16 [7] IEEE Standard for Reduced-Pin and Enhanced-Functionality Test [12] N. C. Umerah, and V. Hahanov, “A diagnostic model for detecting Access Port and Boundary-Scan Architecture IEEE Std 1149.7-2009. functional violation in HDL-code of SoC” Proc. of IEEE East-West [8] F. Da Silva, T. McLaurin, and T. Waayers, “The Core Test Wrapper Design and Test Symposium.– Sevastopol, Ukraine.– 19-20 Handbook. Rationale and Application of IEEE Std. 1500™,” September, pp. 299-302, 2011. Springer, 2006, XXIX. [13] R. Ubar, S. Kostin, and J. Raik, “Block-Level Fault Model-Free [9] E.J. Marinissen, and Yervant Zorian, “Guest Editors' Introduction: Debug and Diagnosis in Digital Systems. DSD '09. 12th Euromicro The Status of IEEE Std 1500,” IEEE Design & Test of Computers, Conference 2009, pp. 229 – 232. No26(1), pp.6-7, 2009. [14] Y. Benabboud, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, [10] A. Benso, S. Di Carlo, P. Prinetto, and Y. Zorian, “IEEE Standard L. Bouzaida, and I. Izaute, "A case study on logic diagnosis for 1500 Compliance Verification for Embedded Cores,” IEEE Trans. System-on-Chip," Quality of Electronic Design, 2009, pp.253,259. VLSI Syst., No 16(4), pp. 397-407, 2008. [15] K. Datta, and P.P. Das, “Assertion based verification using HDVL,” [11] V.I. Hahanov, E.I. Litvinova, S.V. Chumachenko, and O.A. Guz, Proceedings 17th International Conference VLSI Design. 2004, pp. “Logic associative computer,” Electronic simulation, No 1, pp.73-83, 319 – 325. 2011. INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR INTEGRATED CIRCUITS AND SYSTEMS The International Journal of Design, Analysis and Tools for Integrated Circuits and Systems (IJDATICS) was created by a network of researchers and engineers both from academia and industry. IJDATICS is an international journal intended for professionals and researchers in all fields of design, analysis and tools for integrated circuits and systems. The objective of the IJDATICS is to serve a better understanding between the community of researchers and practitioners both from academia and industry. Editor-In-Chief Ka Lok Man Xi'an Jiaotong-Liverpool University, China, Assistant Editor-In-Chief David Afolabi Xi'an Jiaotong-Liverpool University, China, Managing Editor Michele Mercaldi, Kaiyu Wan, Tomas Krilavičius, EnvEve, Switzerland Xi'an Jiaotong-Liverpool University, China Baltic Institute of Advanced Technologies, Lithuania Vytautas Magnus University, Lithuania Journal Secretary Jun Wang, Fujitsu Laboratories of America, Inc., USA Linguistic Editor Nigel Julian Dixon, Caren Crowley, Xi'an Jiaotong-Liverpool University, China Katholieke Universiteit Leuven, Belgium Associate Editor Chao Lu Hai-Ning Liang Mou Ling Dennis Wong Arctic Sand Technologies Inc. Cambridge, MA, US Xi'an Jiaotong-Liverpool University, China Swinburne University of Technology, Malaysia Editorial Board Vladimir Hahanov, Kharkov National University of Franck Vedrine, CEA LIST, France Cheng C. Liu, University of Wisconsin at Stout, USA Radio Electronics, Ukraine Bruno Monsuez, ENSTA, France Farhan Siddiqui, Walden University, Minneapolis, Paolo Prinetto, Politecnico di Torino, Italy Kang Yen, Florida International University, USA USA Massimo Poncino, Politecnico di Torino, Italy Takenobu Matsuura, Tokai University, Japan Katsumi Wasaki, Shinshu University, Japan Alberto Macii, Politecnico di Torino, Italy R. Timothy Edwards, MultiGiG, Inc., USA Pankaj Gupta, Microsoft Corporation, USA Joongho Choi, University of Seoul, South Korea Olga Tveretina, Karlsruhe University, Germany Masoud Daneshtalab, University of Turku, Finland Wei Li, Fudan University, China Maria Helena Fino, Universidade Nova De Lisboa, Amit Chaudhry, Technology Panjab University, India Michel Schellekens, University College Cork, Ireland Portugal Bharat Bhushan Agarwal, I.F.T.M., University, India Emanuel Popovici, University College Cork, Ireland Adrian Patrick ORiordan, University College Cork, Abhilash Goyal, Oracle (SunMicrosystems), USA Jong-Kug Seon, System LSI Lab., LS Industrial Ireland Boguslaw Cyganek, AGH University of Science and Systems R&D Center, South Korea Grzegorz Labiak, University of Zielona Gora, Poland Technology, Poland Umberto Rossi, STMicroelectronics, Italy Jian Chang, Texas Instruments, Inc, USA Yeo Kiat Seng, Nanyang Technological University, Franco Fummi, University of Verona, Italy Yeh-Ching Chung, National Tsing-Hua University, Singapore Graziano Pravadelli, University of Verona, Italy Taiwan Youngmin Kim, UNIST Academy-Industry Research Yui Fai Lam, Hong Kong University of Science and Anna Derezinska, Warsaw University of Technology, Corporation, South Korea Technology, Hong Kong Poland Tom English, Xlinx, Ireland Ajay Patel, Intelligent Support Ltd, United Kingdom Kyoung-Rok Cho, Chungbuk National University, Nicolas Vallee, RATP, France Jinfeng Huang, Philips & LiteOn Digital Solutions South Korea Rajeev Narayanan, Cadence Design Systems, Austin, Netherlands, The Netherlands Yuanyuan Zeng, Wuhan university, China TX, USA Thierry Vallee, Georgia Southern University, D.P. Vasudevan, University College Cork, Ireland Xuan Guan, Freescale Semiconductor, Austin, TX, Statesboro, Georgia, USA Arkadiusz Bukowiec, University of Zielona Gora, USA Monica Donno, Minteos, Italy Poland Pradip Kumar Sadhu, Indian School of Mines, India Jun-Dong Cho, Sung Kyun Kwan University, South Maziar Goudarzi, Sharif University of Technology, Fei Qiao, Tsinghua University, China Korea Iran Ding-Yuan Cheng, National Chiao Tung University, AHM Zahirul Alam, International Islamic University Jin Song Dong, National University of Singapore, Taiwan Malaysia, Malaysia Singapore Shin-Il Lim, Seokyeong University, Seoul Korea Gregory Provan, University College Cork, Ireland Dhamin Al-Khalili, Royal Military College of Canada, Pradeep Sharma, IEC College of Engineering & Miroslav N. Velev, Aries Design Automation, USA Canada Technology, Greater M. Nasir Uddin, Lakehead University, Canada Zainalabedin Navabi, University of Tehran, Iran Noida, GB Nagar UP, India Dragan Bosnacki, Eindhoven University of Lyudmila Zinchenko, Bauman Moscow State Ausra Vidugiriene, Vytautas Magnus University, Technology, The Netherlands Technical University, Russia Lithuania Milan Pastrnak, Siemens IT Solutions and Services, Muhammad Almas Anjum, National University of Sheung-Hung Poon, National Tsing Hua University, Slovakia Sciences and Technology (NUST), Pakistan Taiwan John Herbert, University College Cork, Ireland Deepak Laxmi Narasimha, University of Malaya, Lixin Cheng, Suzhou Institute of Nano-Tech and Zhe-Ming Lu, Sun Yat-Sen University, China Malaysia Nano-Bionics (SINANO), Jeng-Shyang Pan, National Kaohsiung University of Danny Hughes, Katholieke Universiteit Leuven, Chinese Academy of Sciences, China Applied Sciences, Taiwan Belgium Yue Yang, Suzhou Institute of Nano-Tech and Nano- Chin-Chen Chang, Feng Chia University, Taiwan A.P. Sathish Kumar, PSG Institute of Advanced Bionics (SINANO), Studies, India Chinese Academy of Sciences, China Mong-Fong Horng, Shu-Te University, Taiwan N. Jaisankar, VIT University. India Yo-Sub Han, Yonsei University, South Korea Liang Chen, University of Northern British Columbia, Canada Atif Mansoor, National University of Sciences and Chien-Chang Chen, Tamkang University, Taiwan Technology (NUST), Pakistan Hui-huang Hsu, Tamkang University, Taiwan Chee-Peng Lim, University of Science Malaysia, Steven Hollands, Synopsys, Ireland Malaysia Siamak Mohammadi, University of Tehran, Iran Hwann-Tzong Chen, National Tsing Hua University, Salah Merniz, Mentouri University, Constantine, Felipe Klein, State University of Campinas Taiwan Algeria (UNICAMP), Brazil Wichian Sittiprapaporn, Mahasarakham University, Oscar Valero, University of Balearic Islands, Spain Enggee Lim, Xi'an Jiaotong-Liverpool University, Thailand Yang Yi, Sun Yat-Sen University, China China Aseem Gupta, Freescale Semiconductor Inc., Austin, Damien Woods, University of Seville, Spain Kevin Lee, Murdoch University, Australia TX, USA Matthieu Moy, Verimag Laboratory, France Prabhat Mahanti, University of New Brunswick, Saint Kevin Marquet, Verimag Laboratory, France Ramy Iskander, LIP6 Laboratory, France John, Canada Brian Logan, University of Nottingham, UK Suryaprasad Jayadevappa, PES School of Engineering, Tammam Tillo, Xi'an Jiaotong-Liverpool University, Asoke Nath, St. Xavier's College (Autonomous), India India China Tharwon Arunuphaptrairong, Chulalongkorn Shanmugasundaram Hariharan, Pavendar Wen Chang Huang, Kun Shan University, Taiwan University, Thailand Bharathidasan College of Engineering and Masahiro Sasaki, The University of Tokyo, Japan Shin-Ya Takahasi, Fukuoka University, Japan Technology, India Shishir K. Shandilya, NRI Institute of Information Shiho Kim, Chungbuk National University, Korea Chung-Ho Chen, National Cheng-Kung University, Science & Technology, India Hi Seok Kim, Cheongju University, Korea Taiwan J.P.M. Voeten, Eindhoven University of Technology, Yanyan Wu, Xi'an Jiaotong-Liverpool University, Kyung Ki Kim, Daegu University, Korea The Netherlands China
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