Kicking off the oscilloscope FPGA project 165 The oscilloscope sampling speed (100 MHz) is not especially fast for a digital oscilloscope. The reason for keeping the speed of ADC sampling at this level is, first, to keep the cost of the parts down. Extremely high-speed ADCs are very costly. The ADC used for this design costs about $37. Second, high-speed circuit design is difficult. Extremely high-speed circuit design is even more difficult. We are only trying to provide an introduction to the issues associated with high-speed circuit design with this project, so limiting the maximum circuit frequency to a reasonable level will help prevent frustration. The use of the Ethernet communication mechanism opens this architecture up for use as an IoT device. Most digital oscilloscopes use USB to connect to a physically nearby host. With our Ethernet connection, the oscilloscope and its user interface could potentially be on opposite sides of the earth. The remainder of this chapter sets up a baseline Vivado design for this project. Baseline Vivado project This project will use a Xilinx MicroBlaze soft processor running the FreeRTOS real-time operating system to perform TCP/IP communications over the Ethernet port on the Arty A7-100. To complete this phase of the project, you will need the following items: • An Arty A7-100T board • A USB cable connecting the Arty board to your computer • An Ethernet cable connecting the Arty board to your local network • Vivado installed on your computer I am assuming you are now a bit familiar with Vivado. Screenshots will only be provided to demonstrate features that have not been seen as part of previous examples. The following bullet points provide an overview of the steps we will perform: • Create a new Vivado project. • Create a block diagram-based representation of a MicroBlaze microcontroller system with interfaces to the following components on the Arty A7 board: DDR3 SDRAM, an Ethernet interface, 4 LEDs, 4 pushbuttons, 4 RGB LEDs, 4 switches, the SPI connector (J6 on the Arty A7 board), and the USB UART. • Define a 25 MHz clock as the reference clock for the Ethernet interface. This clock signal is assigned to the appropriate pin on the FPGA package using a constraint. • Generate a bitstream from the design. 166 Implementing systems with FPGAs • Export the project from Vivado into the Vitis software development environment. • Create a Vitis project that implements a simple TCP echo server. • Run the software on the Arty board and observe messages sent via the UART. • Use Telnet to verify the TCP echo server is working. Let's get started: 1. Begin by creating a project using the steps listed in the Creating a project section in Chapter 4 , Developing Your First FPGA Program . The suggested name for this project is oscilloscope-fpga and the location is C:\Projects\ oscilloscope-fpga 2. Click Create Block Design to open the block design window. You will be prompted for a design name. The default, design_1 , is acceptable: Figure 5.8 – Creating the block design 3. Select the Board tab in the Block Design window. Drag System Clock onto the Diagram window. Kicking off the oscilloscope FPGA project 167 4. Double-click the Clocking Wizard component to open its Re-customize IP dialog. Be sure to double-click the background of the component and not on one of the pin names. 5. Select the Output Clocks tab in the dialog. Check the checkboxes next to clk_out2 and clk_out3 ( clk_out1 should already be checked). Set Output Freq for clk_out1 to 166.66667 MHz, clk_out2 to 200 MHz, and clk_out3 to 25 MHz: Figure 5.9 – Configuring the Clocking Wizard 6. Scroll the Output Clocks window to the bottom and set Reset Type to Active Low Click OK 7. On the Clocking Wizard component, right-click clk_out3 and select Make External from the menu. A port will appear on the diagram. 8. Click on the text clk_out3_0 in the Diagram window. In the External Port Properties window, rename clk_out3_0 to eth_ref_clk 9. Click Run Connection Automation in the green bar. Click OK in the dialog that appears. 10. Drag DDR3 SDRAM from the Board tab into the Diagram window. 168 Implementing systems with FPGAs 11. Delete the clk_ref_i and sys_clk_i external ports from the Memory Interface Generator (click to select each port, then press the Delete key). 12. Click and drag from the clk_out1 pin on Clocking Wizard to the sys_clk_i pin on the Memory Interface Generator to create a connecting wire. 13. Click and drag from the clk_out2 pin on the Clocking Wizard to the clk_ref_i pin on the Memory Interface Generator to create a connecting wire. 14. Place the mouse over the reset port connected to the Clocking Wizard and when it appears as a pencil, click and drag to the sys_rst input on the Memory Interface Generator . This will create another connecting wire. After this step, the diagram should appear as follows: Figure 5.10 – The completed clocking configuration 15. Click the + icon at the top of the Diagram window and type micro in the search box that appears. Select the MicroBlaze entry and press Enter Kicking off the oscilloscope FPGA project 169 16. Click Run Block Automation in the green bar. Select Real-time as the Preset , set Local Memory to 32 KB, and set Clock Connection to /mig_7series0/ui_ clk (83 MHz) . Click OK 17. Click Run Connection Automation in the green bar. In the dialog that appears, check the box next to All Automation and click OK 18. Double-click the MicroBlaze component in the diagram. Step through the numbered pages in the dialog and make the following changes: On Page 2 , uncheck Enable Integer Divider and Enable Additional Machine Status Register Instructions , and check Enable Branch Target Cache . On Page 3 , do not make any changes. On Page 4 , set the Instruction and Data Cache sizes both to 32 kB. On Page 5 , set Number of PC Breakpoints to 6 . No changes are needed on Page 6 Click OK 19. Drag the following items from the Board window into the Diagram window and click OK after adding each one: Ethernet MII , 4 LEDS , 4 Push Buttons , 4 RGB LEDs , 4 Switches , SPI connector J6 , and USB UART 20. Click the + icon at the top of the Diagram window and type timer in the search box that appears. Select the AXI Timer entry and press Enter 21. Click Run Connection Automation in the green bar. In the dialog that appears, check the box next to All Automation . Click OK 22. Find the Concat block on the diagram and double-click it to open the Re-customize IP dialog. Change Number of Ports to 3 and click OK 23. Connect the In0 - In2 ports of the Concat block to the following pins, in order: AXI EthernetLite/ip2intc_irpt , AXI UartLite/interrupt , and AXI Timer/interrupt 24. Press Ctrl + S to save the design. 25. Press F6 to validate the design. Ensure validation is successful with no errors. 26. Select the Sources tab in the Block Design window. Right-click on design_1 under Design Sources and select Create HDL Wrapper . Click OK This completes the block diagram for the initial phase of the project. In the next series of steps, we will add constraints to specify the characteristics of the Ethernet interface clock output pin: 1. Still in the Sources tab, expand Constraints , then right-click on constrs_1 and select Add Sources 170 Implementing systems with FPGAs 2. In the Add Sources dialog, click Next , then click Create File . Name the file arty and click OK , then click Finish 3. Expand the constrs_1 item and double-click arty.xdc to open the file. 4. Insert the following text into arty.xdc : set_property IOSTANDARD LVCMOS33 [get_ports eth_ref_clk] set_property PACKAGE_PIN G18 [get_ports eth_ref_clk] 5. Press Ctrl + S to save the file. Design entry is now complete for this phase of the project. We will now perform the synthesis, implementation, and bitstream generation steps: 1. Under Flow Navigator , click Generate Bitstream . Click Yes in the No Implementation Results Available dialog and OK in the Launch Runs dialog. This process may take several minutes to complete. 2. When the Bitstream Generation Completed dialog appears, click Cancel If there are no errors reported, this completes the first stage of the oscilloscope FPGA development project. Although we have not implemented any logic related to our ADC interface yet, the current design is capable of booting and running a software application. Follow these steps to create and run the code for the TCP echo server: 1. In Vivado, select File | Export | Export Hardware... . Select the Fixed Platform type , then click Next 2. In the Output dialog, select the Include Bitstream option and click Next 3. In the Files dialog, select the directory C:/Projects/oscilloscope- software and click Next . Click Finish to complete the export. 4. Locate the desktop icon titled Xilinx Vitis 2020.1 (or look for your version number, if different) and double-click it. 5. Select the C:\Projects\oscilloscope-software directory for your workspace and launch Vitis: