reset Clock num_in[15:0] i_i RTL_MUX I0[31:0] S=32'sb00000000000000000000000000001000 I1[31:0] S=default O[31:0] S[31:0] i_reg[31:0] RTL_REG_ASYNC C CLR D Q + i0_i RTL_ADD I0[31:0] I1[31:0] V=X"00000001" O[31:0] < i1_i RTL_LT O I0[31:0] I1[31:0] V=X"00000008" i_i__0 RTL_MUX S I0[31:0] S=1'b1 I1[31:0] S=default O[31:0] i_i__1 RTL_MUX I0[31:0] ...32'sb00000000000000000000000000000000 I1[31:0] S=default O[31:0] S[31:0] r_i RTL_MUX I0[9:0] S=32'sb00000000000000000000000000001000 I1[9:0] S=default O[9:0] S[31:0] a_reg[15:0] RTL_REG_ASYNC C CLR D Q r_reg[9:0] RTL_REG_ASYNC C CLR D Q a_i RTL_MUX I0[15:0] S=32'sb00000000000000000000000000000000 I1[15:0] S=default O[15:0] S[31:0] + r0_i RTL_ADD I0[9:0] I1[9:0] O[9:0] - r0_i__0 RTL_SUB I0[9:0] I1[9:0] O[9:0] r_i__0 RTL_MUX S I0[9:0] S=1'b1 I1[9:0] S=default O[9:0] sq_root0_i RTL_INV I0 O q_i RTL_MUX I0[7:0] S=32'sb00000000000000000000000000001000 I1[7:0] S=default O[7:0] S[31:0] done_i__0 RTL_ROM O A[31:0] q_reg[7:0] RTL_REG_ASYNC C CLR D Q done_i__1 RTL_MUX I0 S=32'sb00000000000000000000000000001000 I1 S=default O S[31:0] sq_root_i RTL_ROM O A[31:0] done_i RTL_ROM O A[31:0] sq_root_reg[7:0] RTL_REG_ASYNC C CE CLR D Q done_reg RTL_REG_ASYNC C CE CLR D Q sq_root[7:0] done ... ... ... ... ... 1 9:2 1 9:2 1 9