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Data Sheet — EP92A7E / EP91A7E V0.4 Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED 1 HDMI 2.1 3-In 1-Out Repeater with Audio In/Out, eARC and HDCP 1.4 / 2.3 EP92A7E / EP91A7E Data Sheet V0.4 Original Release Date: Dec. 25, 2017 Revised Date: Apr. 22, 2019 Explore Data Sheet — EP92A7E / EP91A7E V0.4 Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED 2 Revision History Version Number Revision Date Author Description of Changes 0.1 Aug/1/2018 Ken Chen Initial Version 0.2 Sep/28/2018 Ken Chen Add Power Consumption; Revise the Application Note; Revise RX power pin name; 0.3 Dec/21/2018 Ken Chen Add QFN-88 thermal information to TBD; Highlight that support Dolby Atmos; Revise ARC_VDD pin name to VDD; 0.4 Apr/22/2019 Ken Chen Revise suggested VDD voltage to 1.25V; Data Sheet — EP92A7E / EP91A7E V0.4 Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED 3 Section 1 Introduction 1.1 Overview EP92A7E is a 6 GHz HDMI 2.1 3-IN 1-OUT Repeater with HDCP. It is suitable for Home Theater and Bar Speaker applications. The chip supports 3 HDMI input ports. The chip supports HDCP decryption, audio outputs, audio inputs and HDCP re-encryption in repeater mode. The chip also supports HDCP 1.4 to HDCP 2.3 and HDCP 2.3 to HDCP 1.4 conversions. The chip supports Audio Outputs in IIS and SPDIF. The audio for the HDMI output can be from a regenerated LPCM audio source (input from IIS_*_IN pins), eARC RX, ARC RX or the by-passed audio from the selected HDMI input port. The chip supports SD/HD Audio and HD/3D/4K2K Video up to 60 Hz frame rate. The chip also supports eARC (enhanced Audio Return Channel) and ARC (Audio Return Channel) Receiver. This chip supports the SPDIF to IIS conversion to reduce system cost. The chip is also integrated with an eFlash MCU to make user’s applications very easy. EP91A7E is a simple version which has only one input port. 1.2 Features • On-chip 6GHz 3-IN 1-OUT HDMI Repeater with Equalizer (EP92A7E) • On-chip 6GHz 1-IN 1-OUT HDMI Repeater with Equalizer (EP91A7E) • On-chip eFlash MCU with integrated HDCP keys and EDID memory • Support wide Frequency Range: 25MHz - 600MHz TMDS clock • On-chip HDMI Receiver and Transmitter core which are compliant with HDMI 1.4/2.0/2.1 specification • Support HDCP 1.4 to HDCP 2.3 conversion. • Support HDCP 2.3 to HDCP 1.4 conversion. • On-chip HDCP Engine which supports Repeater and is compliant with HDCP 1.4/2.3 specification • Support eARC (enhanced Audio Return Channel) Receiving. • Support eARC U-bits Message Extraction • Support ARC (Audio Return Channel) Receiving. • Support Dolby Atmos. • Audio for HDMI output can be from a regenerated audio source or the by-passed audio from the selected HDMI input port. • Regenerated Audio source can be from external input pins, eARC RX or ARC RX. • Regenerated Audio source can be SPDIF, LPCM (2 or 8 channel) or HBR Data Sheet — EP92A7E / EP91A7E V0.4 Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED 4 • On-chip Audio Decoder which support 8-channel IIS/DSD and SPDIF audio outputs • On-chip SPDIF to IIS converter (LPCM) • Supports Standard Audio, DSD Audio and HD (HBR) Audio • Supports audio soft mute • Controllable tri-state for Audio output pins • Source Signal Detection in Low Power mode • Low stand-by current at power down mode • 128-pin QFN (E-PAD) package for EP92A7E • 88-pin QFN (E-PAD) package for EP91A7E Data Sheet — EP92A7E / EP91A7E V0.4 Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED 5 Section 2 Overview 2.1 Chip Block Diagram Figure 2-1 Block Diagram HDMI / HDCP / CEC / eARC CONTROLLER MCU_XIN MCU_XOUT MCU_RSTb / MCU_OP HPD / DDC / CEC / GPIOs MCU_SDA RSTb X_IN Registers and Control Logics INTb HDCP 2.3 Controller (Build in HDCP Key) MCU_SCL HDMI Repeater HOST_IIC RX00+/- RX10+/- RX20+/- RXC0+/- DDC0_SDA DDC0_SCL RX01+/- RX11+/- RX21+/- RXC1+/- DDC1_SDA DDC1_SCL RX02+/- RX12+/- RX22+/- RXC2+/- DDC2_SDA DDC2_SCL 3-In 1-Out Switch HDMI MHL 7 G RX Input Port 0 IIS_SCK IIS_WS IIS_SD*/DSD* MCLK EDID 0 HDCP 1.4/2.3 TXs HDMI 6G TX TX00+/- TX10+/- TX20+/- TXC0+/- Audio ! Processor IIS/SPDIF/DSD/HBR Processor IIS_SCK_IN IIS_WS_IN IIS_SD_IN SPDIF MUX P_SEL/S_SEL eARC+ eARC- eARC/ARC RX HDMI 6G RX Input Port 1 EDID 1 HDMI 6G RX Input Port 2 EDID 2 Video/Packet Processor GPIO* PLL SPDIF DECODER MUX HDCP 1.4/2.3 RXs SPIDF/IIS* IIS* SPIDF IIS* Data Sheet — EP92A7E / EP91A7E V0.4 Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED 6 2.2 Pin Diagram Figure 2-2 EP92A7E (QFN-128) 9 128 127 126 125 124 123 122 121 120 119 118 RX00+ 117 RX00- 116 RX_PAVDD12 115 RXC0+ 114 RXC0- 113 VDD12 112 VSS 111 H5V_2 110 H5V_1 109 H5V_0 108 VDD_PLL 107 XFC_A 106 VSS_PLL 105 VSS 104 IIS_SD_IN 103 IIS_WS_IN 102 IIS_SCK_IN 101 MCU_VDDE 100 MXU_XO 99 98 MCU_XI 97 RX22+ 32 RX22- 31 RX_AVDD12 30 RX12+ 29 RX12- 28 RX_AVDD33 27 RX_AVDD12 26 RX02+ 25 RX02- 24 RX_PAVDD12 23 RXC2+ 22 RXC2- 21 RX_VSS 20 RX_VDD12 19 EXT_RES 18 RX_AVDD12 16 RX21+ 15 RX21- 14 RX_AVDD12 13 RX11+ 12 RX11- 11 RX_AVDD33 10 RX_AVDD12 RX01+ 8 RX01- 7 RX_PAVDD12 6 RXC1+ 5 RXC1- 4 P33(SDA23) 3 VSS 33 34 35 HPD_0 36 37 eARC+ 38 P15 (rsvd) 39 P14 (rsvd) 40 P07 (rsvd) 41 P06 (TX5V_CTL) 42 P05 (TX_SDA) 43 P04 (TX_SCL) 44 P23 (rsvd) 45 P22 (Soc_INT) 46 P20/P44 (CEC) 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 67 68 TX0+ 69 TX_AVSS 70 TX1- 71 TX1+ 72 TX_AVDD12 73 TX2- 74 TX2+ 75 TX_AVSS 76 COMR 77 GPIO0/RSEN 78 GPIO1/HTPLG 79 EXT_RSTb 80 tOUT0/A0 81 tOUT1/A1 82 tOUT2 83 SDA23 84 SCL23 85 VDD12 86 MCLK 87 VSS 88 SPDIF 89 IIS_SCK 90 IIS_WS 91 IIS_SD0 92 IIS_SD1 93 IIS_SD2 94 95 96 IIS_SD3 A_MUTE GPIO2 GPIO3 VDD12 P32(SCL23) 2 66 TX0- 65 HPD_1 MCU_OP0 MCU_RSTb eARC- VDD12 RX_AVDD12 1 MCU_VSS P30(Soc_SCL) P71(TXD) P70(RXD) RX_AVDD12 RX20+ RX20- RX_AVDD12 RX10+ RX10- RX_AVDD33 RX_AVDD12 P31(Soc_SDA) VSS VDDE RX_SDA2 RX_SCL0 RX_SCL1 RX_SCL2 TX_PVDD12 TX_PVSS TX_AVSS TXC- TXC+ TX_AVDD12 HPD_2 RX_SDA1 RX_SDA0 17 Data Sheet — EP92A7E / EP91A7E V0.4 Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED 7 Figure 2-3 EP91A7E (QFN-88) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 23 24 25 26 27 28 29 31 33 35 22 18 17 36 37 38 39 40 41 42 43 52 54 56 57 58 60 61 62 63 64 65 66 45 46 47 48 49 50 51 88 87 86 85 84 83 82 81 79 77 76 75 74 72 71 70 69 68 67 44 P20 (X24M) P21 (RSTb) P04 (TX_SCL) P05 (TX_SDA) P06 (T5V_CTL) eARC+ eARC- VSS P24/P17 RX_SCL TX_PVDD12 TX_PVSS TX_AVSS TXC- TXC+ TX_AVDD12 TX0- TX0+ TX_AVSS IIS_SD1 IIS_WS IIS_SCK SPDIF VSS MCLK SCL23 SDA23 tOUT1/A1 EXT_RSTb GPIO0 COMR TX_AVSS TX2+ TX2- TX_AVDD12 TX1+ TX1- IIS_SD0 P32 (SCL23) RX0+ RX_AVDD12 RX_AVDD33 RX1- RX1+ RX_AVDD12 RX2- RX2+ RX_AVDD12 EXT_RES RX_VDD RX_VSS P13/P44 (CEC) P33 (SDA23) RXC- RXC+ RX_PAVDD12 RX0- P31 (Soc SDA) VDD12 VSS RX_H5V VDD_PLL VSS_PLL IIS_WS_IN IIS_SCK_IN VDDE MCU_XO VSS VDD12 GPIO3 GPIO2 IIS_SD3 IIS_SD2 P30 (Soc SCL) P71 (TXD) P70 (RXD) 19 MCU_RSTb 20 MCU_OP0 21 P12 30 VDD12 32 RX_HPD 34 RX_SDA 53 GPIO1 55 tOUT0/A0 59 VDD12 73 MCU_XI 78 IIS_SD_IN 80 XFC_A Data Sheet — EP92A7E / EP91A7E V0.4 Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED 8 2.3 Pin Description Unless otherwise stated, unused input pins must be tied to ground, and unused output pins left open. Table 2-1 HDMI Input Ports Name In/Out Description RXC0- IN Differential Clock Input Pair for HDMI Input Port 0 RXC0+ IN Differential Clock Input Pair for HDMI Input Port 0 RX00- IN Differential Data Input Pair0 for HDMI Input Port 0 RX00+ IN Differential Data Input Pair0 for HDMI Input Port 0 RX10- IN Differential Data Input Pair1 for HDMI Input Port 0 RX10+ IN Differential Data Input Pair1 for HDMI Input Port 0 RX20- IN Differential Data Input Pair2 for HDMI Input Port 0 RX20+ IN Differential Data Input Pair2 for HDMI Input Port 0 RXC1- IN Differential Clock Input Pair for HDMI Input Port 1 RXC1+ IN Differential Clock Input Pair for HDMI Input Port 1 RX01- IN Differential Data Input Pair0 for HDMI Input Port 1 RX01+ IN Differential Data Input Pair0 for HDMI Input Port 1 RX11- IN Differential Data Input Pair1 for HDMI Input Port 1 RX11+ IN Differential Data Input Pair1 for HDMI Input Port 1 RX21- IN Differential Data Input Pair2 for HDMI Input Port 1 RX21+ IN Differential Data Input Pair2 for HDMI Input Port 1 RXC2- IN Differential Clock Input Pair for HDMI Input Port 2 RXC2+ IN Differential Clock Input Pair for HDMI Input Port 2 RX02- IN Differential Data Input Pair0 for HDMI Input Port 2 RX02+ IN Differential Data Input Pair0 for HDMI Input Port 2 RX12- IN Differential Data Input Pair1 for HDMI Input Port 2 RX12+ IN Differential Data Input Pair1 for HDMI Input Port 2 RX22- IN Differential Data Input Pair2 for HDMI Input Port 2 RX22+ IN Differential Data Input Pair2 for HDMI Input Port 2 EXT_RES IN External Termination Resistor for all HDMI Input Ports. A resistor should tie this pin to AVDD33. 510 is recommended. Table 2-2 HDMI Output Ports Name In/Out Description TXC- OUT Differential Clock Output Pair for HDMI Output Port 0 TXC+ OUT Differential Clock Output Pair for HDMI Output Port 0 TX0- OUT Differential Data Output Pair0 for HDMI Output Port 0 TX0+ OUT Differential Data Output Pair0 for HDMI Output Port 0 TX1- OUT Differential Data Output Pair1 for HDMI Output Port 0 TX1+ OUT Differential Data Output Pair1 for HDMI Output Port 0 TX2- OUT Differential Data Output Pair2 for HDMI Output Port 0 TX2+ OUT Differential Data Output Pair2 for HDMI Output Port 0 Data Sheet — EP92A7E / EP91A7E V0.4 Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED 9 COMR Analog Common ground for pull-down resistors for HDMI Output Port Table 2-3 eARC RX pins Name In/Out Description eARC+/- IN/OUT AC coupled eARC differential input/output Table 2-4 Audio Inputs/Outputs Name In/Out Description MCLK OUT System Clock output for audio DAC (128/256/512 * F Sampling_Clock IIS_SCK OUT IIS SCK output for IIS audio port. Sampling clock output for DSD IIS_WS OUT IIS WS output for all IIS audio ports DSD audio output port 2 (Right Channel) IIS_SD0 OUT IIS SD output for audio port 0 or HBR audio output DSD audio output port 0 (Left Channel) IIS_SD1 OUT IIS SD output for audio port 1 or HBR audio output DSD audio output port 0 (Right Channel) IIS_SD2 OUT IIS SD output for audio port 2 or HBR audio output DSD audio output port 1 (Left Channel) IIS_SD3 OUT IIS SD output for audio port 3 or HBR audio output DSD audio output port 1 (Right Channel) SPDIF OUT SPDIF output DSD audio output port 2 (Left Channel) A_MUTE OUT Audio Mute Output IIS_SCK_IN IN IIS SCK input for regenerated IIS audio IIS_WS_IN IN IIS WS input for regenerated IIS audio IIS_SD_IN IN IIS SD input for regenerated IIS audio Table 2-5 DDC/IIC/H5V*/HPD* Name In/Out Description SCL23 IN SCL signal for slave IIC port SDA23 IO SDA signal for slave IIC port SCL10 IN IIC SCL signal for HDMI RX DDC Port 0 SDA10 IO IIC SDA signal for HDMI RX DDC Port 0 SCL11 IN IIC SCL signal for HDMI RX DDC Port 1 SDA11 IO IIC SDA signal for HDMI RX DDC Port 1 SCL12 IN IIC SCL signal for HDMI RX DDC Port 2 SDA12 IO IIC SDA signal for HDMI RX DDC Port 2 H5V_0 IO Detect 5V input from HDMI RX Port 0 (3.3V tolerance) This pin can be configured as general purpose I/O with programmable open-drain property. H5V_1 IO Detect 5V input from HDMI RX Port 1 (3.3V tolerance) This pin can be configured as general purpose I/O with programmable open-drain property. Table 2-2 HDMI Output Ports Name In/Out Description Data Sheet — EP92A7E / EP91A7E V0.4 Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED 10 H5V_2 IO Detect 5V input from HDMI RX Port 2 (3.3V tolerance) This pin can be configured as general purpose I/O with programmable open-drain property. HPD_0 IO HPD Control Signal for HDMI RX Port 0. This pin can be configured as general purpose I/O with programmable open-drain property. HPD_1 IO HPD Control Signal for HDMI RX Port 1. This pin can be configured as general purpose I/O with programmable open-drain property. HPD_2 IO HPD Control Signal for HDMI RX Port 2. This pin can be configured as general purpose I/O with programmable open-drain property. Table 2-6 GPIO Name In/Out Description GPIO0 I/O Multi-Purpose I/O Port 0: 1. SPDIF Audio Input for “Audio Replacement” Logic (ATX_SRC == 2’b00) 2. SPDIF Audio Input for “SPDIF to IIS Conversion” Logic (SPIIS_SRC == 3’b100) 3. SPDIF Audio Input for “SPDIF Bypass” Logic (BYP_EN == 1’b1) & (BYP_IN == 2’b00) 4. SPDIF Audio Input for “Alternative SPDIF” Logic (ALT_SRC == 2’b11) & (BYP_IN == 2’b00) 5. SPDIF Audio Output for “Alternative SPDIF” Logic (ALT_EN = 1’b1) & (ALT_OUT == 2’b00) 6. test signal output 7. General Purpose I/O Port 0 with programmable open-drain property. GPIO1 I/O Multi-Purpose I/O Port 1: 1. SD1 Audio Input for “Audio Replacement” Logic (ATX_SRC == 2’b00) 2. SPDIF Audio Input for “SPDIF to IIS Conversion” Logic (SPIIS_SRC == 3’b101) 3. SPDIF Audio Input for “SPDIF Bypass” Logic (BYP_EN == 1’b1) & (BYP_IN == 2’b01) 4. SPDIF Audio Input for “Alternative SPDIF” Logic (ALT_SRC == 2’b11) & (BYP_IN == 2’b01) 5. SPDIF Audio Output for “Alternative SPDIF” Logic (ALT_EN = 1’b1) & (ALT_OUT == 2’b01) 6. test signal output 7. General Purpose I/O Port 1 with programmable open-drain property. GPIO2 I/O Multi-Purpose I/O Port 2: 1. SD2 Audio Input for “Audio Replacement” Logic (ATX_SRC == 2’b00) 2. SPDIF Audio Input for “SPDIF to IIS Conversion” Logic (SPIIS_SRC == 3’b110) 3. SPDIF Audio Input for “SPDIF Bypass” Logic (BYP_EN == 1’b1) & (BYP_IN == 2’b10) 4. SPDIF Audio Input for “Alternative SPDIF” Logic (ALT_SRC == 2’b11) & (BYP_IN == 2’b10) 5. SPDIF Audio Output for “Alternative SPDIF” Logic (ALT_EN = 1’b1) & (ALT_OUT == 2’b10) 6. test signal output 7. General Purpose I/O Port 2 with programmable open-drain property. GPIO3 I/O Multi-Purpose I/O Port 2: 1. SD3 Audio Input for “Audio Replacement” Logic (ATX_SRC == 2’b00) 2. SPDIF Audio Input for “SPDIF to IIS Conversion” Logic (SPIIS_SRC == 3’b111) 3. SPDIF Audio Input for “SPDIF Bypass” Logic (BYP_EN == 1’b1) & (BYP_IN == 2’b11) 4. SPDIF Audio Input for “Alternative SPDIF” Logic (ALT_SRC == 2’b11) & (BYP_IN == 2’b11) 5. SPDIF Audio Output for “Alternative SPDIF” Logic (ALT_EN = 1’b1) & (ALT_OUT == 2’b11) 6. test signal output 7. General Purpose I/O Port 3 with programmable open-drain property. Table 2-7 Misc. Name In/Out Description X_IN Analog External Crystal Input, 24 Mhz Table 2-5 DDC/IIC/H5V*/HPD* Name In/Out Description Data Sheet — EP92A7E / EP91A7E V0.4 Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED 11 Table 2-9 Power Pins Name In/Out Description RX_AVDD33 PWR HDMI Termination Power (3.3V) RX_PAVDD12 PWR HDMI RX PLL and Analog Power (refer to V RX 12) RX_AVDD12 PWR HDMI RX Analog Power (refer to V RX 12) TX_PVDD12 PWR HDMI TX PLL Analog Power (refer to V TX 12) TX_PVSS GND HDMI TX PLL Analog Ground TX_AVDD12 PWR HDMI TX Analog Power (refer to V TX 12) TX_AVSS GND HDMI TX Analog Ground RX_VDD PWR RX Logic Power (refer to V DD 12) RX_VSS GND RX Logic Ground VDD12 PWR Internal Logic Power (refer to V DD 12) VSS GND Logic Ground VDD_PLL PWR Audio PLL Power (1.2V) VSS_PLL GND Audio PLL Ground VDDE PWR I/O Power (3.3V) MCU_VDDE PWR MCU Power (3.3V) MCU_VSS GND MCU Ground EXT_RSTb IN External Reset input (Active Low) with internal weak pull-up. tOUT0 OUT test output 0. Connecting a pull-up (logic 1) or pull-down (logic 0) resistor at this pin defines bit 4 of the slave IIC Address tOUT1 OUT test output 1. Connecting a pull-up (logic 1) or pull-down (logic 0) resistor at this pin defines bit 5 of the slave IIC Address tOUT2 OUT test output 2 XFC_A Analog For connecting a capacitor to ground for on-chip PLL Table 2-8 HDMI Controller Pins Name In/Out Description MCU_RSTb IN External Reset (active low) with on-chip pull-up. When this pin is asserted low, the HDMI controller is totally reset. MCU_OP0 IN HDMI Controller operation mode 0: Normal mode 1: ICP (In Circuit Flash Programming) mode MCU_XI IN External Crystal Input, 24 MHz MCU_XO OUT External Crystal Output, 24 MHz P0# IN/OUT GPIO port 0 with programmable Open Drain capability. P1# IN/OUT GPIO port 0 or External Interrupt inputs. P2# IN/OUT GPIO port 2 with programmable Open Drain capability. P3# IN/OUT Open Drain I/O port 3, shared with IIC Port P4# IN/OUT GPIO port 4 or External Interrupt inputs P7# IN/OUT Open Drain I/O port 7, shared with Serial Port Table 2-7 Misc. Name In/Out Description Data Sheet — EP92A7E / EP91A7E V0.4 Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED 12 2.4 Electrical Characteristics Absolute Maximum Conditions Symbol Parameter Min Typ Max Units Vcc33 1 1. Permanent device damage may occur if absolute maximum conditions are exceeded. 3.3V Supply Voltage -0.3 4.0 V Vcc12 1 1.2V Supply Voltage -0.3 1.5 V V I Input Voltage SCL_1# SDA_1# -0.3 5.5 V Others -0.3 V cc33 + 0.3 V V O2 2. Functional operation should be restricted to the conditions described under Normal Operating Conditions. Output Voltage All -0.3 V cc33 + 0.3 V T STG Storage Temperature -40 125 C JA Thermal Resistance (Junction to Ambient) 3 3. Analyzed by FEM (Finite Element Modeling) method with chip mounted on 4-layers PCB. QFN-128 24.8 C/W QFN-88 TBD JC Thermal Resistance (Junction to Case) 3 QFN-128 6.24 C/W QFN-88 TBD JT Thermal Resistance (Junction to Top) 3 QFN-128 0.02 C/W QFN-88 TBD Normal Operating Conditions Symbol Parameter Min Typ Max Units V CC 33 3.3V Supply Voltage 3.14 3.3 3.6 V V TX 12 TX_AVDD12 / TX_PVDD12 Supply Voltage 1 1.15 1.2 1.32 V V RX 12 RX_PAVDD12 / RX_AVDD12 / VDD_PLL Supply Voltage 1 1.18 1.25 1.32 V V DD 12 VDD12 / RX_VDD Supply Voltage 1 1.18 1.25 1.32 V V CC N Supply Voltage Noise 50 mV p-p T A Ambient Temperature (with power applied) 0 25 70 C T J Junction Temperature 125 C F X_IN External Crystal Frequency 24 MHz -500 +500 ppm NOTES : Data Sheet — EP92A7E / EP91A7E V0.4 Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED 13 DC Digital I/O Specifications (under normal operating conditions unless otherwise specified) Symbol Parameter Conditions Min Typ Max Units V IH High-level Input Voltage 2.0 V V IL Low-level Input Voltage 0.8 V V OH High-level Output Voltage 2.4 V V OL Low-level Output Voltage 0.4 V I OL Output Leakage Current High Impedance -10 10 uA DC Analogue Specifications ( under normal operating conditions unless otherwise specified ) NOTES : 1. In order to get best performance, it is recommended to assign 3 different DC-DC regulators for the V TX 12, V RX 12, and V DD 12 power domain. It is also important to make sure that the voltage at IC pin side is typical value. The voltage at DC-DC output side could be higher to compensate the power trace lose. Symbol Parameter Conditions Min Typ Max Units V OD Differential Voltage Single ended peak to peak amplitude R LOAD = 50 ohm 510 550 590 mV V DOH Differential High-level Output Voltage 1 AVCC 1 V I DOS Differential Output Short Circuit Current V OUT = 0V; TX Termination is Off 5 uA I PD Power-Down Current 2 25 C Ambient V CC 33 2 mA V DD 12 <10 mA V RX 12 <2 mA V TX 12 <2 mA Data Sheet — EP92A7E / EP91A7E V0.4 Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED 14 Receiver AC Specifications ( under normal operating conditions unless otherwise specified ) Symbol Parameter Conditions Min Typ Max Units T DPS Intra-Pair (+ to -) Differential Input Skew 1 1. Guaranteed by design. 0.8 T bit T CCS Channel to Channel Differential Input Skew 1 1.0 Tpixel T IJIT Differential Input Clock Jitter Tolerance 2 2. Jitter defines as per HDMI Specification 2.0 - 6.1.1.5. at TP2_EQ 0.3 T bit Differential Input Data Jitter Tolerance 2 at TP2_EQ 0.6 T bit F CIP TMDS Data Clock Frequency 25 600 MHz I CCD Supply Current (25 C Ambient, HDCP 2.2 active, R EXT_RES = 510 ohm) 4K2K 60Hz 8-bit (6G, 1 in, 1 out) V CC 33 139 167 mA V DD 12 603 724 mA V RX 12 435 479 mA V TX 12 238 262 mA 4K2K 24Hz 8-bit (3G, 1 in, 1 out) V CC 33 114 137 mA V DD 12 315 378 mA V RX 12 361 397 mA V TX 12 204 224 mA 1080p 60Hz 8-bit (1.5G, 1 in, 1 out) V CC 33 112 134 mA V DD 12 174 209 mA V RX 12 348 383 mA V TX 12 183 201 mA 720p 60Hz 8-bit (75M, 1 in, 1 out) V CC 33 108 130 mA V DD 12 108 130 mA V RX 12 302 332 mA V TX 12 174 191 mA 480p 60Hz 8-bit (27M, 1 in, 1 out) V CC 33 108 130 mA V DD 12 62 74 mA V RX 12 303 333 mA V TX 12 160 176 mA NOTES : 1. AVCC is the 3.3V termination from the Sink Device. NOTES : Data Sheet — EP92A7E / EP91A7E V0.4 Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED 15 Transmitter AC Specifications ( under normal operating conditions unless otherwise specified ) Symbol Parameter Conditions Min Typ Max Units S LHT Differential Swing Low-to-High Transition Time C LOAD = 5pF, R LOAD = 50 ohm 80 100 120 ps S HLT Differential Swing High-to-Low Transition Time C LOAD = 5pF, R LOAD = 50 ohm 80 100 120 ps T OJIT Differential Output Clock Jitter at TP2_EQ 0.3 T bit Differential Output Data Jitter at TP2_EQ 0.6 T bit I2S Audio AC Specifications ( under normal operating conditions unless otherwise specified ) Symbol Parameter Conditions Min Typ Max Units T sck SCK Clock Period C L = 10pF 1 T sck T sck_d SCK Clock Duty Cycle C L = 10pF 40% 60% T sck T sck_h SCK Clock High Time C L = 10pF 40% 60% T sck T sck_l SCK Clock LOW Time C L = 10pF 40% 60% T sck T iis_s SCK to SD and WS (Setup Time) C L = 10pF 40% - T sck T iis_h SCK to SD and WS (Hold Time) C L = 10pF 40% - T sck SPDIF Audio AC Specifications ( under normal operating conditions unless otherwise specified ) Symbol Parameter Conditions Min Typ Max Units T spdif SPDIF Cycle Time C L = 10pF 1 UI T spdif_d SPDIF Duty Cycle C L = 10pF 90% 110% UI Data Sheet — EP92A7E / EP91A7E V0.4 Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED 16 2.5 Standard Audio Output Format Standard audio is output from IIS/SPDIF pins as shown in the following figure: Figure 2-4 PCM Audio Output Format from IIS IIS_SD0 IIS_WS (WS_POL = 0) MSB (1st FL sample 16/24 bits) IIS_SD1 MSB (1st LEF sample 16/24 bits) IIS_SD2 MSB (1st RL sample 16/24 bits) IIS_SD3 MSB (1st RLC sample 16/24 bits) LSB (padding 0) LSB (padding 0) LSB (padding 0) LSB (padding 0) 16 / 32 Clock MSB (1st FR sample 16/24 bits) MSB (1st FC sample 16/24 bits) MSB (1st RR sample 16/24 bits) MSB (1st RRC sample 16/24 bits) LSB (padding 0) LSB (padding 0) LSB (padding 0) LSB (padding 0) The IIS output can suppor the PCM 2 Channel ~ 8 Channel. The channel number and channel mapping information will be extrated in the HDMI Audio Infoframe. Figure 2-5 Compressed Audio Output Format from IIS IIS_SD0 IIS_WS (WS_POL = 0) MSB (1st Data 16/24 bits) LSB (padding 0) 16 / 32 Clock MSB (2nd Data 16/24 bits) LSB (padding 0) ICE 60958 Sub-frame 16 bit 24 bit case The IIS / SPDIF output also support many audio formats which can be packed in the ICE 60958 Sub-frame. For example, PCM 2 Channel, Dolby Digital (EX, Plus...), DTS (ES, Neo:6...). For the compressed audio, please refer to stream header for audio information. Data Sheet — EP92A7E / EP91A7E V0.4 Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED 17 2.6 HBR Audio Output Format HBR (High Bit Rate) audio is output from IIS pins as shown in the following figure: Figure 2-6 HBR Audio Output Format IIS_SD0 IIS_WS (WS_POL = 0) 1st 16 bits 2nd16 bits 9th16 bits 10th 16 bits IIS_SD1 3rd 16 bits 4th16 bits 11th 16 bits 12th16 bits IIS_SD2 5th16 bits 6th 16 bits 13th 16 bits 14th16 bits IIS_SD3 7th 16 bits 8th 16 bits 15th 16 bits 16th16 bits The HBR audio output format can carry the HD Audio like Dolby TrueHD, Dolby Atmos, DTS-HD MA, or DTS:X. Data Sheet — EP92A7E / EP91A7E V0.4 Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED 18 2.7 Standard Audio Input Format Standard audio is input from IIS pins as shown in the following figure: Figure 2-7 PCM Audio Input Format from IIS IIS_SD0 IIS_WS (WS_IN_POL = 0) MSB (1st FL sample 16/24 bits) LSB (padding 0) 16 / 32 Clock MSB (1st FR sample 16/24 bits) LSB (padding 0) Figure 2-8 Compressed Audio Input Format from IIS IIS_SD0 IIS_WS (WS_IN_POL = 0) MSB (1st Data 16/24 bits) LSB (padding 0) 16 / 32 Clock MSB (2nd Data 16/24 bits) LSB (padding 0) ICE 60958 Sub-frame 16 bit 24 bit case The IIS input support many audio formats which can be packed in the ICE 60958 Sub-frame. For example, PCM 2 Channel, Dolby Digital (EX, Plus...), DTS (ES, Neo:6...). User must fill in the ADO Infoframe and Channel Status information to the chip registers. Data Sheet — EP92A7E / EP91A7E V0.4 Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED 19 2.8 Power Sequence Following figure shows the recommended power sequence: Figure 2-9 Power Sequence 3.3V Power 10ms typical MCU_RSTb (reset) Reset Pulse should be asserted after the supplied power is stable. 1.2V Power Don’t care the 1.2V and 3.3V sequence Data Sheet — EP92A7E / EP91A7E V0.4 Explore Confidential Proprietary NON-DISCLOSURE AGREEMENT REQUIRED 20