i Preface Welcome to the Volume 4 Number 2 of the International Journal of Design, Analysis and Tools for Integrated Circuits and Systems (IJDATICS). This issue comprises of i) enhanced and extended version of research papers from the International DATICS Workshops in 2012 and 2013, and ii) ordinary manuscript submissions in 2012 and 2013. DATICS Workshops were created by a network of researchers and engineers both from academia and industry in the areas of i) Design, Analysis and Tools for Integrated Circuits and Systems and ii) Communication, Computer Science, Software Engineering and Information Technology. The main target of DATICS Workshops is to bring together software/hardware engineering researchers, computer scientists, practitioners and people from industry to exchange theories, ideas, techniques and experiences. This IJDATICS issue presents three high quality academic papers. This mix provides a well- rounded snapshot of current research in the field and provides a springboard for driving future work and discussion. The three papers presented in this volume are summarized as follows: • Distributed Control: Bukowiec investigates how distributed control systems can be implemented on FPGAs via Petri Nets. • Reconfigurable Logic: Tkacz and Adamski apply Gentzen Reasoning to implement structured configurable controllers on FPGAs. • Embedded Systems: Knirsch, Schnarz and Wietzke present a novel approach to arbitrate shared resources in partitioned multicore systems via library interposition. • Digital Circuits: Kim proposes two methodologies for predicting transistor aging in nanometer digital circuits as well as controlling periodic jitter leakage. We are beholden to all of the authors for their contributions to the Volume 4 Number 2 of IJDATICS. We would also like to thank the IJDATICS editorial team. Editors: Ka Lok Man , Xi’an Jiaotong-Liverpool University, China, and Baltic Institute of Advanced Technology (BPTI), Lithuania Chi-Un Lei , University of Hong Kong, Hong Kong Amir-Mohammad Rahmani , University of Turku, Finland Nan Zhang , Xi’an Jiaotong-Liverpool University, China David Afolabi , Xi’an Jiaotong-Liverpool University, China ii Table of Contents Vol. 4, No. 2, December 2013 Preface ................................................................................................. i Table of Contents ................................................................................... ii 1. Distributed Control Systems Design as Petri Nets for FPGAs ...... Arkadiusz Bukowiec 1 2. Design of Structured Configurable Controllers Using Gentzen Reasoning ................................................................. Jacek Tkacz and Marian Adamski 10 3. SHARB: Shared Resource Arbitration in Partitioned Multicore Systems via Library Interposition ...................... A ndreas Knirsch, Pierre Schnarz, and Joachim Wietzke 18 4. Transistor Aging Prediction in Nanometer Digital Circuits ................ Kyung Ki Kim 28 5. A New Method for Periodic Jitter Leakage Control .......................... Kyung Ki Kim 32 INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR INTEGRATED CIRCUITS AND SYSTEMS, VOL. 4, NO. 2, DECEMBER 2013 1 Distributed Control Systems Design as Petri Nets for FPGAs Arkadiusz Bukowiec Abstract —The paper describes a new method for the imple- mentation of the application specific distributed control systems, constructed using the FPGA devices. The initial steps of the proposed control algorithm rely on the notion of a Petri net, which is an easy way to describe parallel processes. The sub- sequent steps of the algorithm consist in the decomposition of a given Petri net – with the use of a coloring algorithm – into a set of state machine type subnets. In the results each subnet represents one parallel process. These subnets are then implemented independently in different FPGA devices. To ensure proper communication between all subnets, the entire control system uses a globally asynchronous locally synchronous (GALS) architecture with each subnet synchronized by the local clock signal. Global communication between components is buffer- based and uses additional signals, generated in a given subnet and distributed to the remaining ones. Index Terms —Boolean algebra; Decomposition; Field pro- grammable gate arrays; Logic synthesis; Sequential circuits. I. I NTRODUCTION P ETRI nets (PNs) [1], [2] are one of the most popular concepts used in formal design and synthesis of the application specific concurrent logic controllers [3], [4]. Such graphical representation of algorithm is very comfortable. It gives easy way for representation of concurrent processes and additionally there could be applied mathematical algorithms for formal analysis and verification of the designed model [5], [6], [7]. The digital design of the controllers is very often implemented using integrated circuit as field programmable gate arrays (FPGAs) [8], [9], [10], [11]. The most typical implementation of Petri nets in the FPGA devices uses the one-hot local state encoding method, where each place is represented by a single flip-flop [3]. This approach requires hardware implementation of a large number of logic functions and flip-flops included in logic cells. Moreover, there is no possibility to distribute such system. In this paper there is proposed a method for the implementa- tion of a Petri net representing a distributed application specific logic controller [12]. To allow its subsequent decomposition, the Petri net is initially colored [13], with places that have the same color forming a one-state machine (SM) module. In the process, we use a new subnets extracting procedure that supplements the known methods of Petri net SM coloring [3], [14], [15], [16], [17]. As a result, each SM module can be implemented in a separate FPGA device. To ensure proper communication a globally asynchronous locally synchronous A. Bukowiec is with Institute of Computer Engineering and Electronics, University of Zielona G ́ ora, ul. Podg ́ orna 50, 65-246 Zielona G ́ ora, Poland (Email: a.bukowiec@iie.uz.zgora.pl). The research was financed from budget resources intended for science in 2010–2013 as an own research project No. N N516 513939. (GALS) architecture is used in the entire system. Each of the SM components is synchronized by local clock signal. For the entire system to use an asynchronous mode of synchronization, the additional communication signals are required. In such solution the places of each SM subnet can be encoded with a minimal-length binary vector. This encoding allows to decompose the digital circuit of SM subnet into double-level structure with separate circuits for firing transi- tions and generating microoperations [18], [19]. In this case, the realization of a microoperation decoder is possible with the use of an FPGA embedded memory blocks [20]. This is done in a way that leads to a balanced usage of all the logical resources of the FPGA device. II. P ETRI NET A simple Petri net [1], [2] is defined as a triple P N = ( P, T, F ) , (1) where: P is a finite non-empty set of places, P = { p 1 , . . . , p M } T is a finite non-empty set of transitions, T = { t 1 , . . . , t S } F is a set of arcs (describing flow relations) from places to transitions and from transitions to places: F ⊆ ( P × T ) ∪ ( T × P ) , P ∩ T = ∅ The sets of input and output transitions of a place p m ∈ P are defined respectively as follows: • p m = { t s ∈ T : ( t s , p m ) ∈ F } , p m • = { t s ∈ T : ( p m , t s ) ∈ F } Sets of input and output places of a transition t s ∈ T are defined respectively as follows: • t s = { p m ∈ P : ( p m , t s ) ∈ F } , t s • = { p m ∈ P : ( t s , p m ) ∈ F } A marking of a Petri net is defined as a function: M : P → N Intuitively, given a place p m the function M ( p m ) returns the number of tokens in p m . A place or a set of places is marked when it contains a token. A transition t s can be fired if all its input places are marked. Firing a transition removes tokens from its input places and puts one token in each output place. When the initial marking M 0 is additionally specified, the Petri net can be represented as a tuple: P N = ( P, T, F, M 0 ) (2) INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR INTEGRATED CIRCUITS AND SYSTEMS, VOL. 4, NO. 2, DECEMBER 2013 2 A. Colored Petri Net A Petri net can be enhanced by assigning colors to places and transitions [1], [3], [13]. In a state machine (SM) colored Petri net the colors aid in an intuitive as well as formal consistency check for all the sequential processes covering the net. Each color recognizes one SM subnet. The rules for the Petri net coloring are as follows [14], [15]: • each place and transition must have at least one color assigned, • if the place is assigned with a given color, each of its input and output transitions must be assigned with the same color, • the input places of each transition must be assigned with different colors, • the output places of each transition must be assigned with different colors, • the input and output places of a given transition must share the same set of colors, • the initially marked places cannot share the same set of colors, • the number of different colors which are shared by the initially marked places must be equal to the total number of colors. B. Interpreted Petri Net A Petri net enhanced with an additional feature for infor- mation exchange is called an interpreted Petri net [2]. If an interpreted Petri net is also enhanced with colors, it is often called a colored interpreted Petri net. This exchange is made by use of binary signals. Interpreted Petri nets are used as models of concurrent logic controllers. The Boolean variables occurring in the interpreted Petri net can be divided into three sets: X is the set of input variables, X = { x 1 , . . . , x L } , Y is the set of output variables, Y = { y 1 , . . . , y N } , Z is the set of internal communication variables (most cases not used, with Z = ∅ ). An interpreted Petri net has a guard condition φ s associated with every transition t s . The guard condition φ s is defined to be a Boolean function of a subset of variables from the sets X and Z . In a special case, the condition φ s can be defined as 1 (always true). A transition t s can be fired if all its input places are marked and the current value of the corresponding Boolean function φ s is equal to 1 . The conjunction ψ m associated with a place p m is an elementary conjunction of positive literals formed from output variables from the set Y . If the place p m is marked, the output variables from corresponding conjunction ψ m are set and other variables are reset. C. Macroplace Macroplaces correspond to a subnet or a part of a subnet assigned with a particular color and enhance a Petri net with a hierarchy [2], [5]. In this article we make frequent use of the so-called mono-active macroplaces, that is macroplaces consisting of sequential places, with one input and one output [21]. We note that the macroplaces theory is well developed Y X Y 1 Y 2 Y I Z Y Z 1 Y Z 2 Y Z I X 1 X 2 X I X Z 1 X Z 2 X ZI SMN 1 X X Z Y Y Z SMN 2 SMN I X X Z Y Y Z X X Z Y Y Z CLK CLK CLK RES RES RES RES Fig. 1. Architecture of distributed control system CC RG D Y Q Y 1 Y Z Q Y Y Z Q D D Q X X Z X X Z CLK RES RES LOCAL Fig. 2. Architecture of single SM module and includes much more complex extensions of the basic definition, including the notion of a multi-active macroplace [22]. III. S YSTEM A RCHITECTURE The use of the globally asynchronous locally synchronous (GALS) architecture for a distributed control system seems to be preferable. Since each color recognizes one sequential process, the decomposition of a colored Petri net into SM subnets is based on the assigned colors. As a result, we obtain I SM subnets, where I is the number of the Petri net colors. (The following section describes the process of decomposition in more detail.) In the next step each SM subnet is implemented as a double-level sequential circuit (SMN i ) with local clock signals (Fig. 1) [23], [19]. The communication between components is made asynchronous in a buffer-based mode. We note that there exists a multitude of other commu- nication methods, such as Handshake, FIFO-, Controller-, or Lookup-based [24]. However, in the considered architecture there is no real data exchange, since only the triggers are sent to other components. Note that FIFO-, Controller-, and Lookup-based communication types are not adequate here, since they are designed for systems where large amount of data is exchanged. Only the Handshake method could be applicable, but it requires a modification of the SM subnets control algorithm. Hence we suggest the use of dedicated buffers INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR INTEGRATED CIRCUITS AND SYSTEMS, VOL. 4, NO. 2, DECEMBER 2013 3 to send all the triggers. Each SMN i circuit (Fig. 2) consists of a first-level combinational circuit CC i , a memory register RG i , and a second-level output decoder Y i . The combinational circuit CC i is responsible for the generation of the excitation functions for the memory register. It implements transition functions, and it can be described as follows: D i = D i ( X i , X i Z , Q i ) , (3) where: X i is a subset of the set of the Petri net input variables ( X i ⊆ X ), X i Z is a subset of the set of the additional internal variables used for synchronization ( X i Z ⊆ Z ), Q i is the set of variables used to store a code of the currently marked place in a given SM subnet. Recall that a given SM subnet recognizes one sequential process at a time, hence only once place can be marked in a given moment. The memory register RG i consists of the D-type flip-flops. It is used to store the code of the currently marked place. The number of required flip-flops depends on the number of places as well as on the method of encoding. (We formally define this number in the following section.) The decoder Y i is responsible for the generation of the Petri net output signals Y i that are under control of a given SM subnet and additional internal variables used for synchronization Y i Z These can be defined as follows: Y i = Y i ( Q i ) , Y i Z = Y i Z ( Q i ) (4) Connections between all the SMN i circuits have to be created (Fig. 1). In the above equation, Z denotes a bus implementing the buffer-based communication method that can be defined as follows: Z = I ⋃ i =1 Y i Z (5) The bus Y is an output of the controller and it can be defined as a sum of outputs for all SMN i circuits: Y = I ⋃ i =1 Y i (6) The bus X is an input of the controller. IV. S YNTHESIS M ETHOD The main idea of the proposed synthesis method is based on the decomposition of a Petri net into SM subnets and the minimal encoding of places. The places are encoded separately in each subnet using the minimal (in bits) length vector. The decomposition is based on the colors assigned to the places of a given colored Petri net. The Output variables assigned to places are decoded in the second-level circuit. This is implemented with the embedded memory blocks, which allows a balanced usage of the modern FPGA devices resources [18]. The starting point of the synthesis method is a colored interpreted Petri net. We note that there are several Petri net coloring algorithms and we do not intend to discuss them here, for more information see [16], [17]. Since the coloring algorithms do not care about the output signals, we need to make sure that places, which elementary conjunctions include the same output signal, have at least one color in common. This is required to ensure the proper functioning of the control system. It also prevents the occurrence of the single resource access conflict between concurrent processes. All this can be viewed as an extension of a coloring algorithm. Note that colors should be also assigned to elementary conjunctions of places and that each elementary conjunction should be assigned the same color as its place. Hence the rules for the Petri net coloring should be extended with one condition: • Elementary conjunctions containing a common output signal must share at least one of the colors. The entire synthesis process consists in the following steps: 1) Decomposition into SM subnets . The purpose of this step is to obtain subnets from the initial colored Petri net, assuming that the Petri net is colored with I different colors, where i = 1 , . . . , I is a number of particular color. The process of decomposition begins from the first color, denoted C 1 . All the places colored with this color form the first SM subnet, denoted SMN 1 . All the subsequent subnets are created in a similar way, except that all the sequences of places, which have already been placed in one of the previously created subnets (assigned with the color number lower than currently evaluated), are replaced by a macroplace and dmp m ∈ DM P i – the macroplace doubler – is placed in a given SM subnet. Note that, as a result, there could be several doublers obtained. Doublers occurring sequentially can be replaced by a single doubler. 2) Constructing the set of synchronizing variables . The goal here is to construct the set Z , consisting of variables used for the synchronization of the SMN i subnets. These variables are assigned to places and transitions. There is required to analyze each transition. If a transition t s belongs to more that one SMN i subnet, then each elementary conjunction ψ m assigned to a transition input place p m ∈ • t s (note that in the case of a SM subnet | • t s | = 1 ) should be replaced by a new elementary conjunction ψ ∗ m = ψ m ∧ y p m Z , where y p m Z is the new synchronizing signal and y p m Z ∈ Y i Z . We are then required to replace the guard condition φ s assigned to the transition t s in each subnet SMN i by a new guard condition φ i s = φ s ∧ ( ∧ x p m Z ) – where ∧ x p m Z is a disjunction of signals y p m Z generated by the remaining subnets – and connected to the appropriate inputs x p m Z ∈ X i Z of the considered subnet SMN i 3) Places encoding . The aim of this step is to assign binary code K ( p m ) to each place p m in each subnet SMN i . All the subnets have to be analyzed separately. The encoding should be done using the lowest possible number of bits. This allows an efficient use of the FPGA embedded memory blocks for the purposes of the decoder Y i . In such case the number of bits used is R i = d log 2 | P i |e , (7) INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR INTEGRATED CIRCUITS AND SYSTEMS, VOL. 4, NO. 2, DECEMBER 2013 4 where P i ⊆ ( P ∪ DM P i ) is a set of places of a given subnet SMN i . To store this code we use Q i = { q 0 , . . . , q R i − 1 } variables. The place belonging to the initial marking M 0 should be assigned the code equal to 0 . If a given subnet does not include any place from the initial marking M 0 , the code equal to 0 should be assigned to the place dmp m that replaced macroplace with such place. The subsequent places should receive subsequent Gray codes. We note that it is the most ef- fective encoding for this type of circular state machines [25]. 4) Forming conjunctions . The purpose of this step is to form the conjunctions describing each place p m , each transition t s and any given additional hold conditions. These conjunctions aid the construction of the logical formulas related to the system (3), described in the next step. For each subnet SMN i the conjunctions are formed separately. Given a place p m the conjunction describing p m is formed with literals from the variables q r ∈ Q i , using the code of the place p m (denoted K ( p m ) ). If a variable q r equals 0 – as encoded by K ( p m ) – then the negative literal ̄ q r is used. If q r equals 1 , then the positive literal q r is used: p m = R − 1 ∧ r =0 q l r , (8) where l ∈ { 0 , 1 } , q 0 r = ̄ q r and q 1 r = q r . The conjunction related to a transition t s is formed using the conjunction describing its input place p m ∈ • t s and its guard condition: t s = p m ∧ φ s (9) Additional hold conditions are required to ensure that the code for the current place is not lost, when it will be required for more that one clock cycle. The formula describing the hold conditions of a place p m is the conjunction of p m and the negated disjunction of conjunctions describing its output transitions: hp m = ∨ p m • ∧ p m (10) 5) Building formulas . The goal of this step is to build up the formulas describing the system (3), which is implemented using the combinational circuit CC i . These formulas are formed using a D-type flip-flop and are built from the conjunctions of transition conditions and the conjunctions of the hold conditions for places. If a variable q r is equal to 1 (given the code K ( p m ) for the place p m ) then the respective formula, denoted D r , is a disjunction of conjunctions of the input transitions and the hold conditions for the place p m : D r = M ∨ m =1 ( ∨ • p m ∨ hp m ∧ K ( p m )[ r ]) (11) 6) Creating decoder memory blocks . Since the system (4) has a regular structure, the decoders Y i can be imple- mented with the use of the embedded memory blocks. This allows a balanced usage of the FPGA device resources. The content of these memory blocks can be described by a truth table or by a set of formulas. How- ever, the truth table method is more suitable in this case. The variables q r ∈ Q i represent the address and output, whereas the variables y ∈ ( Y i ⊆ Y ) ∪ Y i Z represent the word stored under this address. The set Y i contains only the output variables controlled by the subnet SMN i In each row of the truth table only the variables y that form a part of the elementary conjunction ψ m related to the place p m (represented by the variables q r , given the code K ( p m ) ) are assigned the value 1 . Other variables receive the value 0 7) Forming logic circuit . The aim of this step is to cre- ate models of each subnet in a hardware description language (HDL) according to the schematic from the figure 2 and rules of its connections into control system according to the schematic from the figure 1. The module related to the combinational circuit CC i is described with the use of continues assignments. It describes the formulas created in the step 5. The memory RG i is described as an R i -bits, D-type, asynchronous reset signal register, which is triggered by a positive edge. The decoder Y i is described as a process using of the case statement. Note that since the embedded memory blocks are synchronous, the decoder has to be synchronous as well and such situation is not shown in the schematic. Note also that it should be triggered by a negative edge. The result is that the output values are ready and stable after a single clock signal period [20]. As a consequence of the behavior of the embedded memory blocks, the reset signal has to be synchronous. A HDL description of this module should include special synthesis directive appropriate for the use of embedded memory blocks. The syntax of this directive depends on a language, device and synthesis tool vendors. The description of the case statement is created based on the truth table created in the step 6. The top-level module of the subnet should describe connections between these three modules based on the schematic shown in figure 2. The local clock and reset signal have to be connected to the memory RG i and the decoder Y i . The connection of clock and reset signal to the decoder is not shown on the schematic because, in general case, the decoder can be asynchronous. Because there is applied simple buffer- based method of synchronization there is required that all local clock signals should have the same frequency. They cloud be shifted in phase and they could have different duty cycles. It means that there could be applied local clock generators for each subnet. Subnets created by following the above should be passed on separately to the third party synthesis & implementation tools. Each subnet is implemented in a separate FPGA device of distributed control system. Devices have to be connected by the external buses according to the schematic in the figure 1, where each block represents one device. INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR INTEGRATED CIRCUITS AND SYSTEMS, VOL. 4, NO. 2, DECEMBER 2013 5 t1 P1 [C1] YT1 XN1 [C1] [C2] [C1,C2] YV1 XF1 YT2 XN2 [C1,C2] YV1 XF1 [C2] [C3] YV2 XF2 [C3] [C2,C3] YM XF4 [C2,C3] YV3 XF3 t2 P4 t3 P5 t4 P6 P9 t9 P8 t6 P7 P10 t7 P11 t8 P2 [C1,C2] P3 t5 Fig. 3. Sample Petri net PN 1 V. A N E XAMPLE P ROCEDURE We use an example Petri net PN 1 (Fig. 3) to illustrate the method of Petri net synthesis described in the previous section. This Petri net describes control process of industrial mixer of aggregate content and water (Fig. 4) [8], [26]. Outputs of the controller are connected into valves of tanks ( yt 1 , yt 2 , yv 1 , yv 2 , yv 3 ) and engine of mixer ( ym ). Inputs gives information about state of tanks ( xf 3 ), scale ( xf 1 , xn 1 , xn 2 ), timer ( xf 4 ) and flow meter ( xf 2 ). The Petri net is colored using three colors C 1 , C 2 and C 3 , shown in the Figure as the lower-right label assigned to places. That sort of a colored Petri net can be considered an entry point in our synthesis method. Firstly, the Petri net has to be decomposed (step 1). The first subnet (Fig. 5a) consists of all the places colored by the color C 1 . The second one (Fig. 5b) has one doubler for the macroplace dmp 1 . This doubler is used instead of places p 4 , p 5 , and p 6 , since these places have been already used in the first subnet. A doubler for the macroplace dmp 2 in the third subnet (Fig. 5c) is also created, replacing p 10 , and p 11 . We note that the replication of the sequential places by a doubler of macroplace has also removed some transitions from received YT1 YT2 YV1 YV2 Aggregate feeder Content feeder Water feeder Scales Content mixer YV3 YM Mixer arm XN1 XN2 XF1 XF3 XF2 Timer XF4 Fig. 4. Industrial control process XF1*XZDMP1 t4 XN2 t3 XF1 t1 XN1 P6 YV1*YZP6 P5 YT2 P4 YV1 P2 YT1 t5 t2 P1 YZP2 XZP3 (a) SMN 1 XF3*XZDMP2 t7 XF4 XF1*XZP6 P11 YV3*YZP11 P10 YM P7 t6 t5 DMP1 t2 P3 t8 XZP2 YZP3 YZDMP1 YZP7 XZP8 (b) SMN 2 t9 XF2 XF3*XZP11 DMP2 YV2 P8 t6 t8 P9 YZP8 XZP7 YZDMP2 (c) SMN 3 Fig. 5. Subnets of the Petri net PN 1 SM subnet. Also output signals, from elementary conjunctions of these places, are now only under control of one SM subnet. Secondly, the synchronization variables are created (step 2). In our case, there are only four transitions belonging to more that one subnet: t 2 and t 5 belong to SMN 1 and SMN 2 and t 6 and t 8 belong to SMN 2 and SMN 3 . Additional signals, denoted y p 2 Z and y p 3 Z , were created for the transition t 2 . These signals were assigned to the conjunctions ψ ∗ 2 and ψ ∗ 3 respectively. These conjunctions relate to places p 2 and p 3 and are connected with the input signals denoted x p 2 Z and x p 3 Z , respectively. The input signals are added to the guard conditions denoted φ 2 2 and φ 1 2 (for the transition t 2 in SMN 2 and SMN 1 ) respectively. In a similar way the signals for three INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR INTEGRATED CIRCUITS AND SYSTEMS, VOL. 4, NO. 2, DECEMBER 2013 6 TABLE I E NCODING OF PLACES SMN 1 SMN 2 SMN 3 Place Code Place Code Place Code q 2 q 1 q 0 q 2 q 1 q 0 q 1 q 0 p 1 000 p 3 000 p 9 00 p 2 001 dmp 1 001 p 8 01 p 4 011 p 7 011 dmp 2 11 p 5 010 p 10 010 p 6 110 p 11 110 remaining transitions have to be created. The entire process is shown in Figure 5. The next step is to encode the places (step 3). In accordance with (7) we are required to use R 1 = 3 , R 2 = 3 , and R 3 = 2 bits, in order to encode all the places. A possible encoding of these places is shown in Table I. It is done separately for each subnet using variables from the corresponding Q i set. Since M 0 = { p 1 , p 3 , p 9 } , the places p 1 , p 3 , and p 9 all are assigned the codes equal to 0 After the encoding process is finished, we can start forming the conjunctions (step 4). The place conjunctions are formed on the basis of the place codes according to (8). The example conjunctions for subnet SMN 1 looks as follow: p 1 = q 2 ∧ q 1 ∧ q 0 , p 2 = q 2 ∧ q 1 ∧ q 0 , p 4 = q 2 ∧ q 1 ∧ q 0 , . . . , p 6 = q 2 ∧ q 1 ∧ q 0 The transition conjunction consists of transition input places and the transition guard condition according to (9). For the SMN 1 , we have: t 1 = p 1 ∧ xn 1 , t 2 = p 2 ∧ x p 3 Z , t 3 = p 4 ∧ xf 1 , . . . , t 5 = p 6 ∧ xf 1 ∧ x dmp 1 Z The hold conjunction for each place consists of a negation of the disjunction of all the conjunctions of the transitions of the output places and a place according to (10). For the SMN 1 , we have: hp 1 = t 1 ∧ p 1 , hp 2 = t 2 ∧ p 2 , hp 4 = t 3 ∧ p 4 , . . . , hp 6 = t 5 ∧ p 6 Now the formulas describing the combinational circuits can be formed (step 5). A formula has to be formed for every ‘ d e f i n e p1 ̃Q[ 2 ] & ̃Q[ 1 ] & ̃Q[ 0 ] ‘ d e f i n e p2 ̃Q[ 2 ] & ̃Q[ 1 ] & Q[ 0 ] ‘ d e f i n e p4 ̃Q[ 2 ] & Q[ 1 ] & Q[ 0 ] ‘ d e f i n e p5 ̃Q[ 2 ] & Q[ 1 ] & ̃Q[ 0 ] ‘ d e f i n e p6 Q[ 2 ] & ̃Q[ 1 ] & Q[ 0 ] ‘ d e f i n e t 1 ‘ p 1 & XN1 ‘ d e f i n e t 2 ‘ p 2 & XZP3 ‘ d e f i n e t 3 ‘ p 4 & XF1 ‘ d e f i n e t 4 ‘ p 5 & XN2 ‘ d e f i n e t 5 ‘ p 6 & XZDMP1 &X F1 ‘ d e f i n e hp1 ̃ ( ‘ t 1 ) & ‘ p 1 ‘ d e f i n e hp2 ̃ ( ‘ t 2 ) & ‘ p 2 ‘ d e f i n e hp4 ̃ ( ‘ t 3 ) & ‘ p 4 ‘ d e f i n e hp5 ̃ ( ‘ t 4 ) & ‘ p 5 ‘ d e f i n e hp6 ̃ ( ‘ t 5 ) & ‘ p 6 Fig. 6. Verilog description of conjunctions for SMN 1 ‘ i n c l u d e ” c o n j u n c t i o n s . vh ” module CC1 ( XN1 , XF1 , XN2 , XF2 , XZP3 , XZDMP1, Q, D) ; i n p u t XN1 , XF1 , XN2 , XF2 , XZP3 , XZDMP1 ; i n p u t [ 2 : 0 ] Q; o u t p u t [ 2 : 0 ] D; a s s i g n D[ 0 ] = ‘ t 1 | ‘ h p 2 | ‘ t 2 | ‘ h p 4 ; a s s i g n D[ 1 ] = ‘ t 2 | ‘ h p 4 | ‘ t 3 | ‘ h p 5 | ‘ t 4 | ‘ h p 6 ; a s s i g n D[ 2 ] = ‘ t 4 | ‘ h p 6 ; endmodule Fig. 7. Verilog description of combinational circuit CC of SMN 1 module RG1 (CLK, RES , Q, D) ; i n p u t CLK, RES ; i n p u t [ 2 : 0 ] D; o u t p u t [ 2 : 0 ] Q; r e g [ 2 : 0 ] Q; a l w a y s @( p o s e d g e CLK or p o s e d g e RES ) i f ( RES ) Q < = 3 ’ b0 ; e l s e Q < = D; endmodule Fig. 8. Verilog description of register RG of SMN 1 variable D r based on (11) in every subnet. For example, the formula for D 0 of SMN 1 is denoted as: D 0 = t 1 ∨ hp 2 ∨ t 2 ∨ hp 4 Since the variable q 0 is equal to 1 – given the code for the places p 2 , and p 4 – the formula D 0 is a disjunction of all the input transition conjunctions of these places. In the considered case these are denoted t 1 , and t 2 . Also, a conjunction of hold conditions for all places has to be added. In a similar way we form the remaining formulas for D 1 and D 2 , and D 0 , D 1 and D 2 of SMN 2 , and D 0 and D 1 of SMN 3 . These formulas can INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR INTEGRATED CIRCUITS AND SYSTEMS, VOL. 4, NO. 2, DECEMBER 2013 7 TABLE II T ABLES OF DECODER OPERATIONS Decoder Y 1 Decoder Y 2 Decoder Y 3 Address Operation Address Operation Address Operation q 2 q 1 q 0 Y 1 q 2 q 1 q 0 Y 2 q 1 q 0 Y 3 000 10000 000 001000 00 100 001 00010 001 000100 01 010 011 00100 011 000010 11 001 010 01000 010 010000 110 00101 110 100001 Y 1 = yt 1 yt 2 yv 1 y p 2 Z y p 6 Z Y 2 = yv 3 ym y p 3 Z y dmp 1 Z y p 7 Z y p 11 Z Y 2 = yv 2 y p 8 Z y dmp 2 Z be obviously minimized after putting conjunctions instead of the corresponding variables. We are now ready to create the decoder memory blocks (step 6). Each of the subnets requires a separate table. Table II shows three such tables in relation to the considered example. Finally, the logic circuit can be formed (step 7). Each SMN i circuit can be easily described in any HDL. Our examples was described in Verilog. The process of the description is illustrated based on SMN 1 . All other SMN i circuit have to be described in the same way. The conjunctions were described in separate file (Fig. 6) and then included into the combinational module CC 1 . The combinational module was described using continues assignments (Fig. 7). The memory register RG 1 was described as an 3-bits, D-type with asynchronous reset, which is triggered by a positive edge (Fig. 8). There was used topical synthesis template [27]. The decoder Y 1 was described as a process using of the case statement (Fig. 9), as it was mentioned earlier. In our example it is targeted into Xilnix Spartan or Virtex devices. It is important for this circuit because it have to implemented into embedded memory blocks. While, each family of FPGA devices has different memory blocks this circuit have to be targeted into specific family. The decoder is a synchronous one with asynchronous reset because embedded memory blocks of Xilnix devices, called BlockRAM, required such behavior. It is triggered by a negative edge. The description of this module should include special synthesis attribute bram_map for the use of BlockRAMs durnig the synthesis & implementation process. The top-level module of the SMN 1 subnet should describe connections between these three components using instanti- ation mechanism (Fig. 10) based on the schematic shown in figure 2. The local clock and reset signal have to be connected to the memory RG and the decoder Y. All SMN i modules do not have to be connected together in any module because they are going to be implemented in separate devices. But, for simulation purpose, there was created the main top-level module according to the schematic in figure 1. Then the simple test-bench for this main top- level module was written. This test-bench emulate the control process of mixer (Fig. 4). It generate all information about state of tanks ( xf 3 ), scale ( xf 1 , xn 1 , xn 2 ), timer ( xf 4 ) and flow meter ( xf 2 ). The sample simulation (Fig. 11) shows one cycle of the process. When simulation results are correct, we are ready to pass module Y1 (CLK, RES , YT1 , YT2 , YV1 , YZP2 , YZP6 , Q) ; i n p u t CLK, RES ; i n p u t [ 2 : 0 ] Q; o u t p u t YT1 , YT2 , YV1 , YZP2 , YZP6 ; r e g YT1 , YT2 , YV1 , YZP2 , YZP6 ; / / s y n t h e s i s a t t r i b u t e bram map o f Y1 i s y e s a l w a y s @( negedge CLK) i f ( RES ) { YT1 , YT2 , YV1 , YZP2 , YZP6 } = 5 ’ b00000 ; e l s e c a s e (Q) 3 ’ b000 : { YT1 , YT2 , YV1 , YZP2 , YZP6 } = 5 ’ b10000 ; 3 ’ b001 : { YT1 , YT2 , YV1 , YZP2 , YZP6 } = 5 ’ b00010 ; 3 ’ b011 : { YT1 , YT2 , YV1 , YZP2 , YZP6 } = 5 ’ b00100 ; 3 ’ b010 : { YT1 , YT2 , YV1 , YZP2 , YZP6 } = 5 ’ b01000 ; 3 ’ b110 : { YT1 , YT2 , YV1 , YZP2 , YZP6 } = 5 ’ b00101 ; d e f a u l t : { YT1 , YT2 , YV1 , YZP2 , YZP6 } = 5 ’ b00000 ; e n d c a s e endmodule Fig. 9. Verilog description of decoder Y of SMN 1 module SMN1 (CLK, RES , XF1 , XF2 , XN1 , XN2 , ZDMP1, ZP3 , YT1 , YT2 , YV1 , ZP2 , ZP6 ) ; i n p u t CLK, RES ; i n p u t XF1 , XF2 , XN1 , XN2 ; i n p u t ZDMP1, ZP3 ; o u t p u t YT1 , YT2 , YV1 ; o u t p u t ZP2 , ZP6 ; w i r e [ 2 : 0 ] D; w i r e [ 2 : 0 ] Q; CC1 CC ( . D(D) , . Q(Q) , . XF1 ( XF1 ) , . XF2 ( XF2 ) , . XN1(XN1) , . XN2(XN2) , . XZDMP1(ZDMP1) , . XZP3 ( ZP3 ) ) ; RG1 RG ( . CLK(CLK) , . RES ( RES ) , . D( D1 ) , . Q(Q) ) ; Y1 Y ( . CLK(CLK) , . RES ( RES ) , . Q(Q) , . YT1 ( YT1 ) , . YT2 ( YT2 ) , . YV1(YV1) , . YZP2 ( ZP2 ) , . YZP6 ( ZP6 ) ) ; endmodule Fig. 10. Verilog description of decoder Y of SMN 1 it on to the third party synthesis & implementation tools. The results for Xilnix Spartan device are shown in table III. The entire control system can be set up on the basis of the obtained circuit. VI. C ONCLUSIONS The paper presents a method of distributed control system realization. A formal description of the method is then accom- panied with a simple example. The specification of the control algorithm uses the notion of a Petri net, which allows an easy description of parallel processes. We note that it is possible to apply formal verification methods to test the algorithm. The proposed method of synthesis is based on the decomposition of INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR INTEGRATED CIRCUITS AND SYSTEMS, VOL. 4, NO. 2, DECEMBER 2013 8 Fig. 11. Simulation of sample Petri net PN 1 TABLE III R ESOURCES OF LOGIC CIRCUIT OF P ETRI NET PN 1 SMN 1 SMN 2 SMN 3 Number of LUTs 6 6 3 Number of Flip-Flops 3 3 2 Number of BRAMs 1 1 1 a Petri net into SM subnets. The architecture for the distributed control system is based on the local synchronization of each of the SM subnets. There is no global synchronization however, which means that the entire system is of GALS type. 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