Page 1 JOB DESCRIPTION VLSI Technology Very Large Scale Integration Semiconductor Division - 2, N agarbhavi, Bengaluru www.vlsiind.in Semiconductor R&D wing NOTE: Best performers will be awarded the privilege of pursuing an M.Tech in Nanotechnology. 1. Company Profile VLSI Technology is a core VLSI Design Company with nearly two decades of expertise in core VLSI Design, Semiconductors and SoC chip Design with a strong focus on R&D in Product Design and Development, we cater to the Indian market by offering a diverse ran ge of innovative products in Healthcare, Aerospace Engineering domain. 2. Our Areas of Expertise VLSI Design, Semiconductors, SoC6, SoC7, 760nm Technology, Chipset AI Studio, Chiplet 3D Integration and Embedded Design Hardware and Software. 3. Job Title: AI Architect Engineer Job Entry Type: Research - Based Inter n 4. Target Students: Bachelor’s and Master’s degree in Electronics & Communication (ECE), Electrical Engineering, or Computer Engineering. 5. CTC: 6 LPA to 7 LPA 6. Duration of Internship: 4 to 6 months Page 2 7. Prerequisites (Qualifications & Skills) To qualify for this role in the AI Architect Engineer domain, you need a strong foundation in AI system design, large - scale architectures, and advanced machine learning concepts. Required Knowledge: • Strong understanding of AI and machine learning fundamentals , including supervised/unsupervised learning, deep learning architectures, and model evaluation techniques. • Expertise in designing scalable AI architectures , including data pipelines, model training workflows, inference systems, and integration with enterprise applications. • Proficiency in programming for AI systems , primarily using Python and familiarity with C/C++ or Java for performance - critical components. • In - depth knowledge of deep learning frameworks and ecosystems , such as PyTorch, TensorFlow , and model optimization tools for training and deployment. • Experience with cloud - native AI platforms and distributed computing , including GPU/TPU utilization, containerization, and orchestration for large - scale AI workloads. • Awareness of MLOps practices , including model versioning, CI/CD for ML, monitoring, governance, and lifecycle management of AI models in production. • Strong understanding of performance, scalability, and cost optimization , including latency, throughput, resource utilization, and energy efficiency in AI systems. 8. Location: Usually onsite/CoE established at College/Universities (requires lab access for usage of components/boards), any company division across INDIA 9. Experience Level: 0 – 2 years (Entry - Level / Junior). 10. Job Role (Responsibilities): As an AI Architect Engineer , you will support the end - to - end lifecycle of AI systems, from initial architecture design and model selection to large - scale deployment and continuous optimization. AI System Architecture Design: Defining end - to - end AI system architectures, including data pipelines, model training workflows, inference engines, and integration with enterprise or edge platforms. Page 3 Model Strategy & Framework Selection: Collaborating with data scientists and engineers to select appropriate machine learning and deep learning models, frameworks, and hardware accelerators based on performance and scalability requirements. Hardware – Software Co - Design: Working closely with hardware, platform, and infrastructure teams to align AI workloads with underlying compute architectures (CPU, GPU, accelerator, cloud, or edge systems). Deployment & MLOps Enablement: Designing and enabling production - ready AI deployments, including CI/CD for ML, model versioning, monitoring, and lifecycle management. Testing & Validation: Validating AI systems for accuracy, robustness, scalability, and reliability across training and inference environments. Optimization: Optimizing AI workloads for performance, cost, and energy efficiency, including latency reduction, throughput improvement, and efficient resource utilization. Documentation: Creating architectural blueprints, technical specifications, and best - practice guidelines for AI system design and usage by engineering teams and stakeholders. 11. Onboarding Onboarding in a semiconductor firm is often more rigorous than in standard IT roles due to the high cost of chip manufacturing. Technical Induction/Free of Cost Training: A 4 - 6 months deep - dive into the company’s proprietary SoC Architecture and internal EDA (Electronic Design Automation) tool flows under PIE(Performance in Evaluation) model during which three assessments will be given out of which it is mandatory to clear two assessments. NDA & IP Protection: Strict legal agreements regarding Intellectual Property (IP); you will be working on designs that are often 2 – 3 years away from hitting the Research market . Mentorship Period: You will typically be assigned a "Buddy" or "Mentor" (Senior Design Engineer) for the first 6 months to oversee your code commits. Lab Safety & Protocol: Training on handling sensitive silicon wafers or Evaluation Boards (EVBs) to prevent Electrostatic Discharge (ESD) damage. Probationary Project: Completion of a "Pilot Project" such as developing a driver for a new sensor interface to demonstrate competency. The Industry Reality: In the VLSI domain, a mistake in your embedded code can sometimes be fixed with a software patch, but a mistake in how that code interacts with the hardware logic might require a multi - million dollar "re - spin" of the chip. This is why accuracy and attention to Page 4 detail are the most valued soft skills in this JD. Note: Job roles and responsibilities are not limited to above specifications; the roles vary as per the company requirement and demand of client. The candidate should be flexible to adapt as per company requirement anywhere anytime. Shortlisted and selected stud ents are required to sign a Consent Form and a Non - Disclosure Agreement (NDA) before proceeding. The stated CTC applies only to candidates who clear all eligibility rounds and criteria in Annexure - I. If you are a referred candidate or applied via off - campus recruitment process or through internship model, you will be entering VLSI Technology as an internee under PIE model (Performance In Evaluation). Placement Process 1. Interaction with HoD of ECE/Principal/Placement Team/Dean/Directors Duration: 20mins Requirement from College: White board/ Smart Board 2. Preplacement Talk Requirement from College: Projector and Laptop 3. Round 1: Pen and Paper Mode Technical Aptitude (Objective type, 30questions*4marks each=120marks (securing 72 marks is mandatory out of 120 marks to get eligibility for Round - 2). 30 questions, each question carries 4 marks, and every wrong answer will be evaluated for - 1 marks. Duration: 30mins Requirement from college: OMR sheets need to be printed based on the number of attendees 4 Round 2: Task - based Coding – Open Book Coding Test A Simple Problem statement (PS) will be given. The candidate must complete the coding for the given PS in the stipulated time (Open book coding – any AI tools like ChatGPT, Google Gemini, Perplexity etc can be used) Requirement from college: Number of Systems based on the number of candidates eligible for the 2nd round, white board/Smart board Duration: 45mins 5. Round 3: HR, NDA Signing and Consent Round (Domain & Project Selection) One to One discussion about any query by the candidate (Eg: any location specific, any medical illness etc) Page 5 12. POST - SELECTION FLOW Internship Selection Process Selection Of internee [ With Stipend/ Without Stipend ] Duration 4 to 6 months [Three Internal Assessment is mandatory ] Probation ary Period Duration 10 months [Stipend Applicable] [Three Internal Assessment is mandatory ] During Probationary Period [Three Internal Assessment is mandatory ] Compulsory to p ass any two test internal assessment Permanent Employee [ CTC Applicable ] Page 6 13. Stipend Module Note: 1. We would like to clarify that we are not a job consultancy, nor do we operate as a training institute. 2. It is strongly suggested that Training and Placement Officers (TPOs) visit our office once prior to confirming any recruitment drive. Round Score Range / Criteria Result Stipend Round 1 < 72 Rejected No Stipend Round 1 72 to 82 Shortlisted to Round 2 Rs. 5,000/ - Round 1 82 to 92 Shortlisted to Round 2 Rs. 8,000/ - Round 1 92 to 102 Shortlisted to Round 2 Rs. 16,000/ - Round 1 102 to 120 Shortlisted to Round 2 Rs. 32,000/ - Page 1 JOB DESCRIPTION VLSI Technology Very Large Scale Integration Semiconductor Division - 2, Nagarbhavi, Bengaluru www.vlsiind.in Semiconductor R&D wing 1. Company Profile VLSI Technology is a core VLSI Design Company with nearly two decades of expertise in core VLSI Design, Semiconductors and SoC chip Design with a strong focus on R&D in Product Design and Development, we cater to the Indian market by offering a diverse range of innovative products in Healthcare, Aerospace Engineering domain. 2. Our Areas of Expertise VLSI Design, Semiconductors, SoC6, SoC7, 760nm Technology, Chipset AI Studio, Chiplet 3D Integration and Embedded Design Hardware and Software. 3. Job Title: Embedded Design Engineer Job Entry Type : Research - Based Inter n 4. Target Students: Bachelor’s and Master’s degree in Electronics & Communication (ECE), Electrical Engineering, or Computer Engineering. 5. CTC: 5 LPA to 6 LPA 6. Duration of Internship: 4 to 6 months NOTE: Best performers will be awarded the privilege of pursuing an M.Tech in Nanotechnology. Page 2 7. Prerequisites (Qualifications & Skills) To qualify for this role in the Embedded Design Engineer domain, you need a strong foundation in embedded hardware design, system - level understanding, and low - level software fundamentals Required Knowledge: • Strong understanding of embedded system architecture , including microcontrollers, microprocessors, SoCs, and memory hierarchies. • Familiarity with digital and analog electronics fundamentals , including logic circuits, power supply design, clocking, and signal integrity basics. • Working knowledge of schematic design and PCB fundamentals , including component selection, board layout concepts, and hardware bring - up considerations. • Proficiency in C/C++ for embedded software development , with an understanding of bare - metal programming and hardware abstraction layers. • Exposure to common communication protocols , such as I2C, SPI, UART, CAN, Ethernet, and USB , and their hardware and software integration. • Awareness of hardware – software co - design principles , including interfacing firmware with hardware, debugging board - level issues, and collaborating with firmware teams. • Basic understanding of performance, power, and thermal considerations , including low - power design techniques, timing constraints, and reliability in embedded systems. 8. Location: Usually onsite/CoE established at College/Universities (requires lab access for usage of components/boards) , any company division across INDIA 9. Experience Level: 0 – 2 years (Entry - Level / Junior). 10. Job Role (Responsibilities): As an Embedded Design Engineer , you will support the complete lifecycle of embedded system development, from initial hardware design and system architecture to board bring - up, validation, and optimization. Embedded Hardware Design: Designing embedded hardware systems including microcontroller - or SoC - based architectures, peripheral selection, power management, and interface planning. Schematic & PCB Design: Creating schematics and supporting PCB layout activities, Page 3 ensuring signal integrity, power integrity, and compliance with design specifications. Hardware – Software Co - Design: Collaborating closely with embedded software and firmware teams to ensure hardware design aligns with software requirements and system functionality. Board Bring - Up & Validation: Assisting in board bring - up activities, validating hardware functionality, and supporting initial testing of embedded platforms. Testing & Debugging: Identifying and resolving hardware - level issues using debugging tools such as oscilloscopes, logic analyzers, and multimeters. Optimization: Optimizing embedded designs for PPA (Power, Performance, and Area), ensuring reliability, thermal stability, and efficient power consumption. Documentation: Creating and maintaining technical documentation including schematics, design specifications, interface descriptions, and hardware validation reports for internal teams and end users. 11. Onboarding Onboarding in a semiconductor firm is often more rigorous than in standard IT roles due to the high cost of chip manufacturing. Technical Induction/Free of Cost Training: A 4 - 6 months deep - dive into the company’s proprietary SoC Architecture and internal EDA (Electronic Design Automation) tool flows under PIE(Performance in Evaluation) model during which three assessments will be given out of which it is mandatory to clear two assessments. NDA & IP Protection: Strict legal agreements regarding Intellectual Property (IP); you will be working on designs that are often 2 – 3 years away from hitting the Research market . Mentorship Period: You will typically be assigned a "Buddy" or "Mentor" (Senior Design Engineer) for the first 6 months to oversee your code commits. Lab Safety & Protocol: Training on handling sensitive silicon wafers or Evaluation Boards (EVBs) to prevent Electrostatic Discharge (ESD) damage. Probationary Project: Completion of a "Pilot Project" such as developing a driver for a new sensor interface to demonstrate competency. The Industry Reality: In the VLSI domain, a mistake in your embedded code can sometimes be fixed with a software patch, but a mistake in how that code interacts with the hardware logic might require a multi - million dollar "re - spin" of the chip. This is why accuracy and attention to detail are the most valued soft skills in this JD. Page 4 Note: Job roles and responsibilities are not limited to above specifications; the roles vary as per the company requirement and demand of client. The candidate should be flexible to adapt as per company requirement anywhere anytime. Shortlisted and selected students are required to sign a Consent Form and a Non - Disclosure Agreement (NDA) before proceeding. The stated CTC applies only to candidates who clear all eligibility rounds and criteria in Annexure - I. If you are a referred candidate or applied via off - campus recruitment process or through internship model, you will be entering VLSI Technology as an internee under PIE model (Performance In Evaluation). Placement Process 1. Interaction with HoD of ECE/Principal/Placement Team/Dean/Directors Duration: 20mins Requirement from College: White board/ Smart Board 2. Preplacement Talk Requirement from College: Projector and Laptop 3. Round 1: Pen and Paper Mode Technical Aptitude (Objective type, 30questions*4marks each=120marks (securing 72 marks is mandatory out of 120 marks to get eligibility for Round - 2). 30 questions, each question carries 4 marks, and every wrong answer will be evaluated for - 1 marks. Duration: 30mins Requirement from college: OMR sheets need to be printed based on the number of Attendees 4. Round 2: Task - based Coding – Open Book Coding Test A Simple Problem statement (PS) will be given. The candidate must complete the coding for the given PS in the stipulated time (Open book coding – any AI tools like ChatGPT, Google Gemini, Perplexity etc can be used) Requirement from college: Number of Systems based on the number of candidates eligible for the 2nd round, white board/Smart board Duration: 45mins Page 5 5. Round 3: HR, NDA Signing and Consent Round (Domain & Project Selection) One to One discussion about any query by the candidate (Eg: any location specific, any medical illness etc) 12. POST - SELECTION FLOW Internship Selection Process Selection Of internee [ With Stipend/ Without Stipend ] Duration 4 to 6 months [Three Internal Assessment is mandatory ] Probationar y Period Duration 10 months [Stipend Applicable] [Three Internal Assessment is mandatory ] During Probationary Period [Three Internal Assessment is mandatory ] Compulsory Pass any two test internal assessment Permanent Employee [ CTC Applicable ] Page 6 13. Stipend Module Note: 1. We would like to clarify that we are not a job consultancy, nor do we operate as a training institute. 2. It is strongly suggested that Training and Placement Officers (TPOs) visit our office once prior to confirming any recruitment drive. Round Score Range / Criteria Result Stipend Round 1 < 72 Rejected No Stipend Round 1 72 to 82 Shortlisted to Round 2 Rs. 5,000/ - Round 1 82 to 92 Shortlisted to Round 2 Rs. 8,000/ - Round 1 92 to 102 Shortlisted to Round 2 Rs. 16,000/ - Round 1 102 to 120 Shortlisted to Round 2 Rs. 32,000/ - Page 1 JOB DESCRIPTION VLSI Technology Very Large Scale Integration Semiconductor Division - 2, Nagarbhavi, Bengaluru www.vlsiind.in Semiconductor R&D wing 1. Company Profile VLSI Technology is a core VLSI Design Company with nearly two decades of expertise in core VLSI Design, Semiconductors and SoC chip Design with a strong focus on R&D in Product Design and Development, we cater to the Indian market by offering a diverse range of innovative products in Healthcare, Aerospace Engineering domain. 2. Our Areas of Expertise VLSI Design, Semiconductors, SoC6, SoC7, 760nm Technology, Chipset AI Studio, Chiplet 3D Integration and Embedded Design Hardware and Software. 3. Job Title: Embedded software engineer Job Entry Type : Research - Based Inter n 4. Target Students: Bachelor’s and Master’s degree in Electronics & Communication (ECE), Electrical Engineering, or Computer Engineering. 5. CTC: 4 LPA to 5 LPA 6. Duration of Internship: 4 to 6 months NOTE: Best performers will be awarded the privilege of pursuing an M.Tech in Nanotechnology. Page 2 7. Prerequisites (Qualifications & Skills) To qualify for this role in the Embedded Software Engineer domain, you need a strong foundation in embedded systems, low - level programming, and real - time software fundamentals Required Knowledge: • Strong understanding of embedded system fundamentals , including microcontrollers, SoCs, memory maps, boot processes, and peripheral architecture. • Proficiency in C/C++ for embedded software development , with experience in bare - metal programming and hardware abstraction layers (HAL). • Familiarity with communication protocols , such as I2C, SPI, UART, CAN, Ethernet, and USB , and their implementation in embedded software. • Exposure to Real - Time Operating Systems (RTOS) like FreeRTOS, Zephyr, or Embedded Linux , including task scheduling, interrupts, timers, and synchronization mechanisms. • Working knowledge of hardware – software interaction , including register - level programming, interrupt handling, and reading datasheets and reference manuals. • Experience or exposure to debugging and testing tools , such as JTAG, SWD, logic analyzers, and in - circuit debuggers , for firmware validation. • Basic understanding of performance, power, and memory optimization , including low - power modes, timing constraints, and efficient resource utilization in embedded systems. 8. Location: Usually onsite/CoE established at College/Universities (requires lab access for usage of components/boards) , any company division across INDIA 9. Experience Level: 0 – 2 years (Entry - Level / Junior). 10. Job Role (Responsibilities): As an Embedded Software Engineer , you will support the complete lifecycle of embedded software development, from initial system bring - up and low - level programming to validation, optimization, and maintenance. Firmware & Driver Development: Writing and maintaining low - level firmware and bare - metal/RTOS - based drivers for peripherals such as I2C, SPI, UART, CAN, Ethernet, and USB. Hardware – Software Co - Design: Collaborating closely with hardware, RTL, and embedded design teams to ensure software aligns with hardware architecture, register maps, and system requirements. Page 3 Board Support Package (BSP): A ssisting in bring - up of new hardware platforms by developing and porting BSPs and Real - Time Operating Systems (RTOS) such as FreeRTOS, Zephyr, or Embedded Linux. Testing & Debugging: Identifying and resolving issues at the hardware – software interface using JTAG/SWD debuggers, logic analyzers, and hardware - in - the - loop (HIL) testing. O p t i m i z a t i o n : Optimizing embedded software for PPA (Power, Performance, and Area), ensuring efficient memory usage, real - time responsiveness, and low power consumption. System Integration & Validation: Integrating firmware with higher - level software stacks and validating system functionality across different operating modes. Documentation: Creating and maintaining technical documentation including API specifications, register - level documentation, and software design descriptions for internal teams and end users. 11. Onboarding Onboarding in a semiconductor firm is often more rigorous than in standard IT roles due to the high cost of chip manufacturing. Technical Induction/Free of Cost Training: A 4 - 6 months deep - dive into the company’s proprietary SoC Architecture and internal EDA (Electronic Design Automation) tool flows under PIE(Performance in Evaluation) model during which three assessments will be given out of which it is mandatory to clear two assessments. NDA & IP Protection: Strict legal agreements regarding Intellectual Property (IP); you will be working on designs that are often 2 – 3 years away from hitting the Research market . Mentorship Period: You will typically be assigned a "Buddy" or "Mentor" (Senior Design Engineer) for the first 6 months to oversee your code commits. Lab Safety & Protocol: Training on handling sensitive silicon wafers or Evaluation Boards (EVBs) to prevent Electrostatic Discharge (ESD) damage. Probationary Project: Completion of a "Pilot Project" such as developing a driver for a new sensor interface to demonstrate competency. The Industry Reality: In the VLSI domain, a mistake in your embedded code can sometimes be fixed with a software patch, but a mistake in how that code interacts with the hardware logic might require a multi - million dollar "re - spin" of the chip. This is why accuracy and attention to detail are the most valued soft skills in this JD. Page 4 Note: Job roles and responsibilities are not limited to above specifications; the roles vary as per the company requirement and demand of client. The candidate should be flexible to adapt as per company requirement anywhere anytime. Shortlisted and selected students are required to sign a Consent Form and a Non - Disclosure Agreement (NDA) before proceeding. The stated CTC applies only to candidates who clear all eligibility rounds and criteria in Annexure - I. If you are a referred candidate or applied via off - campus recruitment process or through internship model, you will be entering VLSI Technology as an internee under PIE model (Performance In Evaluation). Placement Process 1. Interaction with HoD of ECE/Principal/Placement Team/Dean/Directors Duration: 20mins Requirement from College: White board/ Smart Board 2. Preplacement Talk Requirement from College: Projector and Laptop 3. Round 1: Pen and Paper Mode Technical Aptitude (Objective type, 30questions*4marks each=120marks (securing 72 marks is mandatory out of 120 marks to get eligibility for Round - 2). 30 questions, each question carries 4 marks, and every wrong answer will be evaluated for - 1 marks. Duration: 30mins Requirement from college: OMR sheets need to be printed based on the number of attendees 4. Round 2: Task - based Coding – Open Book Coding Test A Simple Problem statement (PS) will be given. The candidate must complete the coding for the given PS in the stipulated time (Open book coding – any AI tools like ChatGPT, Google Gemini, Perplexity etc can be used) Requirement from college: Number of Systems based on the number of candidates eligible for the 2nd round, white board/Smart board Duration: 45mins 5. Round 3: HR, NDA Signing and Consent Round (Domain & Project Selection) One to One discussion about any query by the candidate (Eg: any location specific, any medical illness etc) Page 5 12. POST - SELECTION FLOW Internship Selection Process Selection Of internee [ With Stipend/ Without Stipend ] Duration 4 to 6 months [Three Internal Assessment is mandatory ] Probationar y Period Duration 10 months [Stipend Applicable] [Three Internal Assessment is mandatory ] During Probationary Period [Three Internal Assessment is mandatory ] Compulsory Pass any two test internal assessment Permanent Employee [ CTC Applicable ] Page 6 13. Stipend Module Note: 1. We would like to clarify that we are not a job consultancy, nor do we operate as a training institute. 2. It is strongly suggested that Training and Placement Officers (TPOs) visit our office once prior to confirming any recruitment drive. Round Score Range / Criteria Result Stipend Round 1 < 72 Rejected No Stipend Round 1 72 to 82 Shortlisted to Round 2 Rs. 5,000/ - Round 1 82 to 92 Shortlisted to Round 2 Rs. 8,000/ - Round 1 92 to 102 Shortlisted to Round 2 Rs. 16,000/ - Round 1 102 to 120 Shortlisted to Round 2 Rs. 32,000/ - Page 1 JOB DESCRIPTION VLSI Technology Very Large Scale Integration Semiconductor Division - 2, Nagarbhavi, Bengaluru www.vlsiind.in Semiconductor R&D wing NOTE: Best performers will be awarded the privilege of pursuing an M.Tech in Nanotechnology. 1. Company Profile VLSI Technology is a core VLSI Design Company with nearly two decades of expertise in core VLSI Design, Semiconductors and SoC chip Design with a strong focus on R&D in Product Design and Development, we cater to the Indian market by offering a diverse range of innovative products in Healthcare, Aerospace Engineering domain. 2. Our Areas of Expertise VLSI Design, Semiconductors, SoC6, SoC7, 760nm Technology, Chipset AI Studio, Chiplet 3D Integration and Embedded Design Hardware and Software. 3. Job Title: Firmware Engineer Job Entry Type : Research - Based Internee 4. Target Students: Bachelor’s and Master’s degree in Electronics & Communication (ECE), Electrical Engineering, or Computer Engineering. 5. CTC: 4 LPA to 5 LPA 6. Duration of Inte r nship: 4 to 6 months Page 2 7. Prerequisites (Qualifications & Skills) To qualify for this role in the Firmware Engineer domain, you need a strong foundation in embedded systems, low - level programming, and hardware interaction fundamentals. Required Knowledge: • Strong understanding of embedded systems architecture , including microcontrollers, SoCs, memory maps, and peripheral interfaces. • Proficiency in C/C++ for firmware development , with experience in bare - metal programming and low - level hardware control. • Familiarity with communication protocols , such as I2C, SPI, UART, CAN, and USB , and their implementation in firmware. • Exposure to Real - Time Operating Systems (RTOS) like FreeRTOS, Zephyr, or Embedded Linux , including task scheduling, interrupts, and synchronization mechanisms. • Working knowledge of hardware – software interaction , including reading datasheets, configuring registers, and interfacing with sensors and peripherals. • Experience or exposure to debugging tools and techniques , such as JTAG, SWD, logic analyzers, and oscilloscopes , for firmware validation and issue resolution. • Basic understanding of performance, power, and memory optimization , including low - power modes, timing constraints, and efficient resource utilization on embedded platforms. 8. Location: Usually onsite/CoE established at College/Universities (requires lab access for usage of components/boards) , any company division across INDIA 9. Experience Level: 0 – 2 years (Entry - Level / Junior). 10. Job Role (Responsibilities): As a Firmware Engineer , you will support the complete lifecycle of firmware development, from early hardware bring - up and low - level programming to validation, optimization, and long - term maintenance. Firmware & Driver Development: Developing and maintaining bare - metal and low - level firmware drivers for peripherals such as I2C, SPI, UART, CAN, Ethernet, and USB Hardware – Software Co - Design: Collaborating closely with hardware, RTL, and SoC design teams to ensure firmware aligns with hardware architecture, register definitions, and system requirements. Board Support Package (BSP): Assisting in bring - up of new hardware platforms by developing