TIMING ANALYSIS OF DIGITAL CIRCUITS Dr. Sudeendra kumar K Department of Electronics and Communication Engineering 1 SYNTHESIS, PD AND TIMING ANALYSIS Reliability Issues in MOSFETs Sudeendra kumar K Department of Electronics and Communication Engineering Unit-5: Session I 2 Timing Analysis of Digital Circuits • Reliability in Chip Design • Problems • Solutions • Reliability issues due to Radiation effects in Electronics • Problems • Solutions • Reliability in Embedded Systems • Problems • Solutions 3 Reliability in MOSFETs and Chip Design Timing Analysis of Digital Circuits Motivation 4 • Reliability important for • Normal user • Medical applications • Cars • Air / Space Environment Timing Analysis of Digital Circuits Motivation 5 Prof. Sill Timing Analysis of Digital Circuits Motivation 6 Probability for failures increases due to: Increasing transistor count Shrinking technology 130 nm 90 nm 65 nm 45 nm 0 nm 50 nm 100 nm 150 nm 0 100 200 300 400 500 2002 2004 2006 2008 Technology Transistors [Mill.] Year Prof. Sill Timing Analysis of Digital Circuits Process Failures 7 Occur at production phase • Based on • Process Variations • Particles • ... Timing Analysis of Digital Circuits Random Dopant Fluctuations Prof. Sill 8 10 100 1000 10000 1000 500 250 130 65 32 Technology Node (nm) Mean Number of Dopant Atoms Uniform Non-uniform Power Density Timing Analysis of Digital Circuits 9 Prof. Sill Sun’s Surface 4004 8008 8080 8085 8086 286 386 486 Pentium® P4 1 10 100 1000 10000 1970 1980 1990 2000 2010 Year Power Density (W/cm2) Hot Plate Nuclear Reactor Rocket Nozzle Prescott Pentium® Temperature Variations Timing Analysis of Digital Circuits 10 Power Map On-Die Temperature • Power density is not uniformly distributed across the chip • Silicon is not a good heat conductor • Max junction temperature is determined by hot-spots • Impact on packaging, cooling Prof. Sill Temperature Variations Timing Analysis of Digital Circuits 11 • Power4 Server Chip Prof. Sill Temperature Variations Timing Analysis of Digital Circuits 12 Prof. Sill • Threshold voltage Vth changes with temperature drain-source current changes delay changes sudeendrakumark@pes.edu THANK YOU Prof. Sudeendra kumar K Department of Electronics and Communication Engineering 13 Synthesis, PD and Timing Analysis of Digital Circuits Dr. Sudeendra kumar K Department of Electronics and Communication Engineering 1 TIMING ANALYSIS OF DIGITAL CIRCUITS MOSFET Reliability Issues -II Sudeendra kumar K Department of Electronics and Communication Engineering Unit-5: Session II & III 2 Timing Analysis of Digital Circuits Contents of this Session • Reliability in Chip Design • Electromigration • Hot Carriers • Electrostatic Discharge • Reliability Testing and Screening 3 Timing Analysis of Digital Circuits Reliability in Chip Design 4 Design for Manufacturability, Sandip Kundu • Scaling of feature size coupled with variability in manufacturing process has lead to increased reliability problems. • In satellite and space systems, or in mission-critical applications, product life expectations may be much longer. In order to improve the reliability of semiconductor products, the underlying failure mechanisms must be clearly understood. • Physical corrosion due to leaks and moisture, electrical leakage, package encapsulation problems, and/or loose bonding are examples of manufacturing issues that degrade IC reliability. • High-current density, improper input/output (IO) terminations, and poorly designed heat sinks are examples of chip and package design issues that contribute to reliability failures. Timing Analysis of Digital Circuits Reliability 5 • A device is said to be reliable if it performs intended operations under a given set of conditions over its scheduled lifetime. • Variation in manufacturing process parameters, when coupled with designs that are not “margined” adequately, may lead to reliability failures before the design’s expiration date. • Each product from a manufacturing line may fail at a different time. Thus, mean time to failure (MTTF) is the reliability measure used to describe useful product life. • A related measure is shipped product quality level (SPQL), which quantifies the number of bad chips per million at the beginning of and at various points in a product’s life. • Mortality rate is defined as the ratio of the number of chips failing during a specified time interval to the total number of chips. Whereas the MTTF indicates a product’s expected lifetime, the mortality rate is a better indicator of the failure pattern. Timing Analysis of Digital Circuits Different Phases of Reliability failures 6 • The reliability failures that occur during the lifetime of an IC can be categorized into three phases: - • Early-lifetime failures (aka infant mortality); • Normal-lifetime random failures; and • End-of lifetime wear-out failures. • When plotted on a graph of time versus mortality, the IC lifetime phases form a “bathtub” curve. Timing Analysis of Digital Circuits Infant Mortality 7 • Infant mortality occurs during the early stage of a product’s life. • The most frequent causes of infant mortality are manufacturing imperfections. • A manufacturing stress test is applied to accelerate infant mortality, so that products leaving the factory do not fail early at the customer’s site. • This stress test is also known as the burn-in test or shake-and- bake test, terminologies that are associated with the stress conditions applied.